CN112331255B - Verification statistical circuit and method of 3D NAND memory and 3D NAND memory - Google Patents
Verification statistical circuit and method of 3D NAND memory and 3D NAND memory Download PDFInfo
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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- G—PHYSICS
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
Abstract
The invention provides a verification statistical circuit of a 3D NAND memory, a verification statistical method of the 3D NAND memory and the 3D NAND memory, in the verification statistical circuit of the 3D NAND memory provided by the invention, reference currents with various sizes can be output by controlling and adjusting a reference current control unit through a data signal output by a data register output unit, based on the reference currents with various sizes, write-in failure summary currents can be subjected to successive approximation comparison and output, from high to low, and the output is a weighted code without decoding conversion by a decoder, the circuit structure and the logic principle are simple, and the verification statistics of the number of write-in failure storage units in the 3D NAND memory can be quickly and efficiently realized; in addition, the same quantization unit is shared during multiple comparisons, time-sharing multiplexing of the quantization unit is realized, the circuit structure is further simplified, and the area and the power consumption of a corresponding chip are reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor verification test, in particular to a verification statistical circuit and a verification statistical method of a 3D NAND memory and the 3D NAND memory.
Background
The 3D NAND memory is a technology for stacking data units, can realize the stacking of 32 layers and more of data units at present, overcomes the limit of practical extension limit of a plane memory, further improves the storage capacity, reduces the storage cost of each data bit, and reduces the energy consumption.
However, as the stack structure of the 3D NAND memory is more complicated in structural design, design requirements for write verification of memory cells therein are more and more high. At present, when counting the number of memory cells that fail to be written, it is necessary to count 2 for the case where the number of memory cells that fail to be written is nnThe quantization units perform quantization comparison and also require a decoder to perform code system conversion; when n increases, the required resources increase exponentially, and the occupied area and power consumption also increase sharply.
Therefore, how to simply, efficiently and low-power-consumption verify and count the number of failed write memory cells in the 3D NAND memory is an urgent problem to be solved at present.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a verification statistic solution for 3D NAND memory, which is used to solve the above-mentioned technical problems.
To achieve the above and other related objects, in a first aspect, the present invention provides a verification statistic circuit for a 3D NAND memory, for verifying and counting the number of memory cells with write failure in the 3D NAND memory, including:
the reference current control unit outputs a reference current with adjustable size;
the first input end of the quantization unit is connected with the write-in failure summary current, and the second input end of the quantization unit is connected with the output end of the reference current control unit;
the input end of the data register output unit is connected with the output end of the quantization unit, and the output end of the data register output unit is connected with the reference current control unit;
the input end of the accumulation counter is connected with the output end of the data register output unit;
the write-failure summary current is a summary current of the memory cells with a plurality of write failures.
Optionally, the reference current control unit includes n reference current control branches, and each of the reference current control branches includes a logic or gate and a reference current branch, respectively; in each reference current control branch, the output end of the logic or gate is connected with the reference current branch, and the reference current branch is controlled to be opened or closed by the input signal of the logic or gate; the output ends of the n reference current branches are connected together and used as the output end of the reference current control unit; wherein n is an integer of 1 or more.
Optionally, the logic or gate is a two-input logic or gate, a first input of which is connected to the clock signal, and a second input of which is connected to the data signal; the clock signals and the data signals accessed by the n logic OR gates are different.
Optionally, each reference current branch outputs a reference current, and the reference currents output by the n reference current branches are different; when n reference currents output by the n reference current branches are sequenced from large to small, the former reference current is 2 times of the latter reference current; the reference current is the sum of all or part of the n reference currents.
Optionally, the data register output unit includes n D flip-flops arranged in parallel, and data input ends of the n D flip-flops are respectively connected to the output end of the quantization unit; the n D flip-flops are connected with the n logic OR gates in a one-to-one correspondence mode: and the data latch output end of the D trigger outputs the data signal, and the clock input end of the D trigger is connected with the delay signal of the clock signal.
Optionally, the data latch output terminals of the n D flip-flops are respectively connected to the input terminal of the accumulation counter.
To achieve the above and other related objects, the present invention further provides a verification statistic method for a 3D NAND memory, for verifying and counting the number of failed memory cells in the 3D NAND memory, including:
providing a verification statistical circuit of the 3D NAND memory, forming a plurality of reference currents with adjustable sizes by using a plurality of reference currents in binary weighted relation based on a successive approximation comparison principle, and comparing the write-in failure summary current for a plurality of times and outputting the result.
Optionally, the verification statistical method of the 3D NAND memory further includes:
based on the time division multiplexing principle, the quantization unit is shared when multiple comparisons are carried out.
To achieve the above and other related objects, the present invention further provides a 3D NAND memory, which includes a memory array wafer and a CMOS circuit wafer, wherein the memory array wafer and the CMOS circuit wafer are bonded together, and the CMOS circuit wafer is provided with a verification statistic circuit of the 3D NAND memory.
As described above, the verification statistic circuit of the 3D NAND memory provided by the present invention has the following beneficial effects:
through the control and adjustment of the reference current control unit, reference currents with various sizes can be output, through the reference currents with various sizes, the write-in failure summary current can be subjected to successive approximation comparison and output from high to low, the output is weighted codes, decoding conversion is not needed, the circuit structure and the logic principle are simple, and the number verification statistics of write-in failure storage units in the 3D NAND memory is quickly and efficiently realized; in addition, the same quantization unit is shared during multiple comparisons, time-sharing multiplexing of the quantization unit is realized, the circuit structure is further simplified, and the area and the power consumption of a corresponding chip are reduced.
Drawings
FIG. 1 is a schematic diagram of a verification statistic circuit of a 3D NAND memory.
FIG. 2 shows a schematic diagram of a verification statistic circuit of a 3D NAND memory according to the present invention.
FIG. 3 is a diagram illustrating a verification statistic circuit for a two-bit 3D NAND memory according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating simulation statistics of the verification statistics circuit of the two-bit 3D NAND memory of FIG. 3.
Description of the reference numerals
I<0>、I<1>、…、I<2n-1>、I<n-2>、I<n-1>Reference current, I<Verok_q>- -write failure summary current, A<0>、A<1>、…、A<2n-1>-a non-weighted code DATA signal, DATA<0>、DATA<1>、…、DATA<n-1>-a binary code data signal, I<ref>Reference current, cnt<0>、cnt<1>、…、cnt<n-1>、cnt_delay<0>、cnt_delay<1>、…、cnt_delay<n-1>-a clock signal.
Detailed Description
The inventor researches and discovers that: conventionally, when counting the number of memory cells that fail to be written in a 3D NAND memory, as shown in fig. 1, it is necessary to count 2 for the case where the number of memory cells that fail to be written is nnA quantization unit(namely quantization unit 0, quantization units 1, …, quantization unit 2n-1) summing currents I separately for write failures<Verok_q>To perform a quantitative comparison, correspondingly, 2 is requirednA reference current (i.e. I)<0>、I<1>、…、I<2n-1>) Quantized to obtain a non-weighted code data signal A<0>、A<1>、…、A<2n-1>The decoder is also required to convert the non-weighted code into binary code to obtain n binary code DATA signals DATA<0>、DATA<1>、…、DATA<n-1>Finally, the n binary code data signals are accumulated and counted by an accumulation counter; when n increases, the required resources (especially quantization units) increase exponentially, and the occupied area and power consumption of the corresponding circuit also increase sharply.
Therefore, the present invention provides a verification statistical method for a 3D NAND memory, which is used for verifying and counting the number of memory cells with write failure in the 3D NAND memory, and comprises: on the basis of a successive approximation comparison principle, a plurality of reference currents in a binary weighted relation are utilized to form a plurality of reference currents with adjustable sizes, and the write-in failure summary currents are compared for a plurality of times and then output; based on the time-sharing multiplexing principle, the same quantization unit is shared when multiple comparisons are carried out.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. The structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are for understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined in the claims, and are not essential to the art, and any structural modifications, changes in proportions, or adjustments in size, which do not affect the efficacy and attainment of the same are intended to fall within the scope of the present disclosure. Meanwhile, the terms such as "unit" and "branch" used in the present specification are for clarity of description only, and are not used to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as the scope of the present invention.
As shown in fig. 2, the present invention provides a verification statistic circuit for a 3D NAND memory, for verifying and counting the number of memory cells with write failure in the 3D NAND memory, including:
a reference current control unit (shown by a dotted line frame at the lower part in FIG. 2) for outputting a reference current I < ref > with adjustable magnitude;
the first input end of the quantization unit is connected with the write-in failure summary current I < Verok _ q >, and the second input end of the quantization unit is connected with the output end of the reference current control unit;
a data register output unit (shown by a dotted line frame at the upper part in fig. 2), the input end of which is connected with the output end of the quantization unit, and the output end of which is connected with the reference current control unit;
the input end of the accumulation counter is connected with the output end of the data register output unit;
the write-failure summary current I < Verok _ q > is the summary current of a plurality of write-failure memory cells.
In detail, as shown in fig. 2, the reference current control unit includes n reference current control branches, each of which includes a logic or gate and a reference current branch, respectively; in each reference current control branch, the output end of the logic OR gate is connected with the reference current branch, and the reference current branch is controlled to be opened or closed through the input signal of the logic OR gate; the output ends of the n reference current branches are connected together and used as the output end of the reference current control unit; wherein n is an integer greater than or equal to 1, and the design can be flexibly selected according to the actual situation.
In detail, as shown in fig. 2, the logic or gate is a two-input logic or gate, a first input of which is connected to the clock signal, and a second input of which is connected to the data signal; the clock signals and the data signals accessed by the n logic OR gates are different.
In detail, as shown in fig. 2, each reference current branch outputs a reference current, and the reference currents output by the n reference current branches are different from each other; when n reference currents output by the n reference current branches are sequenced from large to small, the former reference current is 2 times of the latter reference current; the reference current I < ref > is the sum of all or part of the n reference currents.
In more detail, as shown in fig. 2, in the 1 st reference current control branch, a first input terminal of the logic or gate is connected to the clock signal cnt <0>, a second input terminal of the logic or gate is connected to the binary code DATA signal DATA < n-1>, an output terminal of the logic or gate is connected to the corresponding reference current branch, and the reference current branch outputs the reference current I < n-1 >; in the 2 nd reference current control branch circuit, the first input end of the logic OR gate is connected with a clock signal cnt <1>, the second input end of the logic OR gate is connected with a binary code DATA signal DATA < n-2>, the output end of the logic OR gate is connected with a corresponding reference current branch circuit, and the reference current branch circuit outputs a reference current I < n-2 >; by analogy, …; in the nth reference current control branch, the first input end of the logic OR gate is connected with the clock signal cnt < n-1>, the second input end of the logic OR gate is connected with the binary code DATA signal DATA <0>, the output end of the logic OR gate is connected with the corresponding reference current branch, and the reference current branch outputs the reference current I <0 >.
Wherein, I<n-1>＝2*I<n-2>＝4*I<n-3>＝…＝2n-2*I<1>＝2n-1*I<0>The n reference currents are in binary weighted relation, thereby corresponding to binary codes of corresponding weights.
In detail, as shown in fig. 2, the data register output unit includes n D flip-flops arranged in parallel, and data input ends of the n D flip-flops are respectively connected to the output end of the quantization unit; the n D triggers are connected with the n logic OR gates in a one-to-one correspondence mode: the data latch output end of the D trigger outputs a data signal, and the clock input end of the D trigger is connected with a delay signal of the clock signal.
In more detail, as shown in fig. 2, in the data register output unit: the DATA input end of the 1 st D flip-flop is connected with the output end of the quantization unit, the DATA latch output end of the 1 st D flip-flop outputs a binary code DATA signal DATA < n-1> (namely the DATA latch output end of the 1 st D flip-flop is connected with the second input end of the logic OR gate in the 1 st reference current control branch), and the clock input end of the 1 st D flip-flop is connected with a delay signal cnt _ delay <0> of a clock signal cnt <0 >; the DATA input end of the 2 nd D flip-flop is connected with the output end of the quantization unit, the DATA latch output end of the 2 nd D flip-flop outputs a binary code DATA signal DATA < n-2> (namely the DATA latch output end of the 2 nd D flip-flop is connected with the second input end of the logic OR gate in the 2 nd reference current control branch), and the clock input end of the 2 nd D flip-flop is connected with the delay signal cnt _ delay <1> of the clock signal cnt <1 >; by analogy, …; the DATA input end of the nth D trigger is connected with the output end of the quantization unit, the DATA latch output end of the nth D trigger outputs a binary code DATA signal DATA <0> (namely the DATA latch output end of the nth D trigger is connected with the second input end of the logic OR gate in the nth reference current control branch), and the clock input end of the nth D trigger is connected with the delay signal cnt _ delay < n-1> of the clock signal cnt < n-1 >.
The clock signal cnt _ delay < j > is a signal obtained by delaying the clock signal cnt < j > by one quantization comparison period (of the quantization unit), i.e., the delay time of the clock signal cnt _ delay < j > relative to the clock signal cnt < j > is the time required by the quantization unit to complete one quantization comparison, and j is 0, 1, 2, …, n-1; the reference current I < ref > at each comparison is the sum of the superposition of all or part of the n reference currents I < n-1>, I < n-2>, I < n-3>, …, I <1>, I <0>, the reference current I < j > being turned on or off by the corresponding binary code DATA signal DATA < j >.
In detail, as shown in fig. 2, the data latch output terminals of the n D flip-flops are respectively connected to the input terminals of the accumulation counter.
In more detail, as shown in fig. 2, the quantization comparison principle of the verification statistic circuit of the 3D NAND memory is as follows:
(1) initial reset, setting the data of all D triggers in the data register output unit to be 0;
(2) the method comprises the following steps of performing successive approximation comparison, when a clock signal cnt <0> is high, opening a 1 st reference current control branch, outputting a reference current I < n-1>, comparing write failure summary current I < Verok _ q > with the reference current I < n-1> through a quantization unit to obtain a binary code DATA signal DATA < n-1> of the highest bit, after the comparison is completed, the high level of the clock signal cnt _ delay <0> comes, triggering a 1 st D trigger, outputting the binary code DATA signal DATA < n-1> through a DATA latch output end, and selecting the opening or closing of the 1 st reference current control branch according to the value of the binary code DATA signal DATA < n-1 >; thus, the binary code DATA signals DATA <0> with the lowest bit are obtained through the sequential comparison until the binary code DATA signals DATA <0> are output, and all the binary code DATA signals DATA < n-1>, DATA < n-2>, … and DATA <0> are registered and output;
(3) the counter counts in an accumulation way, receives binary code DATA signals DATA < n-1>, DATA < n-2>, … and DATA <0> output by n D triggers in the DATA register output unit in sequence, and carries out accumulation statistics on the binary code DATA signals DATA < n-1>, DATA < n-2>, … and DATA <0> to obtain final quantized DATA.
Optionally, as shown in fig. 3, in an embodiment of the present invention, a quantization comparison process of the verification statistic circuit of the two-bit 3D NAND memory is taken as an example:
1) temporarily carrying out high-order comparison when the high level of the clock signal cnt <0>, opening a higher reference current 2I, comparing a write-failure summary current I < Verok _ q > with a reference current I < ref > (namely the reference current 2I) through a quantization unit, if the write-failure summary current I < Verok _ q > is greater than or equal to 2I, feeding back a binary code DATA signal DATA <1> output by the quantization unit to a control branch of the reference current 2I, and enabling the reference current 2I to be remained and input into the quantization unit; if the write-failure summary current I < Verok _ q > is smaller than 2I, the binary code DATA signal DATA <1> output by the quantization unit is 0, and the binary code DATA signal DATA <1> is fed back to the control branch of the reference current 2I, so that the reference current 2I is closed;
2) temporarily performing low-order comparison when the clock signal cnt <1> is at a high level, opening a reference current I, if the binary code DATA signal DATA <1> is 1, keeping the reference current 2I, comparing a write-failure summary current I < Verok _ q > with a reference current I < ref > (namely, the reference current 2I + I is 3I) through a quantization unit, if the write-failure summary current I < Verok _ q > is greater than or equal to 3I, the binary code DATA signal DATA <0> output by the quantization unit is 1, and if the write-failure summary current I < Verok _ q > is less than 3I, the binary code DATA signal DATA <0> output by the quantization unit is 0; if the binary code DATA signal DATA <1> -0, the reference current 2I is turned off, the write-failure summary current I < Verok _ q > is compared with the reference current I < ref > (i.e. the reference current I) by the quantization unit, if the write-failure summary current I < Verok _ q > is greater than or equal to I, the binary code DATA signal DATA <0> -1 output by the quantization unit, and if the write-failure summary current I < Verok _ q > is less than I, the binary code DATA signal DATA <0> -0 output by the quantization unit.
Meanwhile, in the embodiment of the present invention, a simulation test is performed on the verification statistic circuit of the 3D NAND memory with two bits (that is, n is 2), and the corresponding simulation result is shown in fig. 4, and the reference current is adjusted so that I is 8.6 μ a, 2I is 17.2 μ a, and 3I is 25.8 μ a.
Correspondingly, the specific simulation results are shown in the following table: outputting 00 within the range of 0-I; outputting 01 within the range of I to 2I; outputting 10 within the range of 2I-3I; and 3I or above to output 11.
| I<Verok_q>Range | Binary output | Decimal number |
| 1μA～8μA | 00 | 0 |
| 9μA～17μA | 01 | 1 |
| 18μA～25μA | 10 | 2 |
| 26μA～30μA | 11 | 3 |
Therefore, the verification statistical circuit of the 3D NAND memory provided by the invention simply and efficiently realizes verification statistics on the number of write-failed memory cells in the 3D NAND memory.
In addition, the invention also provides a 3D NAND memory, which comprises a storage array wafer and a CMOS circuit wafer, wherein the storage array wafer and the CMOS circuit wafer are bonded together, and the CMOS circuit wafer is provided with the verification statistical circuit of the 3D NAND memory.
In summary, in the verification and statistics method for the 3D NAND memory, the verification and statistics circuit for the 3D NAND memory, and the 3D NAND memory provided by the present invention, the reference current control unit can be controlled and adjusted by the data signal output by the data register output unit, so that the reference currents of various sizes can be output, and based on the reference currents of various sizes, the write-in failure summary current can be successively approximated and compared and output, from high to low, and the output is a weighted code, without requiring a decoder to perform decoding conversion, so that the circuit structure and the logic principle are simple, and the verification and statistics of the number of the write-in failure storage units in the 3D NAND memory can be quickly and efficiently realized; in addition, the same quantization unit is shared during multiple comparisons, time-sharing multiplexing of the quantization unit is realized, the circuit structure is further simplified, and the area and the power consumption of a corresponding chip are reduced.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A verification statistical circuit of a 3D NAND memory is used for verifying and counting the number of storage units which fail to be written in the 3D NAND memory, and is characterized by comprising the following steps:
the reference current control unit outputs a reference current with adjustable magnitude, and the reference current is composed of a plurality of reference currents in a binary weighted relation;
the first input end of the quantization unit is connected with the write-in failure summary current, the second input end of the quantization unit is connected with the output end of the reference current control unit, and the write-in failure summary current is compared for multiple times and then output by utilizing a plurality of reference currents with different sizes based on the successive approximation comparison principle;
the input end of the data register output unit is connected with the output end of the quantization unit, and the output end of the data register output unit is connected with the reference current control unit;
the input end of the accumulation counter is connected with the output end of the data register output unit;
the write-failure summary current is summary current of the storage units with a plurality of write failures, and the quantization unit is shared during multiple comparisons based on a time division multiplexing principle.
2. The verification statistic circuit of 3D NAND memory according to claim 1, wherein the reference current control unit comprises n reference current control branches, each of the reference current control branches comprises a logic OR gate and a reference current branch respectively; in each reference current control branch, the output end of the logic or gate is connected with the reference current branch, and the reference current branch is controlled to be opened or closed by the input signal of the logic or gate; the output ends of the n reference current branches are connected together and used as the output end of the reference current control unit; wherein n is an integer of 1 or more.
3. The verification statistic circuit for 3D NAND memory according to claim 2, wherein the logic OR gate is a two-input logic OR gate, a first input of which is connected to a clock signal and a second input of which is connected to a data signal; the clock signals and the data signals accessed by the n logic OR gates are different.
4. The verification statistic circuit of 3D NAND memory according to claim 3, wherein each of the reference current branches respectively outputs a reference current, and the reference currents outputted by the n reference current branches are different from each other; when n reference currents output by the n reference current branches are sequenced from large to small, the former reference current is 2 times of the latter reference current; the reference current is the sum of all or part of the n reference currents.
5. The verification statistic circuit of 3D NAND memory according to claim 4, wherein the data register output unit comprises n D flip-flops arranged in parallel, and data input terminals of the n D flip-flops are respectively connected with the output terminal of the quantization unit; the n D flip-flops are connected with the n logic OR gates in a one-to-one correspondence mode: and the data latch output end of the D trigger outputs the data signal, and the clock input end of the D trigger is connected with the delay signal of the clock signal.
6. The verification statistic circuit for 3D NAND memory according to claim 5, wherein the data latch outputs of n D flip-flops are respectively connected to the input terminals of the accumulation counter.
7. A verification statistical method of a 3D NAND memory is used for verifying and counting the number of storage units which fail to be written in the 3D NAND memory, and is characterized by comprising the following steps:
providing a verification statistic circuit of a 3D NAND memory according to any one of claims 1 to 6, forming a plurality of reference currents with adjustable magnitudes by using a plurality of reference currents in binary weighted relation based on the comparison principle of successive approximation, and comparing the write failure summary current for a plurality of times to output.
8. The verification statistical method of the 3D NAND memory according to claim 7, wherein the verification statistical method of the 3D NAND memory further comprises:
based on the time division multiplexing principle, the quantization unit is shared when multiple comparisons are carried out.
9. A3D NAND memory, which comprises a memory array wafer and a CMOS circuit wafer, wherein the memory array wafer and the CMOS circuit wafer are bonded together, and the CMOS circuit wafer is provided with the verification statistical circuit of the 3D NAND memory according to any one of claims 1 to 6.
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