CN112327554B

CN112327554B - Array substrate and display panel

Info

Publication number: CN112327554B
Application number: CN202011315086.9A
Authority: CN
Inventors: 肖锋; 八木敏文; 池田哲也; 杨桂冬
Original assignee: Chengdu BOE Display Technology Co Ltd
Current assignee: Chengdu BOE Display Technology Co Ltd
Priority date: 2020-11-20
Filing date: 2020-11-20
Publication date: 2023-05-09
Anticipated expiration: 2040-11-20
Also published as: CN112327554A

Abstract

The invention provides an array substrate and a display panel. The array substrate comprises a plurality of data lines, a plurality of first grid lines and a plurality of second grid lines, and the plurality of data lines and the first grid lines limit the array substrate into a plurality of pixel units in a crisscross manner; a second gate line is arranged between every two adjacent first gate lines so as to divide each pixel unit into a first area and a second area; the array substrate further comprises a first pixel electrode covering the first area and a second pixel electrode covering the second area; the array substrate further comprises a first thin film transistor and a second thin film transistor corresponding to the first area, and a third thin film transistor corresponding to the second area. The invention can improve the aperture ratio of the pixel area and lead the transmittance of the display panel to be higher.

Description

Array substrate and display panel

Technical Field

The present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate and a display panel.

Background

With the development of liquid crystal display technology, the size of a display screen is larger and larger, and the conventional pixels with vertical alignment of 4 domains can highlight bad performances of visual character bias. In order to improve the viewing angle performance of the panel, the vertical alignment pixels of 3T and 8domain (8 domain, 3 transistor) are gradually applied to the design of large-sized liquid crystal panels.

In the existing 3T and 8domain vertical alignment pixels, 4 domains of a main area and 4 domains of a secondary area in the same sub-pixel are divided, and the difference of front view and side view is reduced by the characteristic of difference of space and liquid crystal orientation, so that the number of TFT thin film transistor devices arranged in the sub-pixel can be used for adjusting the voltage division ratio. For example, 3 thin film transistor devices, and adjacent one main gate line and one sub gate line dividing the sub pixel region into a sub region located at an upper side of the sub gate line and a main region located at a lower side of the main gate line are disposed in each sub pixel region of the array substrate. When the main gate line turns on two of the thin film transistor devices, charges are respectively transferred into the main region and the sub-region through the two thin film transistor devices; when the main gate line is turned off and the sub gate line is turned on, the remaining 1 thin film transistor is turned on, and part of charges of the sub region are discharged through the 1 thin film transistor device, so that a potential difference occurs between the sub region and the main region to reduce color shift.

However, the main gate lines and the sub gate lines are disposed in each sub pixel region, which reduces the aperture ratio of the pixel region and reduces the transmittance of the display panel.

Disclosure of Invention

The invention provides an array substrate and a display panel, which can improve the aperture ratio of a pixel area and enable the transmittance of the display panel to be higher.

In a first aspect, the present invention provides an array substrate, including a plurality of data lines extending along a first direction, and a plurality of first gate lines and second gate lines extending along a second direction, wherein the plurality of data lines and the first gate lines crisscross define the array substrate as a plurality of pixel units; a second gate line is arranged between every two adjacent first gate lines so as to divide each pixel unit into a first area and a second area; the array substrate further includes: a first thin film transistor, a second thin film transistor, and a third thin film transistor, and a first pixel electrode covering the first region and a second pixel electrode covering the second region; the grid electrode of the first thin film transistor is electrically connected with the first grid line, the grid electrodes of the second thin film transistor and the third thin film transistor are electrically connected with the second grid line, the first thin film transistor and the second thin film transistor correspond to the first area, and the third thin film transistor corresponds to the second area, so that the voltage of the first pixel electrode is different from the voltage of the second pixel electrode.

In a second aspect, the present invention provides a display panel, including a color film substrate, a liquid crystal layer, and the above array substrate, where the liquid crystal layer is sandwiched between the color film substrate and the array substrate.

According to the invention, the data lines and the first grid lines define a plurality of pixel units, and the second grid lines divide the pixel units into the first area and the second area, the first grid lines are positioned at the edges of the pixel units, the first area formed between the first grid lines and the second grid lines can transmit light, and a non-light-transmitting interval area is not required to be reserved between the first grid lines and the second grid lines as in the prior art, so that the aperture ratio of the pixel area can be improved, and the transmittance of the display panel is higher.

Drawings

Fig. 1 is a schematic structural diagram of an array substrate with a first structure according to an embodiment of the present invention;

fig. 2 is a schematic diagram illustrating simulation of alignment dark lines formed in an array substrate with a first structure according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an alignment dark stripe formed in an array substrate with a first structure according to an embodiment of the present invention;

fig. 4 is a schematic diagram of another alignment dark stripe formed in an array substrate with a first structure according to an embodiment of the present invention;

Fig. 5 is a schematic structural diagram of an array substrate with a second structure according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of an array substrate with a third structure according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of an alignment dark stripe formed in the array substrate of the second structure of FIG. 5;

FIG. 8 is a schematic structural diagram of an alignment dark stripe formed in the array substrate of the third structure of FIG. 6;

fig. 9 is a schematic diagram illustrating a simulation of alignment dark marks formed in the array substrate of the third structure of fig. 6;

fig. 10 is a schematic structural diagram of an array substrate with a fourth structure according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of an alignment dark stripe formed in an array substrate with a fourth structure according to an embodiment of the present invention;

fig. 12 is a schematic diagram illustrating simulation of alignment dark lines formed in an array substrate with a fourth structure according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of an array substrate with a fifth structure according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of an alignment dark stripe formed in an array substrate with a fifth structure according to an embodiment of the present invention;

fig. 15 is a schematic flow chart of a first photoalignment method of a display panel according to an embodiment of the present invention;

Fig. 16 is a schematic alignment structure diagram of a first photo-alignment method of a display panel according to an embodiment of the present invention;

fig. 17 is a schematic flow chart of a second photoalignment method of a display panel according to an embodiment of the present invention;

fig. 18 is a schematic alignment structure diagram of a second photo-alignment method of a display panel according to an embodiment of the present invention;

fig. 19 is a schematic diagram illustrating a simulation of alignment dark marks in a display panel obtained by aligning the display panel according to the second photo-alignment method of the present invention.

Reference numerals:

100. 200, 300, 400, 500-array substrate; 10-data lines; 21-a first gate line; 22-a second gate line; 31-a first region; 32-a second region; 33-a first drain trace; 331-a first drain segment; 332-a second drain segment; 333-a third drain segment; 334-a sixth drain segment; 335-seventh drain segment; 34-a second drain trace; 341-a fourth drain segment; 342-a fifth drain segment; 51-a first pixel electrode; 511-a first notch; 512-first protrusions; 52-a second pixel electrode; 521-second gap; 522-second protrusions; 53. 54-sloped transition region; 61-a first thin film transistor; 621-a first via; 622-second vias; 60- "ten" fields; 62-a second thin film transistor; 63-a third thin film transistor; 64-a lateral portion; 641-a first extension; 642-a second extension; 65-longitudinal section; 651-third extension; 652-fourth extension; 71. 72-vertical exposure area; 73-a first exposure area; 74-a second exposure area; 75-a third exposure area; 76-fourth exposure area; 80-storage capacitor lines; 81. 82, 83, 84-a first storage capacitor section; 85. 86-a second storage capacitor line; 90-sharing a capacitance line; 91-alignment dark marks; 92-a first shared capacitor section; 93-a second shared capacitance section; 94-auxiliary wiring.

Detailed Description

The array substrate in the prior art has the technical problems of low pixel aperture ratio and low transmittance of the display panel, and is characterized in that: the main gate line and the sub gate line are both located in the pixel unit, and a certain space needs to be provided between the main gate line and the sub gate line to meet the electrical design requirement, and the space belongs to an opaque area, so that the aperture ratio of the pixel can be occupied.

According to the pixel unit, the first gate line (corresponding to the secondary gate line in the prior art) is arranged at the edge of the pixel unit, the second gate line (corresponding to the main gate line in the prior art) is arranged in the pixel unit, and the pixel unit is divided into the first area and the second area by the second gate line, so that the opaque space as in the prior art is omitted between the first gate line and the second gate line, and the aperture ratio of the pixel unit can be improved. The present application is described in detail below with reference to the accompanying drawings.

Example 1

Fig. 1 is a schematic structural diagram of an array substrate with a first structure according to an embodiment of the present invention. Referring to fig. 1, an array substrate 100 of the present application includes a plurality of data lines 10 extending in a first direction F, and a plurality of first and

second gate lines

21 and 22 extending in a second direction S, the plurality of data lines 10 and the first gate lines 21 crisscross defining the array substrate 100 as a plurality of pixel cells; a second gate line 22 is provided between every two adjacent first gate lines 21 to divide each pixel cell into a first region 31 and a second region 32.

In this application, the first direction F and the second direction S represent different extending directions, and may be any directions. In fig. 1, taking the data line 10 extending vertically along the drawing plane as an example, the first gate line 21 and the second gate line 22 extending laterally along the drawing plane as an example, i.e., the first direction F is the vertical direction of the drawing plane of fig. 1, and the second direction S is the lateral direction of the drawing plane of fig. 1. However, the present invention is not limited thereto, and the extending directions of the first direction F and the second direction S may be different. It should be understood that the array substrate 100 in the present application includes a plurality of pixel units, and for convenience of description, only one of the pixel units is shown in the drawings in the present application.

Referring to fig. 1, the first and

second gate lines

21 and 22 are parallel to each other with a predetermined interval therebetween, and the data lines 10 are perpendicular to the first and

second gate lines

21 and 22, such that the plurality of data lines 10 and the first gate lines 21 crisscross define the array substrate 100 as a plurality of pixel cells. And the second gate line 22 is located between two adjacent first gate lines 21 (only one first gate line is drawn in fig. 1), each pixel cell can be divided into a first region 31 and a second region 32.

As a possible way, the second gate line 22 is located right in between its corresponding two adjacent first gate lines 21, i.e. the second gate line 22 is equidistant from its two adjacent first gate lines 21. So that the first region 31 and the second region 32 have substantially the same area. Of course, the present invention is not limited thereto, and the second gate line 22 may be not equidistant from the two first gate lines 21 adjacent thereto.

In this embodiment, with continued reference to fig. 1, corresponding to the first region 31 and the second region 32, the array substrate 100 further includes: a first pixel electrode 51, a second pixel electrode 52, a first thin film transistor 61, a second thin film transistor 62, and a third thin film transistor 63. Wherein the first pixel electrode 51 and the second pixel electrode 52 are indicated by dashed boxes. Wherein the first pixel electrode 51 covers the first region 31 and the second pixel electrode 52 covers the second region 32. The first thin film transistor 61 is provided corresponding to the first gate line 21, for example, the first thin film transistor 61 is formed above the first gate line 21, a gate electrode of the first thin film transistor 61 is electrically connected to the first gate line 21, and a voltage is supplied to the first thin film transistor 61 by the first gate line 21; the second thin film transistor 62 and the third thin film transistor 63 are disposed corresponding to the second gate line 22, for example, the second thin film transistor 62 and the third thin film transistor 63 are formed over the second gate line 22, the gate electrode of the second thin film transistor 62 and the gate electrode of the third thin film transistor 63 are electrically connected to the second gate line 22, and a voltage is supplied from the second gate line 22 to the second thin film transistor 62 and the third thin film transistor 63. The on/off time of the first thin film transistor 61 and the second thin film transistor 62 may affect the voltage of the first pixel electrode 51, and the on/off time of the third thin film transistor 63 may affect the voltage of the second pixel electrode 52.

Note that the first thin film transistor 61 and the second thin film transistor 62 correspond to the first region 31, meaning that the first thin film transistor 61 and the second thin film transistor 62 are used to influence the voltage magnitude of the first pixel electrode 51 in the first region 31; the third thin film transistor 63 corresponds to the second region 32, meaning that the third thin film transistor 63 can affect the voltage level of the second pixel electrode 52 in the second region 32. The voltage of the first pixel electrode 51 is made different from the voltage of the second pixel electrode 52 by the common operation of the first thin film transistor 61, the second thin film transistor 62, and the third thin film transistor 63.

In the above-mentioned scheme, the data lines 10 and the first gate lines 21 define a plurality of pixel units on the array substrate 100, and the second gate lines 22 divide the pixel units into the first region 31 and the second region 32 capable of transmitting light, compared with the prior art, the first gate lines 21 are located at the edges of the pixel units, and the first region 31 formed between the first gate lines 21 and the second gate lines 22 is sufficiently sized to meet the electrical requirements, and can transmit light, and there is no need to reserve a non-light-transmitting interval region between the first gate lines 21 and the second gate lines 22 as in the prior art.

It will be appreciated that the first thin film transistor 61 and the second thin film transistor 62 are used to control the voltage of the first pixel electrode 51, the third thin film transistor 63 is used to control the voltage of the second pixel electrode 52, and a voltage difference may exist between the voltage of the first pixel electrode 51 and the voltage of the second pixel electrode 52, for example, the voltage of the first pixel electrode 51 may be lower than the voltage of the second pixel electrode 52, so that the brightness of the first region 31 is slightly lower than the brightness of the second region 32 during specific display to reduce color shift.

It should be noted that the above description is given by taking the example that the voltage of the first pixel electrode 51 is lower than the voltage of the second pixel electrode 52 as an example, but the present application is not limited thereto, and the voltage of the first pixel electrode 51 may be higher than the voltage of the second pixel electrode, so that the brightness of the first region 31 is slightly higher than the brightness of the second region 32 in a specific display to reduce color shift.

In this embodiment, referring to fig. 1, a first drain trace 33 for electrically connecting the drain of the first thin film transistor 61 and the drain of the second thin film transistor 62 is further disposed in each first region 31. Further, each second region 32 is further provided with a second drain trace 34 for electrically connecting the drain of the third thin film transistor 63 and the second pixel electrode 52 corresponding to the second region 32.

For example, the array substrate 100 may include a substrate and storage capacitor lines 80 formed on the substrate; the first gate line 21 and the second gate line 22 are in the same layer as the storage capacitor line 80, and in one possible embodiment, further include a shared capacitor line 90 located above the storage capacitor line 80, where the data line 10 is in the same layer as the shared capacitor line 90, and the shared capacitor line 90 is located in the first region 31.

The connection relationship between the portions in each pixel unit is specifically described below.

Referring to fig. 1, the gate electrode of the first thin film transistor 61 is electrically connected to the first gate line 21, and the drain electrode of the first thin film transistor 61 is electrically connected to the drain electrode of the second thin film transistor 62 through the first drain trace 33. Alternatively, the first drain trace 33 may be electrically connected to the first pixel electrode 51 through the first via hole 621. The source electrode of the first thin film transistor 61 is further electrically connected to the sharing capacitor line 90, and the sharing capacitor line 90 is located directly above a portion of the storage capacitor line 80, so that a sharing capacitor is formed between the sharing capacitor line 90 and the storage capacitor line 80.

The gate electrode of the second thin film transistor 62 is electrically connected to the second gate line 22, the drain electrode of the second thin film transistor 62 is electrically connected to the drain electrode of the first thin film transistor 61 through the first drain trace 33, the drain electrode of the second thin film transistor 62 is also electrically connected to the first pixel electrode 51 through the first via hole 621, the second thin film transistor 62 is commonly connected to the third thin film transistor 63, and the source electrode of the second thin film transistor 62 is electrically connected to the data line 10. The gate electrode of the third thin film transistor 63 is electrically connected to the second gate line 22, the drain electrode of the third thin film transistor 63 is electrically connected to the second pixel electrode 52 through the second drain trace 34 and the second via 622 formed over the second drain trace 34, the source electrode of the third thin film transistor 63 is common to the second thin film transistor 62, and the source electrode of the third thin film transistor 63 is electrically connected to the data line 10.

In particular operation, the second gate line 22 is turned on to turn on the gates of the second and third

thin film transistors

62 and 63, and charge is supplied to the first and

second regions

31 and 32 through the second and third

thin film transistors

62 and 63, respectively. When the second gate line 22 is turned off and the first gate line 21 is turned on, the sharing capacitor line is turned on, and part of the charges in the first region 31 are released into the sharing capacitor, so that the potential corresponding to the first region 31 is smaller than the potential corresponding to the second region 32, and the first region 31 and the second region 32 exhibit a potential difference, thereby achieving the purpose of reducing color shift.

< alignment dark streak >

Fig. 2 is a schematic diagram of an alignment dark line formed in an array substrate with a first structure according to an embodiment of the present invention, and fig. 3 is a schematic diagram of an alignment dark line formed in an array substrate with a first structure according to an embodiment of the present invention.

Referring to fig. 2, a display panel to which the array substrate 100 of the present embodiment is applied employs UV ² A photo-alignment technique, in which each of the first region 31 and the second region 32 has an alignment dark stripe 91 caused by photo-alignment at the time of display. Specifically, in the display panel including the array substrate 100 shown in fig. 1 and 2, the photo-alignment method shown in fig. 15 described later in the present application is adopted, the alignment dark line 91 corresponding to the first region 31 is in an "8" shape, and the alignment dark line 91 corresponding to the second region 32 is in a "jia" shape, for example, in a right-handed "shape Type "of the material.

Specifically, the alignment dark stripe 91 may have a "ten" field 60 located at the center of the first region 31 or the center of the second region 32, and the first drain trace 33 may extend corresponding to the "ten" field 60. For example, referring to fig. 1 and 3, the "ten" field 60 includes a transverse portion 64 and a longitudinal portion 65 intersecting each other, the transverse portion 64 extending in the second direction and being located at a center position of the first region 31 or the second region 32 in the first direction F. The longitudinal portion 65 extends along the first direction F and is located at a central position of the first region 31 or the second region 32 in the second direction S.

In this application, for convenience of explanation, an upward direction of the first direction F shown in fig. 1 is defined as up, and a downward direction of the first direction F shown in fig. 1 is defined as down; the leftward direction of the second direction S shown in fig. 1 is defined as left, and the rightward direction of the second direction S shown in fig. 1 is defined as right; of course, the array substrate shown in fig. 1 is a case where one surface of the array substrate close to the liquid crystal layer faces the outside of the paper.

The "swastika" type dark pattern further includes an extension section located at an edge of the first area 31 or the second area 32, for example, referring to fig. 2 and 3, the "swastika" type dark pattern is formed in the second area 32 is taken as an example, and it is understood that the "swastika" type dark pattern is formed in the first area 31 similarly, and will not be described herein again.

The dark lines of the swastika comprise first extension parts 641 extending from two end parts of the transverse part 64 to the position away from the transverse part 64 respectively, and the first extension parts 641 connected with the left end part of the transverse part 64 extend upwards along a first direction F; the first extension 641 connected to the right end of the transverse portion 64 extends downward in the first direction F.

The dark line of the "swastika" type further comprises second extending parts 642 extending from both ends of the longitudinal portion 65 toward the opposite sides of the longitudinal portion 65, respectively, and the second extending parts 642 connected to the upper end of the longitudinal portion 65 extend rightward in the second direction S; the second extension 642 connected with the lower end portion of the longitudinal portion 65 extends leftward in the second direction S. Wherein the two first extension portions 641 and the two second extension portions 642 make the dark pattern of the "swastika" in a right-handed state.

For the dark line of the "8" shape, taking the case where the dark line is provided in the first area 31 as illustrated in fig. 2, the dark line of the "8" shape includes the third extension portion 651 extending from both end portions of the lateral portion 64 toward the end portion away from the lateral portion 64, and the third extension portion 651 connected to the left end portion of the lateral portion 64 extends downward in the first direction F; the third extension 651 connected with the right end portion of the lateral portion 64 extends upward in the first direction F.

The dark line in the shape of "8" further includes fourth extension portions 652 extending from both end portions of the longitudinal portion 65 toward the direction away from the longitudinal portion 65, respectively, the fourth extension portions 652 connected to the upper end portion of the longitudinal portion 65 extending rightward in the second direction S; the fourth extension 652 connected to the lower end of the longitudinal portion 65 extends leftward in the second direction S. And each third extension 651 intersects the ends of the adjacent fourth extension 652 such that the dark veins of the "8" form a closed "8" shape.

< first drain electrode wiring and alignment dark stripe >

As described above, the first drain trace 33 is located in the first region 31, so as to minimize the influence of the first drain trace 33 on the effective aperture ratio of the pixel, at least a part of the structure on the first drain trace 33 and the orthographic projection of the alignment dark stripe 91 on the array substrate may have an overlapping region. Thus, part of the structure of the opaque first drain trace 33 can be hidden under the alignment dark stripe 91, so that the loss of the effective aperture ratio can be reduced. For example, the orthographic projection of at least part of the "ten" field 60 of the structure and alignment dark stripe on the first drain trace 33 on the array substrate has an overlapping area.

Referring to fig. 1 and 3, the first drain trace 33 includes, from bottom to top, a first drain segment 331, a second drain segment 332, and a third drain segment 333 electrically connected in sequence. Specifically, one end of the first drain section 331 is electrically connected to the drain of the second thin film transistor 62, the other end of the first drain section 331 is electrically connected to one end of the second drain section 332, the other end of the second drain section 332 is electrically connected to one end of the third drain section 333, and the other end of the third drain section 333 is electrically connected to the drain of the first thin film transistor 61.

Illustratively, a first via hole 621 is correspondingly disposed at a position where the other end of the second drain segment 332 and one end of the third drain segment 333 are connected, and the first via hole 621 is used to electrically connect the other end of the second drain segment 332 and one end of the third drain segment 333 with the first pixel electrode 51. In the case where the first region 31 has an alignment dark stripe, the third drain segment 333 may extend downward from the drain of the first thin film transistor 61 along the extending direction of the longitudinal portion 65 of the alignment dark stripe, and to the intersection O of the lateral portion 64 and the longitudinal portion. The second drain segment 332 may extend leftwards along the lateral portion 64 of the alignment dark stripe from the intersection O and to an edge position of the lateral portion 64, and the first drain segment 331 may extend downwards along the first direction from an end of the second drain segment 332 near the edge position of the first region 31 to a drain position of the second thin film transistor 62.

Fig. 4 is a schematic structural diagram of another alignment dark stripe formed in the array substrate with the first structure according to the embodiment of the present invention. Fig. 3 shows a case where "8" -shaped alignment dark lines are formed in the first region 31 and "swastika" -shaped alignment dark lines are formed in the second region 32; fig. 4 shows a case where the first region 31 forms a "swan" type alignment dark line, and the second region 32 forms an "8" type alignment dark line.

Referring to fig. 3 and 4, in the case that the alignment dark stripe 91 of the first area 31 is a "stigmata" dark stripe or an "8" dark stripe, in the above-mentioned first drain trace 33, the orthographic projection of the third drain segment 333 and the longitudinal portion 65 on the array substrate 100 has an overlapping area, that is, the third drain segment 333 may be hidden under the longitudinal portion 65; the orthographic projection of the second drain segment 332 and the lateral portion 64 on the array substrate 100 has an overlapping area, that is, the second drain segment 332 may be hidden under the lateral portion 64, so as to reduce the loss of the effective aperture ratio. In other words, the third drain segment 333 and the second drain segment 332 may be hidden under the "ten" field 60 of the alignment shading.

In the case that the alignment dark stripe 91 is an "8" -shaped dark stripe, as shown in fig. 3, the orthographic projection of the first drain segment 331 and the third extension portion 651 on the left side on the array substrate 100 has an overlapping area, that is, the first drain segment 331 may be hidden under the third extension portion 651. It can be understood that, in the case that the alignment dark stripe 91 is a "swan" dark stripe, the first drain trace 33 except for the first drain segment 331 may be hidden under the alignment dark stripe 91; in the case that the alignment dark stripe 91 is an "8" shaped dark stripe, the whole first drain trace 33 may be hidden under the alignment dark stripe 91. Therefore, the arrangement of the first drain trace 33 in the above-mentioned scheme can improve the effective aperture ratio of the pixel unit.

< second drain electrode wiring and alignment dark stripe >

As described above, the second drain trace 34 is located in the second region 32, so as to minimize the influence of the second drain trace 34 on the effective aperture ratio of the pixel, the orthographic projection of at least part of the structure on the second drain trace 34 and the alignment dark stripe 91 corresponding to the second region 32 on the array substrate may have an overlapping region. Thus, part of the structure of the opaque second drain trace 34 can be hidden under the alignment dark stripe 91, so that the loss of the effective aperture ratio can be reduced. For example, the orthographic projection of the "ten" field 60 of at least a portion of the structure and alignment dark stripe on the second drain trace 34 on the array substrate has an overlapping area.

Referring to fig. 1 and 3, the second drain trace 34 includes a fourth drain segment 341 and a fifth drain segment 342 electrically connected in sequence from top to bottom. Specifically, one end of the fourth drain segment 341 is electrically connected to the drain electrode of the third thin film transistor 63, the other end of the fourth drain segment 341 is electrically connected to one end of the fifth drain segment 342, and the other end of the fifth drain segment 342 is electrically connected to the second pixel electrode 52 through the second via hole 622.

Where the second region 32 has an alignment dark stripe, the fourth drain segment 341 may extend along the first direction F from the drain of the second thin film transistor 62 and extend to the end of the lateral portion 64, and the fifth drain segment 342 may extend along the lateral portion 64 from the end of the fourth drain segment 341 to the intersection position P of the lateral portion 64 and the longitudinal portion 65.

Referring to fig. 3 and 4, in the case that the alignment dark stripe 91 of the second area 32 is a "jia" dark stripe or an "8" dark stripe, in the second drain trace 34, the front projection of the fifth drain segment 342 and the transverse portion 64 of the alignment dark stripe 91 on the array substrate 100 has an overlapping area, that is, the fifth drain segment 342 may be hidden under the transverse portion 64, so that the loss of the effective aperture ratio can be reduced. In other words, the fifth drain segment 342 may be hidden under the "ten" field 60 of the alignment shading; in the case that the alignment dark stripe 91 of the second area 32 is a "stika" dark stripe, as shown in fig. 3, in the first drain trace 33, the orthographic projection of the fourth drain segment 341 and the first extension 641 of the alignment dark stripe 91 on the array substrate 100 has an overlapping area, that is, the fourth drain segment 341 may be hidden under the first extension 641, so that the arrangement mode of the second drain trace 34 in the above scheme can improve the effective aperture ratio of the pixel unit.

< storage capacitor line and alignment dark line >

As described above, the array substrate 100 may include a substrate and the storage capacitor line 80 formed on the substrate; the first and

second gate lines

21 and 22 are layered with the storage capacitor line 80, and the storage capacitor line 80 and the pixel electrode in the corresponding region form a storage capacitor together. The storage capacitor line 80 and the orthographic projection of the alignment dark stripe 91 on the array substrate have overlapping areas. As described above, the storage capacitor line 80 is provided so as to have an overlapping region with the alignment dark line 91, and the storage capacitor line 80 is hidden under the alignment dark line 91 which inevitably occurs, so that the loss of the effective aperture ratio of the pixel unit can be reduced as compared with the case of being provided at another position. Illustratively, the orthographic projection of at least a portion of the "ten" field 60 of the structure and alignment shading on the storage capacitor line 80 on the array substrate 100 may have an overlapping area.

In one possible embodiment, the storage capacitor line 80 includes a plurality of first storage capacitor segments extending in a direction parallel to the data line 10, and at least one first storage capacitor segment is corresponding to each of the first region 31 and the second region 32. Referring to fig. 1 and 3, two first

storage capacitor segments

81 and 82 are correspondingly arranged in the first region 31, and the two first

storage capacitor segments

81 and 82 are spaced in the second direction S and extend along two vertical edges of the first region 31 respectively; the second region 32 has two first

storage capacitor segments

83, 84, which are spaced apart in the second direction S and extend along two vertical edges of the second region 32, respectively.

Further, the storage capacitor line 80 further includes a plurality of second storage capacitor lines extending in parallel to the first gate line 21, and one second storage capacitor line is disposed before each two adjacent first gate lines 21 and second gate lines 22, that is, one second storage capacitor line is disposed in each of the first area 31 and the second area 32. Referring to fig. 1 and 3, a second storage capacitor line 85 is corresponding to the first region 31; the second region 32 corresponds to a second storage capacitor line 86.

Referring to fig. 1, 3 and 4, in the case that the alignment dark line 91 of the first area 31 is a "swan" dark line or an "8" dark line, the orthographic projection of the second storage capacitor line 85 and the lateral portion 64 of the alignment dark line 91 on the array substrate has an overlapping area, that is, most of the structure of the second storage capacitor line 85 located in the opening area of the pixel may be hidden under the lateral portion 64 of the "ten" field 60, so as to improve the effective aperture ratio of the pixel unit.

It should be noted that, since the second drain segment 332 is also hidden under the lateral portion 64, that is, the orthographic projection of the second drain trace 34 and the partial structure of the storage capacitor line 80 on the array substrate 100 may also have an overlapping area.

Referring to fig. 3 and 4, in the case that the alignment dark line of the second area 32 is a "jia" dark line or an "8" dark line, the front projection of the second storage capacitor line 86 and the lateral portion 64 of the alignment dark line on the array substrate 100 has an overlapping area, that is, most of the structure of the second storage capacitor line 86 located in the opening area of the pixel may be hidden under the lateral portion 64, so as to improve the effective aperture ratio of the pixel unit.

It should be noted that, since the fifth drain segment 342 is also hidden under the lateral portion 64, that is, the orthographic projection of the second drain trace 34 and the partial structure of the storage capacitor line 80 on the array substrate 100 may also have an overlapping area.

In the case where the alignment dark stripe 91 of the first area 31 is a "stika" dark stripe, as shown in fig. 4, in the upper half of the first storage capacitor section 81, a part of the structure and the orthographic projection of the left first extension 641 of the alignment dark stripe 91 on the array substrate 100 have an overlapping area, that is, the part of the structure of the first storage capacitor section 81 may be hidden under the left first extension 641, so as to improve the effective aperture ratio of the pixel unit.

The front projection of the second extension 641 on the right side of the alignment dark stripe 91 in the lower half of the first storage capacitor section 82 has an overlapping area, i.e., the second extension 641 on the right side can be hidden by the partial structure of the first storage capacitor section 82, so as to improve the effective aperture ratio of the pixel unit.

In the case that the alignment dark stripe of the first area 31 is an "8" -shaped dark stripe, as shown in fig. 3, the above-mentioned partial structure of the lower half section of the first storage capacitor section 81 and the orthographic projection of the third extension portion 651 on the left side of the alignment dark stripe have an overlapping area, that is, the partial structure of the first storage capacitor section 81 may be hidden under the third extension portion 651, so as to improve the effective aperture ratio of the pixel unit. Further, the width of the lower half of the first storage capacitor section 81 may be widened locally, and the storage capacitor may be further increased by increasing the area of the first storage capacitor section 81.

The front projection of the upper half section of the first storage capacitor section 82 and the third extension portion 651 on the right side of the alignment dark line on the array substrate 100 has an overlapping area, that is, a part of the structure of the first storage capacitor section 82 may be hidden under the third extension portion 651 on the right side, so that the effective aperture ratio of the pixel unit may be improved. The arrangement of the overlapping areas of the first

storage capacitor segments

81, 82, 83, 84 and the dark fringes in the second area 32 is similar to that of the first area 31, and will not be repeated here.

< shared capacitor line, storage capacitor line, and alignment dark line >

As described above, the first region 31 is further provided with the sharing capacitor line 90, and the sharing capacitor line 90 is located directly above the partial structure of the storage capacitor line 80, so that a sharing capacitor is formed between the sharing capacitor line 90 and the storage capacitor line 80. The data line 10 and the sharing capacitor line 90 are in the same layer, and the orthographic projections of the sharing capacitor line 90, the storage capacitor line 80, and the alignment dark stripe 91 on the array substrate 100 have overlapping areas.

In the prior art, the first gate line and the second gate line penetrate through the middle part of the pixel unit, so that the shared capacitor can be located at the position adjacent to the first gate line and the second gate line in the main area or the secondary area, and the effective aperture ratio of the pixel is affected. In this application, the orthographic projection of the shared capacitor line 90 and the alignment dark line on the array substrate 100 has an overlapping area, and compared with the case that the shared capacitor line 90 occupies the open space in the prior art, the partial structure of the shared capacitor line 90 is hidden under the alignment dark line with lower light transmittance, so that the open area is not additionally occupied, and the effective aperture ratio of the pixel can be improved.

Specifically, referring to fig. 1 and 3, the shared capacitor line 90 includes a first shared capacitor section 92 extending along a first direction F, further, the shared capacitor line 90 further includes a second shared capacitor section 93 extending along a second direction S, one end of the first shared capacitor section 92 is electrically connected to the source of the first thin film transistor 61, the other end of the first shared capacitor section 92 is electrically connected to one end of the second shared capacitor section 93, and the other end of the second shared capacitor section 93 is suspended. In one example, if one end of the first sharing capacitor section 92 is spaced from the first thin film transistor 61, an auxiliary trace 94 may be disposed therebetween to electrically connect the two.

The alignment dark stripe corresponding to the first region 31, the first sharing capacitor section 92 and the orthographic projection of at least one first storage capacitor section on the array substrate have overlapping regions.

For example, in the case where the first region 31 has an alignment dark stripe, as shown in fig. 3, one end of the auxiliary trace 94 extends from the drain of the first thin film transistor 61 along the fourth extension 652 on the upper side of the alignment dark stripe 91, the first sharing capacitor section 92 extends along the right edge of the first region 31, and the second sharing capacitor section 93 extends along the lateral portion 64 of the alignment dark stripe to the intersection O of the lateral portion 64 and the longitudinal portion 65.

In the case that the alignment dark stripe 91 of the first area 31 is a "stika" dark stripe or an "8" dark stripe, as shown in fig. 3 and fig. 4, the orthographic projection of the auxiliary trace 94 and the second extension portion 642 or the fourth extension portion 652 on the array substrate has an overlapping area. In the above-mentioned sharing capacitor line 90, the second sharing capacitor section 93 and the front projection of the lateral portion 64 of the alignment dark stripe on the array substrate have an overlapping area, i.e. the second sharing capacitor section 93 may be hidden under the lateral portion 64.

Under the condition that the alignment dark stripe 91 of the first area 31 is an "8" -shaped dark stripe, the orthographic projection of the first sharing capacitor section 92 and the third extension portion 651 on the upper side of the alignment dark stripe on the array substrate 100 has an overlapping area, that is, the first sharing capacitor section 92 can be hidden under the third extension portion 651, so that the loss of the effective aperture ratio can be reduced.

Therefore, in the case that the alignment dark stripe is a "swastika" dark stripe, the sharing capacitor line 90 may be hidden under the alignment dark stripe except for the first sharing capacitor section 92; in the case that the alignment dark line is an "8" dark line, the whole shared capacitor line 90 may be hidden under the alignment dark line. The arrangement of the sharing capacitor line 90 in this way can improve the effective aperture ratio of the pixel unit.

< first drain wire, second drain wire, shared capacitor wire and storage capacitor wire)

Referring to fig. 1 and 3, as described above, the storage capacitor line 80 includes the first storage capacitor segment 81 having a direction parallel to the data line 10, and a part of the first storage capacitor segment 81 may be hidden under the third extension 651, and since the first drain segment 331 is also hidden under the third extension 651, a part of the first storage capacitor segment 81 may be widened, and the widened part may be located directly under the first drain segment 331, which may not affect the effective aperture ratio of the pixel, but also increase the storage capacitor.

Similarly, the portion of the first storage capacitor segment 82 corresponding to the first sharing capacitor segment 92 is also partially widened, so that the widened portion is located right below the first sharing capacitor segment 92, which does not affect the effective aperture ratio of the pixel, and increases the storage capacitor.

Similarly, in the second region 32, it is possible to widen a part of the structure of the first storage capacitor section 83 and locate the widened part directly under the fourth drain section 341, without affecting the effective aperture ratio of the pixel, and increasing the storage capacitor.

For the second storage capacitor segment 85, it may be located directly under the second drain segment 332 and the second shared capacitor segment 93, and for the second storage capacitor segment 86, it may be located directly under the fifth drain segment 342.

< pixel electrode and second Gate line >

As described above, the array substrate of the present application includes the first pixel electrode 51 covering the first region 31 and the second pixel electrode 52 covering the second region 32. If the ends of the first pixel electrode 51 and the second pixel electrode 52 near the second gate line 22 are spaced apart from the second gate line 22, that is, if the first pixel electrode 51 and the second pixel electrode 52 are located in the opening regions of the first region 31 and the second region 32, the alignment dark fringes in the first region 31 and the alignment dark fringes in the second region 32 are spaced apart from the second gate line 22.

In order to reduce the influence of the alignment dark stripe 91 on the effective aperture ratio, the dimensions of the first pixel electrode 51 and the second pixel electrode 52 may be reasonably set, so that the alignment dark stripe 91 in the first region 31 and the second region 32 may move toward the second gate line 22, so as to achieve the purpose of overlapping a part of the alignment dark stripe 91 with the second gate line 22.

Fig. 5 is a schematic structural diagram of an array substrate with a second structure according to an embodiment of the present invention, and fig. 7 is a schematic structural diagram of an alignment dark stripe formed in the array substrate with the second structure of fig. 5.

For example, referring to fig. 5, in addition to the structure of the array substrate of the first structure shown in fig. 1, in the array substrate 200, the first pixel electrode 51 and the second pixel electrode 52 are each extended toward the end of the second gate line 22 in a direction approaching the second gate line 22. To achieve the effect that the orthographic projection of the end parts of the second gate line 22, which are close to the second gate line 22, of the first pixel electrode 51 on the array substrate 200 has an overlapping area; and/or the orthographic projections of the second gate line 22 and the end portion of the second pixel electrode 52 near the second gate line 22 on the array substrate 200 have an overlapping region.

Referring to fig. 7, in the array substrate 200 of the second structure shown in fig. 5, the second extension portion 642 or the fourth extension portion 652 of the generated alignment dark stripe moves toward the second gate line 22, and part of the structure overlaps the second gate line 22, thereby reducing the areas of the alignment dark stripe in the first region 31 and the second region 32 and improving the effective aperture ratio.

Fig. 6 is a schematic structural diagram of an array substrate with a third structure according to an embodiment of the present invention, fig. 8 is a schematic structural diagram of an alignment dark stripe formed in the array substrate with the third structure of fig. 6, and fig. 9 is a schematic simulation diagram of the alignment dark stripe formed in the array substrate with the third structure of fig. 6. In other examples, in order to further reduce the areas of the alignment dark marks 91 in the first region 31 and the second region 32, the shape of the pixel electrode may be further rationally designed.

Referring to fig. 6, the array substrate 300 of the third structure is based on the array substrate 200 of the second structure, in which the end of the first pixel electrode 51 on the second gate line 22 is provided with a first notch 511, the position of the first notch 511 is located on the right side of the first pixel electrode 51, and correspondingly, the end of the second pixel electrode 52 on the second gate line 22 is provided with a second protrusion 522 corresponding to the first notch 511, and the shape of the outer edge of the second protrusion 522 is complementary to the shape of the outer edge of the first notch 511, so that space is utilized to the maximum extent and the space between the two is reduced.

In this way, referring to fig. 8, since the first notch 511 is not formed at the position of the first region 31, the first pixel electrode 51 is formed with the first notch 511 at the position, and the effective aperture ratio is not affected; in the second region 32, the position of the second protruding portion 522 corresponds to the second extending portion 642 or the fourth extending portion 652 of the alignment dark line (when the alignment dark line of the second region 32 is the "8" -shaped dark line), since the second protruding portion 522 protrudes toward the first region 31, the edge of the second protruding portion 522 protrudes more into the second gate line 22 than in the case shown in fig. 7, and thus more portions of the second extending portion 642 or the fourth extending portion 652 of the wiring dark line corresponding to the second region 32 enter the second gate line 22, thereby reducing the area of the wiring dark line in the second region 32 and improving the pixel effective aperture ratio of the second region 32.

It can be understood that the first protrusion 512 is simultaneously formed at the lower left edge of the first pixel electrode 51 while the first notch 511 is formed at the lower right edge of the first pixel electrode 51; the second notch 521 is simultaneously formed at the upper left edge of the second pixel electrode 52 while the second protrusion 522 is formed at the upper right edge of the second pixel electrode 52.

The second extension portion 642 or the fourth extension portion 652 of the alignment dark line corresponding to the first protrusion portion 512 extends into the second gate line 22, so that the area of the wiring dark line in the first region 31 is reduced, and the effective aperture ratio of the pixel in the first region 31 is improved.

It should be noted that, referring to fig. 6 and 8, the boundary region between the first protrusion 512 and the first notch 511 may be formed as the inclined transition region 53, and the boundary region between the second protrusion 522 and the second notch 521 may be formed as the inclined transition region 54, so that the dark streak portion at the intersection point of the longitudinal portion 65 of the alignment dark streak 91 and the second extension 642 or the fourth extension 652 may be removed as compared with the formation of the right angle transition region.

It is understood that the boundary area between the first protrusion 512 and the first notch 511 may be formed as an inclined transition area 53, specifically, the outer edge of the transition area between the first protrusion 512 and the first notch 511 is inclined in a straight line, and the inclined straight line may have a predetermined included angle with the second direction S, i.e. the outer edge of the transition area is not parallel to or perpendicular to the second direction S. The boundary area between the second protrusion 522 and the second notch 521 may also be formed as an inclined transition area 54, specifically, the outer edge of the transition area 54 between the second protrusion 522 and the second notch 521 is inclined in a straight line, and the inclined straight line may have a predetermined included angle with the second direction S, i.e. the outer edge of the transition area 54 is not parallel to or perpendicular to the second direction S.

As can be seen from the simulated pattern of the alignment dark lines, the second and fourth extending

portions

642 and 652 of the alignment dark lines 91, which are adjacent to the second gate lines 22, are not formed in the first and

second regions

31 and 32 as the second and

first protrusions

522 and 512 enter the second gate lines 22, thereby increasing the effective aperture ratio of the pixels in the first and

second regions

31 and 32.

Fig. 10 is a schematic structural diagram of an array substrate with a fourth structure according to an embodiment of the present invention, and fig. 11 is a schematic structural diagram of an alignment dark stripe formed in an array substrate with a fourth structure according to an embodiment of the present invention. Fig. 12 is a schematic diagram illustrating simulation of alignment dark lines formed in an array substrate with a fourth structure according to an embodiment of the present invention. In this embodiment, referring to fig. 10 to 12, the formation position of the first thin film transistor 61 is improved on the basis of the array substrate with the first structure, so that the structures and positions of the first drain trace 33 and the shared capacitor line 90 are also changed, and the rest of the array substrate with the fourth structure is similar to the array substrate with the first structure, and is not repeated here.

Referring to fig. 1, in the array substrate with the first structure, the shared capacitor line 90 includes an auxiliary trace 94, a first shared capacitor section 92, and a second shared capacitor section 93 electrically connected in sequence, the shared capacitor line 90 and the data line 10 are on the same layer, and are located under the first pixel electrode 51, and a parasitic capacitance formed between the shared capacitor line 90 and the first pixel electrode 51 is larger, so that it is considered to reduce the area of the shared capacitor line 90 in order to reduce the size of the parasitic capacitance.

Referring to the array substrate 400 of fig. 10, for example, the first thin film transistor 61 may be moved in a direction close to the shared capacitor line 90 compared to the array substrate 100 of the first structure, for example, the source of the first thin film transistor 61 may be located on the extension line of the first shared capacitor section 92, the shared capacitor line 90 may include the first shared capacitor section 92 and the second shared capacitor section 93 compared to the array substrate of the first structure, one end of the first shared capacitor section 92 is electrically connected to the first thin film transistor 61, the other end of the first shared capacitor section 92 is electrically connected to one end of the second shared capacitor section 93, and the other end of the second shared capacitor section 93 is suspended.

In the array substrate 400 of the fourth structure as described above, since the auxiliary wiring 94 is omitted, the length of the sharing capacitor line 90 is reduced, and the parasitic capacitance between the sharing capacitor line 90 and the first pixel electrode 51 can be reduced.

It should be noted that, since the first thin film transistor 61 moves rightward, the first drain trace 33 includes a sixth drain segment 334 in addition to the first, second and

third drain segments

331, 332, 333 electrically connected in sequence, one end of the sixth drain segment 334 being electrically connected to the other end of the third drain segment 333, the other end of the sixth drain segment 334 being electrically connected to the drain of the first thin film transistor 61, as compared to the array substrate 100 of the first structure. The connection of the first drain segment 331, the second drain segment 332, and the third drain segment 333 is the same as that of the array substrate 100 with the first structure, and will not be described herein.

Referring to fig. 11 and 12, the forward projection of the sixth drain segment 334 and the second extension 642 (when the alignment dark stripe of the first region is a "swastika" dark stripe) or the fourth extension 652 of the alignment dark stripe 91 on the array substrate 400 has an overlapping region. Thus, the sixth drain segment 334 may be hidden under the alignment dark stripe 91 to reduce the effective aperture loss.

Fig. 13 is a schematic structural diagram of an array substrate with a fifth structure according to an embodiment of the present invention, and fig. 14 is a schematic structural diagram of an alignment dark stripe formed in the array substrate with the fifth structure according to an embodiment of the present invention.

In this embodiment, an array substrate 500 with a fifth structure is further provided, referring to fig. 13 and 14, the structure and the formation position of the first drain trace 33 are improved on the basis of the array substrate with the fourth structure 400 by the array substrate 500 with the fifth structure, and other parts are similar to the array substrate 400 with the fourth structure and are not repeated here.

As an example, referring to fig. 13, compared to the array substrate 400 of the fourth structure, in the first region 31, the first drain trace 33 includes, in order from bottom to top, a seventh drain segment 335, a first drain segment 331, a third drain segment 333, and a sixth drain segment 334, wherein one end of the seventh drain segment 335 is electrically connected to the drain of the second thin film transistor 62, the other end of the seventh drain segment 335 is electrically connected to one end of the first drain segment 331, the other end of the first drain segment 331 is electrically connected to one end of the third drain segment 333, the other end of the third drain segment 333 is electrically connected to one end of the sixth drain segment 334, and the other end of the sixth drain segment 334 is electrically connected to the drain of the first thin film transistor 61. Wherein the other end of the first drain segment 331 and one end of the third drain segment 333 are electrically connected to the first pixel electrode 51 through the first via hole 621. One end of the second drain segment 332 is electrically connected to the other end of the first drain segment 331, and the other end of the second drain segment 332 is suspended.

Thus, in the case where the alignment dark stripe 91 in the first region 31 is a "swamp" dark stripe, as in fig. 14, in the first drain trace 33, the seventh drain segment 335 and the sixth drain segment 334 may be hidden in the second extension 642, the first drain segment 331 and the third drain segment 333 may be hidden under the longitudinal portion 65, and the second drain segment 332 may be hidden under the lateral portion 64, so that the effective aperture ratio of the pixel can be improved.

In the case where the alignment dark stripe 91 in the first region 31 is an "8" -shaped dark stripe, although not shown, in the first drain trace 33, the seventh drain segment 335 and the sixth drain segment 334 may be hidden under the fourth extension 652, the first drain segment 331 and the third drain segment 333 may be hidden under the longitudinal portion 65, and the second drain segment 332 may be hidden under the lateral portion 64, so that the effective aperture ratio of the pixel may be improved.

In the array substrate 400 of the fifth structure described above, when the alignment dark lines 91 in the first region 31 are the "8" -shaped dark lines and the "Wan" -shaped dark lines, all of the first drain wirings 33 are hidden under the alignment dark lines 91.

Example two

The embodiment provides a display panel, which includes the

array substrate

100, 200, 300, 400, 500 of the embodiment, and further includes a color film substrate disposed opposite to the array substrate, a liquid crystal molecular layer is sandwiched between the array substrate and the color film substrate, and an electric field is applied between the array substrate and the color film substrate, so that a voltage in the electric field can control an arrangement condition of liquid crystal molecules in the liquid crystal molecular layer, thereby achieving the purposes of shading and transmitting light, and enabling the display panel to display images. The structure, function and working principle of the

array substrates

100, 200, 300, 400, 500 are described in detail in the first embodiment, and are not described herein again. The display panel provided in this embodiment adopts the

array substrates

100, 200, 300, 400, and 500 described in embodiment one, so that the effective aperture ratio of the pixels can be increased, and the light transmittance of the array substrate can be effectively improved.

Example III

The embodiment provides a photoalignment method of a display panel, which is applied to the display panel described in the second embodiment. The structure, function and working principle of the array substrate and the display panel including the same are described in detail in the first embodiment and the second embodiment, and are not described here again. As described above, the display panel has a color film substrate disposed opposite to the array substrate, and the color film substrate has first pixel units corresponding to the pixel units on the array substrate in one-to-one manner.

Fig. 15 is a schematic flow chart of a first photoalignment method of a display panel according to an embodiment of the present invention; fig. 16 is a schematic alignment structure diagram of a first photo-alignment method of a display panel according to an embodiment of the present invention.

Referring to fig. 15 and 16, the first photoalignment method of the display panel of the present embodiment includes:

s10, dividing each pixel unit into two vertical exposure areas arranged along a second direction S of the array substrate, and respectively aligning each vertical exposure area along a first direction F in the array substrate, wherein the alignment directions of the different vertical exposure areas are opposite.

In fig. 16, the color filter substrate and the array substrate are aligned, and the dashed arrow indicates the alignment direction of the array substrate side, and the solid arrow indicates the alignment direction of the color filter substrate side.

Specifically, in fig. 16, one pixel unit is divided into two

vertical exposure areas

71, 72 arranged along the second direction S of the array substrate, for example, the vertical exposure area 71 located on the left side of the second direction S is first aligned along the first direction F; the vertically exposed regions 72 located on the right side of the second direction S are then aligned in the first direction F. And the alignment directions of the two exposure areas are opposite. In fig. 16, an example will be described in which the alignment direction of the vertical exposure area 11 on the left side is the first direction F downward, and the alignment direction of the vertical exposure area 72 on the right side is the first direction F upward. Of course, other options are possible, as long as the opposite alignment directions of the two exposure areas are ensured.

S20, dividing each first pixel unit into a first exposure area, a second exposure area, a third exposure area and a fourth exposure area which are sequentially arranged along a first direction F; the alignment of each exposure area of the first pixel unit is carried out along a second direction S, wherein the alignment directions of the first exposure area and the fourth exposure area, and the alignment directions of the second exposure area and the third exposure area are the same; the alignment directions of the first exposure area and the third exposure area are opposite.

Specifically, referring to fig. 16, the first sub-pixel unit is divided into four exposure areas arranged in the first direction F, for example, four exposure areas correspond to a first exposure area 73, a second exposure area 74, a third exposure area 75, and a fourth exposure area 76 of a first row, a second row, a third row, and a fourth row, respectively. Wherein the alignment directions of the first exposure region 73 and the fourth exposure region 76, and the second exposure region 74 and the third exposure region 75 are the same; the alignment direction of the first exposure region 73 is opposite to that of the third exposure region 75. For example, in fig. 16, the alignment directions of the first exposure region 73, the second exposure region 74, the third exposure region 75, and the fourth exposure region 76 are respectively the second direction to the left, the second direction to the right, and the second direction to the left. It should be noted that the above step S20 is followed by a step of aligning the array substrate and the color film substrate. After the alignment is completed, reference is made to fig. 2 for a schematic diagram of the alignment shading in the obtained display panel. As can be seen from the figure, the first region 31 has dark fringes in the shape of "8", and the second region 32 has dark fringes in the shape of "swamp".

Fig. 17 is a schematic flow chart of a second photoalignment method of a display panel according to an embodiment of the present invention; fig. 18 is a schematic alignment structure diagram of a second photo-alignment method of a display panel according to an embodiment of the present invention; fig. 19 is a schematic diagram illustrating a simulation of alignment dark marks in a display panel obtained by aligning the display panel according to the second photo-alignment method of the present invention.

The alignment method of the present embodiment improves the alignment method of the color film substrate on the basis of the first optical alignment method, and referring to fig. 17 and 18, the second optical alignment method of the display panel of the present embodiment includes:

s100, dividing each pixel unit into two vertical exposure areas arranged along a second direction of the array substrate, and respectively aligning each vertical exposure area along a first direction of the array substrate, wherein the alignment directions of different vertical exposure areas are opposite. The alignment method for the array substrate in this embodiment is the same as the first optical alignment method, and will not be described here again.

S200, dividing each first pixel unit into four exposure areas which are sequentially arranged along a first direction, respectively aligning the four exposure areas along a second direction, and enabling the alignment directions of the adjacent exposure areas to be opposite.

In fig. 18, the color filter substrate and the array substrate are aligned, and the dashed arrow indicates the alignment direction of the array substrate side, and the solid arrow indicates the alignment direction of the color filter substrate side. Specifically, in fig. 18, the first sub-pixel unit is divided into four exposure areas arranged along the first direction F, for example, the four exposure areas correspond to a first exposure area 73, a second exposure area 74, a third exposure area 75, and a fourth exposure area 76 of a first row, a second row, a third row, and a fourth row, respectively. Wherein the alignment directions of the adjacent exposure areas are opposite. Illustratively, in fig. 16, the alignment directions of the first exposure region 73, the second exposure region 74, the third exposure region 75, and the fourth exposure region 76 are the second direction S to the right, the second direction S to the left, the second direction S to the right, and the second direction S to the left, respectively. The step S200 further includes the step of aligning the array substrate and the color film substrate. After the cartridge is completed, referring to the schematic simulation of the alignment dark pattern 91 shown in fig. 19, it can be seen that the dark pattern 91 of "swamp" appears in both the first region 31 and the second region 32.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. An array substrate is characterized by comprising a plurality of data lines extending along a first direction, a plurality of first grid lines and second grid lines extending along a second direction, and the plurality of data lines and the first grid lines limit the array substrate into a plurality of pixel units in a crisscross manner; a second gate line is arranged between every two adjacent first gate lines so as to divide each pixel unit into a first area and a second area;

the array substrate further includes: a first thin film transistor, a second thin film transistor, and a third thin film transistor, and a first pixel electrode covering the first region and a second pixel electrode covering the second region; the grid electrode of the first thin film transistor is electrically connected with the first grid line, the grid electrode of the second thin film transistor and the grid electrode of the third thin film transistor are electrically connected with the second grid line, the first thin film transistor and the second thin film transistor correspond to the first area, and the third thin film transistor corresponds to the second area, so that the voltage of the first pixel electrode is different from the voltage of the second pixel electrode;

The array substrate further comprises a substrate, a storage capacitor line formed on the substrate and a sharing capacitor line positioned above the storage capacitor line;

the storage capacitor line comprises a plurality of first storage capacitor sections with the extending direction parallel to the data line, and at least one first storage capacitor section is correspondingly arranged in each of the first area and the second area;

the first area and the second area are provided with alignment dark patterns, and the alignment dark patterns positioned in the center of the first area and the center of the second area are provided with transverse parts and longitudinal parts which are mutually intersected;

the alignment shading of the first region includes a third extension extending from both ends of the lateral portion to a direction away from the lateral portion;

a first drain wire for electrically connecting the drain electrode of the first thin film transistor and the drain electrode of the second thin film transistor is arranged in the first region, the first drain wire comprises a first drain section, a second drain section and a third drain section which are electrically connected in sequence from bottom to top, and one end of the first drain section is electrically connected with the drain electrode of the second thin film transistor;

in the first region, a portion of the first storage capacitor section corresponding to the first drain section is locally widened, and a widened portion is located directly under the first drain section; the orthographic projection of the third extension part of the alignment dark stripe corresponding to the first region, the first drain electrode section and at least one first storage capacitor section on the array substrate has an overlapping region;

The shared capacitor line comprises a first shared capacitor section extending along the first direction, wherein in the first region, a part of the first storage capacitor section corresponding to the first shared capacitor section is locally widened, and the widened part is positioned right below the first shared capacitor section; the orthographic projection of the third extension part of the alignment dark stripe corresponding to the first area, the first sharing capacitor section and at least one first storage capacitor section on the array substrate has an overlapping area;

the alignment shading of the second region comprises first extension parts respectively extending from two end parts of the transverse part to the direction away from the transverse part;

a second drain electrode wiring for electrically connecting the drain electrode of the third thin film transistor and the second pixel electrode is arranged in the second region, the second drain electrode wiring comprises a fourth drain electrode section and a fifth drain electrode section which are sequentially and electrically connected from top to bottom, and one end of the fourth drain electrode section is electrically connected with the drain electrode of the third thin film transistor;

in the second region, a portion of the first storage capacitor segment corresponding to the fourth drain segment is locally widened, and a widened portion is located directly under the fourth drain segment; and orthographic projections of the first extension part of the alignment dark stripe, the fourth drain electrode section and at least one first storage capacitor section corresponding to the second region on the array substrate are provided with an overlapping region.

2. The array substrate of claim 1, wherein an orthographic projection of at least a portion of the structure on the first drain trace and the alignment dark stripe corresponding to the first region on the array substrate has an overlapping region.

3. The array substrate according to claim 2, wherein the first gate line and the second gate line are in the same layer as the storage capacitor line, and orthographic projections of the storage capacitor line and the alignment dark lines corresponding to the first region and/or the second region on the array substrate have overlapping regions.

4. The array substrate of claim 3, wherein the orthographic projection of the first drain trace and the storage capacitor line on the array substrate has an overlapping region.

5. The array substrate of claim 3, wherein the data line is on the same layer as the shared capacitor line, the shared capacitor line is located in the first region, and orthographic projections of alignment dark lines corresponding to the shared capacitor line, the storage capacitor line, and the first region on the array substrate have overlapping regions.

6. The array substrate of claim 1, wherein a source of the first thin film transistor is located on an extension line of the first shared capacitor section.

7. The array substrate according to any one of claims 2 to 6, wherein the orthographic projection of at least part of the structure on the second drain trace and the alignment dark stripe corresponding to the second region on the array substrate has an overlapping region.

8. The array substrate of any one of claims 1 to 6, wherein,

orthographic projection of the end parts, close to the second gate lines, of the second gate lines and the first pixel electrodes on the array substrate has an overlapping area;

the orthographic projection of the end parts, close to the second gate lines, of the second gate lines and the second pixel electrodes on the array substrate has an overlapping area.

9. A display panel comprising a color film substrate, a liquid crystal layer, and an array substrate according to any one of claims 1 to 8, wherein the liquid crystal layer is sandwiched between the color film substrate and the array substrate.