CN112311418B - Dual-mode radio frequency receiving and transmitting switch - Google Patents
Dual-mode radio frequency receiving and transmitting switch Download PDFInfo
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- CN112311418B CN112311418B CN202011198505.5A CN202011198505A CN112311418B CN 112311418 B CN112311418 B CN 112311418B CN 202011198505 A CN202011198505 A CN 202011198505A CN 112311418 B CN112311418 B CN 112311418B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/44—Transmit/receive switching
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Abstract
Embodiments of the present disclosure provide a dual mode radio frequency transmit receive switch. The dual-mode radio frequency transceiving switch comprises a first radio frequency port TX _ OUT, a second radio frequency port TX _ IN, a third radio frequency port RITO, a fourth radio frequency port RX _ IN, a fifth radio frequency port RX _ OUT, a first transmission line TL1, a second transmission line TL2, a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4 and a fifth NMOS tube M5. The dual-mode radio frequency transceiving switch can work in multiple modes, and has the advantages of low loss, low cost, high isolation degree and high linearity.
Description
Technical Field
Embodiments of the present disclosure relate generally to the field of radio frequency integrated circuits, and more particularly, to a dual mode radio frequency transmit receive switch.
Background
The radio frequency transceiver switch is an important element in a wireless communication system, and realizes the conversion between a receiving mode and a transmitting mode by selecting different links. The traditional radio frequency transceiving switch has only one working mode.
In addition, the conventional transceiving switch generally adopts a method of increasing the width of the transistor to reduce the insertion loss, but the parasitic capacitance increases when the width of the transistor increases, which results in the deterioration of the isolation between the transmitting terminal and the receiving terminal. When the input signal power is large, the voltage swing applied to each element varies greatly, resulting in poor linearity of the element.
With the development of wireless communication technology, higher requirements are placed on the performance of the rf transceiver switch, and therefore, an rf transceiver switch capable of operating in multiple modes, with low loss, low cost, high isolation, and high linearity is necessary.
Disclosure of Invention
According to an embodiment of the present disclosure, a dual mode radio frequency transmit receive switch is provided. The dual-mode radio frequency transceiving switch comprises a first radio frequency port TX _ OUT, a second radio frequency port TX _ IN, a third radio frequency port RITO, a fourth radio frequency port RX _ IN, a fifth radio frequency port RX _ OUT, a first transmission line TL1, a second transmission line TL2, a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4 and a fifth NMOS tube M5; the drain of the first NMOS transistor M1 is connected to the first rf port TX _ OUT, the second rf port TX _ IN, and one end of the first transmission line TL1, and the source is connected to the drain of the second NMOS transistor M2; the source electrode of the second NMOS tube M2 is grounded; the drain electrode of the third NMOS transistor M3 is connected to the third radio frequency port RITO, the other end of the first transmission line TL1 and one end of the second transmission line TL2, and the source electrode is connected to the drain electrode of the fourth NMOS transistor M4; the source electrode of the fourth NMOS tube M4 is grounded; the drain of the fifth NMOS transistor M5 is connected to the fourth rf port RX _ IN, the fifth rf port RX _ OUT, and the other end of the second transmission line TL2, and the source is grounded.
In the above-described aspect and any possible implementation manner, an implementation manner is further provided, and the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4, and the fifth NMOS transistor are deep N-well NMOS transistors.
The above aspects and any possible implementations further provide an implementation where the first transmission line TL1 and the second transmission line TL2 are a quarter wavelength in length.
In the aspect and any possible implementation manner described above, there is further provided an implementation manner, in which the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4, and the fifth NMOS transistor M5 adopt a transistor parasitic optimization technology, and the gates are respectively connected to corresponding control terminals through series resistors; the substrates are grounded through series resistors, respectively.
The above-mentioned aspects and any possible implementation manner further provide an implementation manner, and the dual-mode radio frequency transceiving switch includes two modes, namely a transceiving multiplexing mode and a transceiving separating mode.
In the aspects and any possible implementation manners described above, an implementation manner is further provided, in a receiving mode of the transceiving multiplexing mode, the first NMOS transistor M1 and the second NMOS transistor M2 are turned on, the third NMOS transistor M3, the fourth NMOS transistor M4 and the fifth NMOS transistor M5 are turned off, and a signal flows in from the third rf port RITO and flows OUT from the fifth rf port RX _ OUT;
IN a transmitting mode of a transceiving multiplexing mode, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3 and the fourth NMOS transistor M4 are turned off, the fifth NMOS transistor M5 is turned on, and a signal flows IN from the second rf port TX _ IN and flows out from the third rf port RITO;
IN a receiving mode of the transceiving split mode, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are turned on, the fifth NMOS transistor M5 is turned off, and a signal flows IN from the fourth rf port RX _ IN and flows OUT from the fifth rf port RX _ OUT;
IN a transmitting mode of the transmit-receive separation mode, the first NMOS transistor M1 and the second NMOS transistor M2 are turned off, the third NMOS transistor M3, the fourth NMOS transistor M4 and the fifth NMOS transistor M5 are turned on, and a signal flows IN from the second rf port TX _ IN and flows OUT from the first rf port TX _ OUT.
As for the above aspect and any possible implementation manner, there is further provided an implementation manner that when the control terminal is at a low level, the corresponding NMOS transistor is turned off; when the control end is at high level, the corresponding NMOS tube is conducted.
IN the aspect and any possible implementation manner described above, an implementation manner is further provided, IN which a drain of the fifth NMOS transistor M5 is connected to the fourth rf port RX _ IN, the fifth rf port RX _ OUT, and the other end of the second transmission line TL2, and a source is connected to a drain of the sixth NMOS transistor M6; the source of the sixth NMOS transistor M6 is grounded.
It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements, and wherein:
fig. 1 illustrates a schematic structural diagram of a dual mode rf transceiver switch according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
Fig. 1 is a schematic structural diagram of a dual mode rf transceiver switch according to an embodiment of the present disclosure, as shown in fig. 1, the dual mode rf transceiver switch includes:
the first radio frequency port TX _ OUT, the second radio frequency port TX _ IN, the third radio frequency port RITO, the fourth radio frequency port RX _ IN, the fifth radio frequency port RX _ OUT, the first transmission line TL1, the second transmission line TL2, the first NMOS tube M1, the second NMOS tube M2, the third NMOS tube M3, the fourth NMOS tube M4 and the fifth NMOS tube M5; wherein the content of the first and second substances,
the drain of the first NMOS transistor M1 is connected to the first rf port TX _ OUT, the second rf port TX _ IN and one end of the first transmission line TL1, and the source is connected to the drain of the second NMOS transistor M2;
the source electrode of the second NMOS tube M2 is grounded;
the drain electrode of the third NMOS transistor M3 is connected to the third radio frequency port RITO, the other end of the first transmission line TL1 and one end of the second transmission line TL2, and the source electrode is connected to the drain electrode of the fourth NMOS transistor M4;
the source electrode of the fourth NMOS tube M4 is grounded;
the drain of the fifth NMOS transistor M5 is connected to the fourth rf port RX _ IN, the fifth rf port RX _ OUT, and the other end of the second transmission line TL2, and the source is grounded.
The first NMOS transistor M1 is connected in series with the second NMOS transistor M2;
the first NMOS tube M1 and the second NMOS tube M2 which are connected IN series are connected IN parallel with the first radio frequency port TX _ OUT and the second radio frequency port TX _ IN;
the third NMOS transistor M3 is connected in series with the fourth NMOS transistor M4;
the fifth NMOS transistor M5 is connected IN parallel to the fourth rf port RX _ IN and the fifth rf port RX _ OUT.
In some embodiments, the first NMOS transistor M1 is connected in series with the second NMOS transistor M2, and the third NMOS transistor M3 is connected in series with the fourth NMOS transistor M4, so that the voltage swing of a single NMOS transistor is reduced and the linearity is improved by adopting a stacked transistor technology.
Since the power and voltage swing of the general receiving circuit is not large, a single fifth NMOS transistor M5 is adopted. In some embodiments, the fifth NMOS transistor M5 and the sixth NMOS transistor M6 may be connected in series (the sixth NMOS transistor M6 is not shown in fig. 1, and the specific structure, connection manner, and control manner are similar to those of the first NMOS transistor M1 and the second NMOS transistor M2, and the third NMOS transistor M3 and the fourth NMOS transistor M4 are connected in series, which is not described herein again).
In some embodiments, the lengths of the first transmission line TL1 and the second transmission line TL2 are quarter wavelengths, so as to improve the isolation of the receiving branch and the transmitting branch.
In some embodiments, the dual-mode rf transceiver switch includes two modes, a transmit-receive multiplexing mode and a transmit-receive separation mode;
in a receiving mode of the transceiving multiplexing mode, the first NMOS transistor M1 and the second NMOS transistor M2 are switched on, and the third NMOS transistor M3, the fourth NMOS transistor M4 and the fifth NMOS transistor M5 are switched off; since the first NMOS transistor M1 and the second NMOS transistor M2 connected IN parallel with the transmitting branch (the first rf port TX _ OUT and the second rf port TX _ IN) are turned on and grounded, the receiving branch operates, and a signal flows IN from the third rf port RITO and flows OUT from the fifth rf port RX _ OUT;
in a transmitting mode of a transceiving multiplexing mode, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3 and the fourth NMOS transistor M4 are disconnected, and the fifth NMOS transistor M5 is connected; since the fifth NMOS transistor M5 connected IN parallel to the fourth rf port RX _ IN and the fifth rf port RX _ OUT is turned on and grounded, a signal flows IN from the second rf port TX _ IN and flows OUT from the third rf port RITO;
in a receiving mode of the transceiving separation mode, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3 and the fourth NMOS transistor M4 are turned on, and the fifth NMOS transistor M5 is turned off; since the first NMOS transistor M1-the second NMOS transistor M2 connected IN parallel with the first rf port TX _ OUT and the second rf port TX _ IN are turned on and grounded, and the third NMOS transistor M3-the fourth NMOS transistor M4 connected IN parallel with the third rf port RITO are turned on and grounded, a signal flows IN from the fourth rf port RX _ IN and flows OUT from the fifth rf port RX _ OUT;
in a transmitting mode of the transceiving separation mode, the first NMOS transistor M1 and the second NMOS transistor M2 are disconnected, and the third NMOS transistor M3, the fourth NMOS transistor M4 and the fifth NMOS transistor M5 are connected; since the fifth NMOS transistor M5 connected IN parallel to the fourth rf port RX _ IN and the fifth rf port RX _ OUT is turned on and grounded, and the third NMOS transistor M3 — the fourth NMOS transistor M4 connected IN parallel to the third rf port RITO is turned on and grounded, a signal flows IN from the second rf port TX _ IN and flows OUT from the first rf port TX _ OUT.
In some embodiments, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4, and the fifth NMOS transistor M5 are controlled by the first control terminal Vc1, the second control terminal Vc2, the third control terminal Vc3, the fourth control terminal Vc4, and the fifth control terminal Vc5, respectively; when the control end is at low level, for example 0V, the corresponding NMOS tube is disconnected; when the control terminal is at a high level, for example, 1V, the corresponding NMOS transistor is turned on.
In some embodiments, the gate of the first NMOS transistor M1 is connected to the first control terminal Vc1, the gate of the second NMOS transistor M2 is connected to the second control terminal Vc2, the gate of the third NMOS transistor M3 is connected to the third control terminal Vc3, the gate of the fourth NMOS transistor M4 is connected to the fourth control terminal Vc4, and the gate of the fifth NMOS transistor M5 is connected to the fifth control terminal Vc 5.
In some embodiments, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4, and the fifth NMOS transistor M5 all use a transistor parasitic optimization technique, and the gate is respectively connected in series with a high-ohmic first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5 to improve isolation, so as to reduce the influence of parasitic capacitance between the gate and the source, and parasitic capacitance between the gate and the drain; the substrate is grounded through a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10 which are connected in series with high-ohmic resistors respectively, and is used for body end suspension, so that the influence of substrate parasitic capacitance is reduced, insertion loss is reduced, linearity is improved, and in order to further improve isolation, the resistance values of all the body suspension resistors are large enough. The gate of the first NMOS transistor M1 is connected to one end of a first resistor R1, and the other end of the first resistor R1 is connected to a first control terminal Vc 1; the gate of the second NMOS transistor M2 is connected to one end of a second resistor R2, and the other end of the second resistor R2 is connected to a second control terminal Vc 2; the gate of the third NMOS transistor M3 is connected to one end of a third resistor R3, and the other end of the third resistor R3 is connected to a third control terminal Vc 3; the gate of the fourth NMOS transistor M4 is connected to one end of a fourth resistor R4, and the other end of the fourth resistor R4 is connected to a fourth control terminal Vc 4; the gate of the fifth NMOS transistor M5 is connected to one end of a fifth resistor R5, and the other end of the fifth resistor R5 is connected to a fifth control terminal Vc 5. The body end of the first NMOS transistor M1 is connected with one end of a sixth resistor R6, and the other end of the sixth resistor R6 is grounded; the body end of the second NMOS transistor M2 is connected with one end of a seventh resistor R7, and the other end of the seventh resistor R7 is grounded; the body end of the third NMOS transistor M3 is connected with one end of an eighth resistor R8, and the other end of the eighth resistor R8 is grounded; the body end of the fourth NMOS transistor M4 is connected with one end of a ninth resistor R9, and the other end of the ninth resistor R9 is grounded; the body end of the fifth NMOS transistor M5 is connected to one end of the tenth resistor R10, and the other end of the tenth resistor R10 is grounded.
In some embodiments, the resistors R1-R10 are all 10K ohms.
In some embodiments, the return loss of the dual-mode radio frequency transceiving switch is better than-15 dB, the isolation is better than-20 dB, and the insertion loss is better than-2 dB.
According to the embodiment of the disclosure, the following technical effects are achieved:
(1) the transceiver has two modes of transceiving multiplexing and transceiving separation, and can meet different use requirements;
(2) the isolation of receiving and transmitting branches is improved by adopting a parallel switch and a transmission line structure with the length of one quarter of wavelength;
(3) the voltage swing of the transistor is reduced and the linearity is improved by adopting a stacked transistor technology;
(4) by adopting a transistor parasitic optimization technology and a deep N-well process body suspension technology, the influence of parasitic capacitance and substrate noise of a transistor is reduced, the insertion loss is reduced, and the linearity is improved.
Those skilled in the art will appreciate that the embodiments described in this specification are exemplary and that no acts or modules are necessarily required by the disclosure. While several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (6)
1. A dual mode radio frequency transmit receive switch, comprising:
the first radio frequency port TX _ OUT, the second radio frequency port TX _ IN, the third radio frequency port RITO, the fourth radio frequency port RX _ IN, the fifth radio frequency port RX _ OUT, the first transmission line TL1, the second transmission line TL2, the first NMOS tube M1, the second NMOS tube M2, the third NMOS tube M3, the fourth NMOS tube M4 and the fifth NMOS tube M5; wherein the content of the first and second substances,
the drain of the first NMOS transistor M1 is connected to the first rf port TX _ OUT, the second rf port TX _ IN and one end of the first transmission line TL1, and the source is connected to the drain of the second NMOS transistor M2;
the source electrode of the second NMOS tube M2 is grounded;
the drain electrode of the third NMOS transistor M3 is connected to the third radio frequency port RITO, the other end of the first transmission line TL1 and one end of the second transmission line TL2, and the source electrode is connected to the drain electrode of the fourth NMOS transistor M4;
the source electrode of the fourth NMOS tube M4 is grounded;
the drain of the fifth NMOS transistor M5 is connected to the fourth rf port RX _ IN, the fifth rf port RX _ OUT, and the other end of the second transmission line TL2, and the source is grounded;
the dual-mode radio frequency transceiving switch comprises a transceiving multiplexing mode and a transceiving separation mode;
in a receiving mode of a transceiving multiplexing mode, the first NMOS transistor M1 and the second NMOS transistor M2 are turned on, the third NMOS transistor M3, the fourth NMOS transistor M4 and the fifth NMOS transistor M5 are turned off, and a signal flows in from the third radio frequency port RITO and flows OUT from the fifth radio frequency port RX _ OUT;
IN a transmitting mode of a transceiving multiplexing mode, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3 and the fourth NMOS transistor M4 are turned off, the fifth NMOS transistor M5 is turned on, and a signal flows IN from the second rf port TX _ IN and flows out from the third rf port RITO;
IN a receiving mode of the transceiving split mode, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are turned on, the fifth NMOS transistor M5 is turned off, and a signal flows IN from the fourth rf port RX _ IN and flows OUT from the fifth rf port RX _ OUT;
IN a transmitting mode of the transmit-receive separation mode, the first NMOS transistor M1 and the second NMOS transistor M2 are turned off, the third NMOS transistor M3, the fourth NMOS transistor M4 and the fifth NMOS transistor M5 are turned on, and a signal flows IN from the second rf port TX _ IN and flows OUT from the first rf port TX _ OUT.
2. A dual mode radio frequency transceiver switch as defined in claim 1,
the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4 and the fifth NMOS transistor are deep N-well NMOS transistors.
3. A dual mode radio frequency transceiver switch as defined in claim 1,
the first transmission line TL1 and the second transmission line TL2 are quarter-wavelength long.
4. A dual mode radio frequency transceiver switch as defined in claim 1,
the first NMOS tube M1, the second NMOS tube M2, the third NMOS tube M3, the fourth NMOS tube M4 and the fifth NMOS tube M5 adopt a transistor parasitic optimization technology, and the grid electrodes of the first NMOS tube M1, the second NMOS tube M2, the third NMOS tube M3, the fourth NMOS tube M4 and the fifth NMOS tube M5 are respectively connected with corresponding control ends through series resistors; the substrates are grounded through series resistors, respectively.
5. A dual mode radio frequency transceiver switch as defined in claim 1,
when the control end is at a low level, the corresponding NMOS tube is disconnected; when the control end is at high level, the corresponding NMOS tube is conducted.
6. A dual mode radio frequency transceiver switch as defined in claim 1,
the drain of the fifth NMOS transistor M5 is connected to the fourth rf port RX _ IN, the fifth rf port RX _ OUT, and the other end of the second transmission line TL2, and the source is connected to the drain of the sixth NMOS transistor M6;
the source of the sixth NMOS transistor M6 is grounded.
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| CN202011198505.5A CN112311418B (en) | 2020-10-31 | 2020-10-31 | Dual-mode radio frequency receiving and transmitting switch |
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| CN202011198505.5A CN112311418B (en) | 2020-10-31 | 2020-10-31 | Dual-mode radio frequency receiving and transmitting switch |
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| CN105227167B (en) * | 2015-09-21 | 2018-09-25 | 温州大学 | A kind of cmos switch circuit |
| CN107994918B (en) * | 2017-12-21 | 2024-05-10 | 武汉华讯国蓉科技有限公司 | Single-pole double-throw switch for radio frequency receiving and transmitting switching |
| CN210640865U (en) * | 2019-12-23 | 2020-05-29 | 中国电子科技集团公司第五十四研究所 | CMOS millimeter wave ultra-wideband parallel asymmetric single-pole double-throw switch |
| CN210640864U (en) * | 2019-12-23 | 2020-05-29 | 中国电子科技集团公司第五十四研究所 | CMOS millimeter wave series asymmetric single-pole double-throw switch |
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