CN112311385B - Gate-controlled clock circuit - Google Patents
Gate-controlled clock circuit Download PDFInfo
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- CN112311385B CN112311385B CN202011195633.4A CN202011195633A CN112311385B CN 112311385 B CN112311385 B CN 112311385B CN 202011195633 A CN202011195633 A CN 202011195633A CN 112311385 B CN112311385 B CN 112311385B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
Embodiments of the present disclosure provide a gated clock circuit. The gated clock circuit comprises a first synchronous circuit M1, a second synchronous circuit M2, a two-input AND gate M3 and an inverter M4; a CP port of the first synchronous circuit M1 is accessed to an input clock pulse signal CP, an RDN port is accessed to an RSTN signal, and a D port is accessed to a power supply VDD; a CP port of the second synchronous circuit M2 is accessed to an input clock pulse signal CP, an RDN port is accessed to a Q port of the first synchronous circuit M1, and a D port is accessed to an EN enabling signal; the A port of the two-input AND gate M3 is accessed to the Q port of the second synchronous circuit M2, and the B port is accessed to the input clock pulse signal CP; the output signal of the Q port of the two-input AND gate M3 is an output clock Q; the I port of the inverter M4 is connected to the Q port of the two-input AND gate M3; the output signal of the QN port of the inverter M4 is the output clock QN. In this way, the output clock state can be determined when the clock is closed, and no burr is generated in the clock switching process.
Description
Technical Field
Embodiments of the present disclosure relate generally to the field of digital circuit technology, and more particularly, to a gated clock circuit.
Background
In digital circuits, the circuit operates according to a clock signal. When the circuit does not need to operate, the clock may be turned off in order to save power. The circuit used to control the clock on or off is a clock gating circuit.
The output clock of a conventional clock gating circuit may be high or low when it is turned off, depending on the state of the input clock. When the input clock state is indeterminate, the state when the output clock is off is indeterminate. Under the scene that a digital circuit has strict requirements on the clock closing state, the traditional gated clock circuit cannot meet the requirements.
Disclosure of Invention
According to an embodiment of the present disclosure, a gated clock circuit is provided, which includes a first synchronization circuit M1, a second synchronization circuit M2, a two-input and gate M3, and an inverter M4; the CP port of the first synchronous circuit M1 is accessed to an input clock pulse signal CP, the RDN port is accessed to an RSTN signal, and the D port is accessed to a power supply VDD; a CP port of the second synchronous circuit M2 is accessed to an input clock pulse signal CP, an RDN port is accessed to a Q port of the first synchronous circuit M1, and a D port is accessed to an EN enabling signal; the A port of the two-input AND gate M3 is accessed to the Q port of the second synchronous circuit M2, and the B port is accessed to the input clock pulse signal CP; the output signal of the Q port of the two-input AND gate M3 is the output clock Q of the gated clock circuit; the I port of the inverter M4 is connected with the Q port of the two-input AND gate M3; the output signal of the QN port of the inverter M4 is the output clock QN of the clock gating circuit.
As for the above-mentioned aspects and any possible implementation manners, an implementation manner is further provided, in which the input clock pulse signal CP accessed by the CP port of the first synchronization circuit M1 and the input clock pulse signal CP accessed by the CP port of the second synchronization circuit M2 are synchronized with the input clock pulse signal CP accessed by the B port of the two-input and gate M3.
As for the above-mentioned aspects and any possible implementation, an implementation is further provided, when RSTN =0, en =0, the Q port of the two-input and gate M3 is low, and the QN port of the inverter M4 is high.
As for the above-mentioned aspects and any possible implementation manner, an implementation manner is further provided, when RSTN =1, en changes from 0 to 1, the clock signal Q output by the Q port of the two-input and gate M3 is synchronized with CP, and the clock signal QN output by the QN port of the inverter M4 is inverted with CP.
As with the aspect and any possible implementation described above, there is further provided an implementation in which, when RSTN =1, en changes from 1 to 0, the Q port of the two-input and gate M3 is low, and the QN port of the inverter M4 is high.
It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements, and wherein:
FIG. 1 shows a block diagram of a clock gating circuit according to an embodiment of the present disclosure;
fig. 2 shows a timing diagram of a clock gating circuit according to an embodiment of the disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
In addition, the term "and/or" herein is only one kind of association relationship describing the association object, and means that there may be three kinds of relationships, for example, a and/or B, and may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.
Fig. 1 shows a block diagram of a clock gating circuit according to an embodiment of the present disclosure. As shown in fig. 1, the clock gating circuit includes:
the synchronous circuit comprises a first synchronous circuit M1, a second synchronous circuit M2, a two-input AND gate M3 and an inverter M4; wherein the content of the first and second substances,
a CP port of the first synchronous circuit M1 is accessed to a clock pulse signal CP, an RDN port is accessed to an RSTN signal (low level is effective), and a D port is accessed to a power supply VDD;
a CP port of the second synchronous circuit M2 is accessed to a clock pulse signal CP, an RDN port is accessed to a Q port of the first synchronous circuit M1, and a D port is accessed to an EN enabling signal (high level is effective);
the A port of the two-input AND gate M3 is accessed to the Q port of the second synchronous circuit M2, and the B port is accessed to the clock pulse signal CP;
the I port of the inverter M4 is connected with the Q port of the two-input AND gate M3;
in some embodiments, the input clock pulse signal CP accessed by the CP port of the first synchronization circuit M1 and the input clock pulse signal CP accessed by the CP port of the second synchronization circuit M2 are synchronized with the input clock pulse signal CP accessed by the B port of the two-input and gate M3.
In some embodiments, the output signal of the Q port of the two-input and gate M3 is the output clock Q of the clock gating circuit, and the output signal of the QN port of the inverter M4 is the output clock QN of the clock gating circuit.
Fig. 2 shows a timing diagram of a clock gating circuit according to an embodiment of the present disclosure, as shown in fig. 2,
when RSTN =0,en =0, the first synchronization circuit M1 is reset, and its Q port is low; since the RDN port of the second synchronization circuit M2 is connected to the Q port of the first synchronization circuit M1, the second synchronization circuit M2 is reset, and the Q port thereof is at a low level; since the a port of the two-input and gate M3 is connected to the Q port of the second synchronization circuit M2, when the a port is at a low level, the Q port of the two-input and gate M3 is at a low level, and the QN port of the inverter M4 is at a high level. It can be seen that the output clock Q, QN states are deterministic, independent of the input clock CP.
When RSTN =1, the first synchronization circuit M1 operates, and since the CP rising edge is active, the Q port of the first synchronization circuit M1 is synchronized with the first CP rising edge, and the output is 1; when CP =0, keep the original state unchanged, the output is still 1; since the RDN port of the second synchronization circuit M2 is connected to the Q port of the first synchronization circuit M1, the second synchronization circuit M2 works, which includes the following two cases:
when EN is changed from 0 to 1, the Q port of the second synchronous circuit M2 is synchronous with the rising edge of the first CP, and the output is 1; when CP =0, the output remains 1 as it is. It can be seen that the a port of the two-input and gate M3 changes from 0 to 1 in synchronization with the first CP rising edge, and no glitch is generated. The clock signal Q and CP output from Q port of two-input AND gate M3 are synchronous, and the clock signal QN and CP output from QN port of inverter M4 are inverse.
When EN is changed from 1 to 0, the Q port of the second synchronous circuit M2 is synchronous with the rising edge of the first CP, and the output is 0; when CP =0, the output remains 0 as it is. It can be seen that the a port of the two-input and gate M3 changes from 1 to 0 in synchronization with the first CP rising edge, and no glitch is generated. The Q port of the two-input and gate M3 is low, and the QN port of the inverter M4 is high.
According to the embodiment of the disclosure, the following technical effects are achieved:
when the output clock is closed, the state of the output clock is determined, and the scene with strict requirements on the closed state of the clock is met;
no glitch is generated during the clock switching process.
It should be noted that for simplicity of description, the foregoing embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present disclosure is not limited by the order of acts, as some steps may occur in other orders or concurrently with other steps in accordance with the disclosure. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.
Further, while operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (4)
1. A gated clock circuit, comprising:
the synchronous circuit comprises a first synchronous circuit M1, a second synchronous circuit M2, a two-input AND gate M3 and an inverter M4; wherein the content of the first and second substances,
a CP port of the first synchronous circuit M1 is accessed to an input clock pulse signal CP, an RDN port is accessed to an RSTN signal, and a D port is accessed to a power supply VDD;
a CP port of the second synchronous circuit M2 is accessed to an input clock pulse signal CP, an RDN port is accessed to a Q port of the first synchronous circuit M1, and a D port is accessed to an EN enabling signal;
the port A of the two-input AND gate M3 is connected to the port Q of the second synchronous circuit M2, and the port B is connected to the input clock pulse signal CP; the output signal of the Q port of the two-input AND gate M3 is the output clock Q of the gated clock circuit;
the I port of the inverter M4 is connected with the Q port of the two-input AND gate M3; the output signal of the QN port of the inverter M4 is the output clock QN of the gating clock circuit;
the input clock pulse signal CP accessed to the CP port of the first synchronization circuit M1 and the input clock pulse signal CP accessed to the CP port of the second synchronization circuit M2 are synchronized with the input clock pulse signal CP accessed to the B port of the two-input and gate M3.
2. The clock-gating circuit of claim 1,
when RSTN =0,en =0, the Q port of the two-input and gate M3 is low, and the QN port of the inverter M4 is high.
3. The clock gating circuit of claim 1,
when RSTN =1 and en changes from 0 to 1, the clock signal Q output from the Q port of the two-input and gate M3 is synchronized with CP, and the clock signal QN output from the QN port of the inverter M4 is inverted from CP.
4. The clock-gating circuit of claim 1,
when RSTN =1, en changes from 1 to 0, the Q port of the two-input and gate M3 is at a low level, and the QN port of the inverter M4 is at a high level.
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| CN202011195633.4A CN112311385B (en) | 2020-10-31 | 2020-10-31 | Gate-controlled clock circuit |
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| CN202011195633.4A CN112311385B (en) | 2020-10-31 | 2020-10-31 | Gate-controlled clock circuit |
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| CN112311385A CN112311385A (en) | 2021-02-02 |
| CN112311385B true CN112311385B (en) | 2022-10-18 |
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| US8604825B2 (en) * | 2011-01-19 | 2013-12-10 | Micro RDC | Radiation hardened circuit design for multinode upsets |
| JP5947099B2 (en) * | 2011-05-20 | 2016-07-06 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| CN103197728B (en) * | 2012-01-06 | 2017-07-04 | 上海华虹集成电路有限责任公司 | The implementation method and circuit of different clock-domains burr-free clock switching circuit |
| CN104202032B (en) * | 2014-07-04 | 2017-04-19 | 东南大学 | Single-phase clock low-level asynchronous reset low-power consumption trigger and control method thereof |
| TWI575875B (en) * | 2015-10-29 | 2017-03-21 | 智原科技股份有限公司 | Flip-flop circuit |
| CN106452394B (en) * | 2016-07-22 | 2019-05-14 | 天津大学 | A kind of clock switching construction with auto-reset function |
| CN109756207A (en) * | 2018-11-21 | 2019-05-14 | 西北工业大学 | A kind of TSPC edge triggered flip flop with automatic feedback gated clock |
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