CN112311345A - Adjustable gain equalizer - Google Patents
Adjustable gain equalizer Download PDFInfo
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- CN112311345A CN112311345A CN202011195637.2A CN202011195637A CN112311345A CN 112311345 A CN112311345 A CN 112311345A CN 202011195637 A CN202011195637 A CN 202011195637A CN 112311345 A CN112311345 A CN 112311345A
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- nmos transistor
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- adjustable gain
- gain equalizer
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- 230000005540 biological transmission Effects 0.000 claims abstract description 40
- 238000005516 engineering process Methods 0.000 claims abstract description 10
- 230000003071 parasitic effect Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005457 optimization Methods 0.000 claims abstract description 5
- 238000007667 floating Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 8
- 239000000725 suspension Substances 0.000 abstract description 4
- 238000003780 insertion Methods 0.000 abstract description 3
- 230000037431 insertion Effects 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 3
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G9/00—Combinations of two or more types of control, e.g. gain control and tone control
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3089—Control of digital or coded signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G5/00—Tone control or bandwidth control in amplifiers
- H03G5/005—Tone control or bandwidth control in amplifiers of digital signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G5/00—Tone control or bandwidth control in amplifiers
- H03G5/16—Automatic control
- H03G5/165—Equalizers; Volume or gain control in limited frequency bands
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
Embodiments of the present disclosure provide an adjustable gain equalizer. The adjustable gain equalizer comprises a first radio frequency port RF _ IN, a second radio frequency port RF _ OUT, a first resonance unit, a second resonance unit and a third transmission line TL 3; the first resonance unit comprises a first NMOS transistor M1, a second NMOS transistor M2 and a first transmission line TL 1; the second resonant unit includes a third NMOS transistor M3, a fourth NMOS transistor M4, and a second transmission line TL 2. The adjustable gain equalizer has 2 bits adjustable and four equalization modes, and can meet different use requirements; by adopting the CMOS process, the method has the advantages of low loss, low cost, easy integration and the like; by adopting a transistor parasitic optimization technology and a deep N-well process body suspension technology, the influence of parasitic capacitance and substrate noise of a transistor is reduced, the insertion loss is reduced, and the linearity is improved.
Description
Technical Field
Embodiments of the present disclosure relate generally to the field of radio frequency integrated circuit technology, and more particularly, to an adjustable gain equalizer.
Background
The development of wireless communication technology puts higher demands on the research of radio frequency front end of a wireless transceiver. The radio frequency front end of the wireless transceiver realized by adopting discrete components has high price and large volume and cannot meet the increasing application requirements. The CMOS silicon-based process has the advantages of low power consumption, small area, low cost, high speed, high integration level, high anti-interference capability, etc., and has become the mainstream process technology of large-scale integrated circuits.
In a radio frequency front-end system of a wireless transceiver, the cascade connection of multiple stages of amplifying circuits easily causes large gain fluctuation, so that signals are distorted, and the communication quality and the transmission speed of the system are affected. The equalizer can generate a gain curve opposite to that of the original system, and the amplitude of the signals at each frequency point in the band is ensured to be consistent. The gain slope of the traditional equalizer is fixed, only a specific gain curve can be compensated, and the application limitation is large.
Disclosure of Invention
According to an embodiment of the present disclosure, an adjustable gain equalizer is provided. The adjustable gain equalizer comprises a first radio frequency port RF _ IN, a second radio frequency port RF _ OUT, a first resonance unit, a second resonance unit and a third transmission line TL 3; the first resonance unit comprises a first NMOS tube M1, a second NMOS tube M2 and a first transmission line TL1, the first NMOS tube M1 and the second NMOS tube M2 are connected IN parallel, the drain electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2 are connected with a first radio frequency port RF _ IN and one end of a third transmission line TL3, and the source electrode of the first NMOS tube M1 and the source electrode of the second NMOS tube M2 are connected with one end of the first transmission line TL 1; the other end of the first transmission line TL1 is suspended; the second resonance unit comprises a third NMOS transistor M3, a fourth NMOS transistor M4 and a second transmission line TL2, the third NMOS transistor M3 and the fourth NMOS transistor M4 are connected in parallel, the drain of the third NMOS transistor M2 and the drain of the fourth NMOS transistor M4 are connected with a second radio frequency port RF _ OUT and one end of a third transmission line TL3, and the source of the third NMOS transistor M3 and the source of the fourth NMOS transistor M4 are connected with one end of the second transmission line TL 2; the other end of the second transmission line TL2 is floating.
In the above-described aspect and any possible implementation manner, an implementation manner is further provided, and the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are deep N-well NMOS transistors.
The above aspects and any possible implementations further provide an implementation where the first transmission line TL1 and the second transmission line TL2 are a quarter wavelength in length.
In the aspect and any possible implementation manner described above, there is further provided an implementation manner, in which the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 adopt a transistor parasitic optimization technology, and the gates are respectively connected to the corresponding control terminals through series resistors; the substrates are grounded through series resistors, respectively.
As for the above-mentioned aspect and any possible implementation manner, there is further provided an implementation manner, gates of the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are respectively connected to the first control terminal Vc1, the second control terminal Vc2, the third control terminal Vc3, and the fourth control terminal Vc 4.
The above-mentioned aspect and any possible implementation manner further provide an implementation manner, where the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are turned off, and the adjustable gain equalizer operates in the first equalization mode; the first NMOS transistor M1 and the third NMOS transistor M3 are disconnected, the second NMOS transistor M2 and the fourth NMOS transistor M4 are connected, and the adjustable gain equalizer works in a second equalization mode; the first NMOS transistor M1 and the third NMOS transistor M3 are switched on, the second NMOS transistor M2 and the fourth NMOS transistor M4 are switched off, and the adjustable gain equalizer works in a third equalization mode; the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3 and the fourth NMOS transistor M4 are turned on, and the adjustable gain equalizer works in a fourth equalization mode.
As for the above aspect and any possible implementation manner, there is further provided an implementation manner that when the control terminal is at a low level, the corresponding NMOS transistor is turned off; when the control end is at high level, the corresponding NMOS tube is conducted.
It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements, and wherein:
fig. 1 shows a schematic structural diagram of an adjustable gain equalizer according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
Fig. 1 is a schematic structural diagram of an adjustable gain equalizer according to an embodiment of the present disclosure, and as shown in fig. 1, the adjustable gain equalizer includes:
comprises a first radio frequency port RF _ IN, a second radio frequency port RF _ OUT, a first resonance unit, a second resonance unit and a third transmission line TL 3; wherein the content of the first and second substances,
the first resonant unit comprises a first NMOS transistor M1, a second NMOS transistor M2 and a first transmission line TL1,
the first NMOS tube M1 and the second NMOS tube M2 are connected IN parallel, the drain electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2 are connected with the first radio frequency port RF _ IN and one end of a third transmission line TL3, and the source electrode of the first NMOS tube M1 and the source electrode of the second NMOS tube M2 are connected with one end of a first transmission line TL 1; the first transmission line TL1 is an open-circuit transmission line branch, and the other end of the first transmission line TL1 is suspended;
the second resonant unit comprises a third NMOS transistor M3, a fourth NMOS transistor M4 and a second transmission line TL2,
the third NMOS transistor M3 is connected in parallel with the fourth NMOS transistor M4, a drain of the third NMOS transistor M2 and a drain of the fourth NMOS transistor M4 are connected to the second RF port RF _ OUT and one end of the third transmission line TL3, and a source of the third NMOS transistor M3 and a source of the fourth NMOS transistor M4 are connected to one end of the second transmission line TL 2; the second transmission line TL2 is an open-circuit transmission line stub with the other end floating.
In some embodiments, the first and second transmission lines TL1, TL2 are one-quarter wavelength long.
In some embodiments, the third transmission line TL3 is used for interstage matching of the two-stage resonant cell.
In some embodiments, the adjustable gain equalizer comprises four equalization modes, each implementing four equalization amounts;
the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3 and the fourth NMOS transistor M4 are disconnected, and the adjustable gain equalizer works in a first equalization mode;
the first NMOS transistor M1 and the third NMOS transistor M3 are disconnected, the second NMOS transistor M2 and the fourth NMOS transistor M4 are connected, and the adjustable gain equalizer works in a second equalization mode;
the first NMOS transistor M1 and the third NMOS transistor M3 are switched on, the second NMOS transistor M2 and the fourth NMOS transistor M4 are switched off, and the adjustable gain equalizer works in a third equalization mode;
the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3 and the fourth NMOS transistor M4 are turned on, and the adjustable gain equalizer works in a fourth equalization mode.
The first NMOS transistor M1 and the third NMOS transistor M3 have the same size, and the second NMOS transistor M2 and the fourth NMOS transistor M4 have the same size.
In some embodiments, the sizes of the second NMOS transistor M2 and the fourth NMOS transistor M4 are multiple, for example, two times, the sizes of the first NMOS transistor M1 and the third NMOS transistor M3. Different gain adjustment can be realized through the selection of the sizes of the second NMOS transistor M2 and the fourth NMOS transistor M4 and the sizes of the first NMOS transistor M1 and the third NMOS transistor M3.
In some embodiments, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are controlled by the first control terminal Vc1, the second control terminal Vc2, the third control terminal Vc3, and the fourth control terminal Vc4, respectively; when the control end is at low level, for example 0V, the corresponding NMOS tube is disconnected; when the control terminal is at a high level, for example, 1V, the corresponding NMOS transistor is turned on.
In some embodiments, the first control terminal Vc1 is connected to the third control terminal Vc3, the second control terminal Vc2 is connected to the fourth control terminal Vc4, and the first control terminal Vc1 is controlled by a 2-bit digital signal, and the first control terminal Vc4 has a low level state and a high level state, and respectively controls the first NMOS transistor M1, the third NMOS transistor M3, the second NMOS transistor M2, and the fourth NMOS transistor M4, wherein the first NMOS transistor M1 and the third NMOS transistor M3 have the same states, and the second NMOS transistor M2 and the fourth NMOS transistor M4 have the same states.
In some embodiments, the gate of the first NMOS transistor M1 is connected to the first control terminal Vc1, the gate of the second NMOS transistor M2 is connected to the second control terminal Vc2, the gate of the third NMOS transistor M3 is connected to the third control terminal Vc3, and the gate of the fourth NMOS transistor M4 is connected to the fourth control terminal Vc 4.
In some embodiments, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 all use transistor parasitic optimization technology, and the gate is respectively connected in series with the high-ohmic first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 to improve isolation, so as to reduce the influence of parasitic capacitance between the gate and the source, and parasitic capacitance between the gate and the drain; the substrate is grounded through a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8 which are connected in series with high-ohmic resistors respectively and used for body end suspension, so that the influence of parasitic capacitance of the substrate is reduced, the insertion loss is reduced, the linearity is improved, and in order to further improve the isolation degree, the resistance values of all the body suspension resistors are required to be large enough. The gate of the first NMOS transistor M1 is connected to one end of a first resistor R1, and the other end of the first resistor R1 is connected to a first control terminal Vc 1; the gate of the second NMOS transistor M2 is connected to one end of a second resistor R2, and the other end of the second resistor R2 is connected to a second control terminal Vc 2; the gate of the third NMOS transistor M3 is connected to one end of a third resistor R3, and the other end of the third resistor R3 is connected to a third control terminal Vc 3; the gate of the fourth NMOS transistor M4 is connected to one end of a fourth resistor R4, and the other end of the fourth resistor R4 is connected to a fourth control terminal Vc 4. The body end of the first NMOS transistor M1 is connected with one end of a fifth resistor R5, and the other end of the fifth resistor R5 is grounded; the body end of the second NMOS transistor M2 is connected with one end of a sixth resistor R6, and the other end of the sixth resistor R6 is grounded; the body end of the third NMOS transistor M3 is connected with one end of a seventh resistor R7, and the other end of the seventh resistor R7 is grounded; the body end of the fourth NMOS transistor M4 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is grounded.
In some embodiments, the resistors R1-R8 are all 10K ohms.
According to the embodiment of the disclosure, the following technical effects are achieved:
(1)2 bits are adjustable, four equilibrium modes are provided, and different use requirements can be met;
(2) by adopting the CMOS process, the method has the advantages of low loss, low cost, easy integration and the like;
(3) by adopting a transistor parasitic optimization technology and a deep N-well process body suspension technology, the influence of parasitic capacitance and substrate noise of a transistor is reduced, the insertion loss is reduced, and the linearity is improved.
Those skilled in the art will appreciate that the embodiments described in this specification are exemplary and that no acts or modules are necessarily required by the disclosure. While several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (7)
1. An adjustable gain equalizer, comprising:
a first radio frequency port RF _ IN, a second radio frequency port RF _ OUT, a first resonant element, a second resonant element, a third transmission line TL 3; wherein the content of the first and second substances,
the first resonant unit comprises a first NMOS transistor M1, a second NMOS transistor M2 and a first transmission line TL1,
the first NMOS tube M1 and the second NMOS tube M2 are connected IN parallel, the drain electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2 are connected with the first radio frequency port RF _ IN and one end of a third transmission line TL3, and the source electrode of the first NMOS tube M1 and the source electrode of the second NMOS tube M2 are connected with one end of a first transmission line TL 1; the other end of the first transmission line TL1 is suspended;
the second resonant unit comprises a third NMOS transistor M3, a fourth NMOS transistor M4 and a second transmission line TL2,
the third NMOS transistor M3 is connected in parallel with the fourth NMOS transistor M4, a drain of the third NMOS transistor M2 and a drain of the fourth NMOS transistor M4 are connected to the second RF port RF _ OUT and one end of the third transmission line TL3, and a source of the third NMOS transistor M3 and a source of the fourth NMOS transistor M4 are connected to one end of the second transmission line TL 2; the other end of the second transmission line TL2 is floating.
2. The adjustable gain equalizer of claim 1,
the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are deep N-well NMOS transistors.
3. The adjustable gain equalizer of claim 1,
the first transmission line TL1 and the second transmission line TL2 are quarter-wavelength long.
4. The adjustable gain equalizer of claim 1,
the first NMOS tube M1, the second NMOS tube M2, the third NMOS tube M3 and the fourth NMOS tube M4 adopt a transistor parasitic optimization technology, and control ends are connected with the grid electrodes through series resistors correspondingly; the substrates are grounded through series resistors, respectively.
5. The adjustable gain equalizer of claim 1,
the gates of the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are connected to the first control terminal Vc1, the second control terminal Vc2, the third control terminal Vc3, and the fourth control terminal Vc4, respectively.
6. The adjustable gain equalizer of claim 5,
the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3 and the fourth NMOS transistor M4 are disconnected, and the adjustable gain equalizer works in a first equalization mode;
the first NMOS transistor M1 and the third NMOS transistor M3 are disconnected, the second NMOS transistor M2 and the fourth NMOS transistor M4 are connected, and the adjustable gain equalizer works in a second equalization mode;
the first NMOS transistor M1 and the third NMOS transistor M3 are switched on, the second NMOS transistor M2 and the fourth NMOS transistor M4 are switched off, and the adjustable gain equalizer works in a third equalization mode;
the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3 and the fourth NMOS transistor M4 are turned on, and the adjustable gain equalizer works in a fourth equalization mode.
7. The adjustable gain equalizer of claim 5,
when the control end is at a low level, the corresponding NMOS tube is disconnected; when the control end is at high level, the corresponding NMOS tube is conducted.
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| CN202011195637.2A CN112311345B (en) | 2020-10-31 | 2020-10-31 | Adjustable gain equalizer |
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| CN202011195637.2A CN112311345B (en) | 2020-10-31 | 2020-10-31 | Adjustable gain equalizer |
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| CN110138353A (en) * | 2019-05-27 | 2019-08-16 | 肖泽 | 6~18GHz Wideband Equalizer circuit |
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2020
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5363069A (en) * | 1993-04-05 | 1994-11-08 | Itt Corporation | Electronically tunable gain equalizer |
| CN102185573A (en) * | 2011-03-11 | 2011-09-14 | 京信通信系统（中国）有限公司 | Circuit of electric-tuning gain equalizer |
| CN202696648U (en) * | 2012-07-13 | 2013-01-23 | 四川九洲电器集团有限责任公司 | Adjustable millimeter wave power equalizer |
| CN103929139A (en) * | 2014-04-22 | 2014-07-16 | 西安电子科技大学 | Transimpedance pre-amplifier of photo-receiver with high-precision automatic gain control |
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| CN110138353A (en) * | 2019-05-27 | 2019-08-16 | 肖泽 | 6~18GHz Wideband Equalizer circuit |
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