CN112310124B - Display panel, display device and preparation method of display panel - Google Patents
Display panel, display device and preparation method of display panel Download PDFInfo
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- CN112310124B CN112310124B CN202011170361.2A CN202011170361A CN112310124B CN 112310124 B CN112310124 B CN 112310124B CN 202011170361 A CN202011170361 A CN 202011170361A CN 112310124 B CN112310124 B CN 112310124B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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Abstract
The application provides a display panel, a display device and a preparation method of the display panel, wherein the display panel comprises a display area and a non-display area, the display area comprises a first metal layer, and the non-display area comprises: a substrate layer; the first grid electrode layer is arranged on the surface of one side of the substrate layer; an interlayer dielectric layer arranged on the surface of one side of the first grid layer far away from the substrate layer; the second metal layer is arranged on the surface of one side, far away from the substrate layer, of the interlayer dielectric layer, extends from the non-display area to the display area and is electrically connected with the first metal layer; and the second flat layer is arranged on the surface of one side of the second metal layer, which is far away from the substrate layer. According to the application, the first metal layer and the first flat layer in the prior art are etched, and the second metal layer and the second flat layer in the display area are extended to the non-display area, so that the risk of exposing the second metal layer caused by the etching step is reduced, and the stability of the display panel is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel, a display device and a preparation method of the display panel.
Background
Because of the advantages of light weight, self luminescence, wide viewing angle, wide color gamut, high contrast, light weight, low driving voltage, low energy consumption, fast response speed and the like, the Organic light emitting Diode display device (Organic LIGHT EMITTING DISPLAY, OLED), especially Active Matrix Organic LIGHT EMITTING Diode (AMOLED), has a wider application range, and becomes a main field of research and development in the display technical field.
With the development of AMOLED display technology, the requirements of terminal devices on the brightness uniformity of the display are improved, but due to the existence of the resistance voltage Drop effect (IR Drop), when the display panel works, the thin film field effect transistor will generate loop current, thereby generating the effect of the resistance voltage Drop, resulting in the reduction of the voltage on the power supply voltage, so that the display panel has poor brightness uniformity due to the fact that the brightness of the two ends, which are closer to the driving IC (INTEGRATED CIRCUIT ) and farther from the driving IC, of the display panel is different.
Currently, many AMOLED display panels adopt a general dual-layer metal trace (dual Source/Drain, dual SD) structure for improving the resistance voltage drop effect, that is, a structure in which a first metal layer (SD 1) and a second metal layer (SD 2) are connected, and this structure makes a non-display area of the display panel form a structure, which sequentially includes: the substrate 111, the insulating layer 112, the first gate layer (GATE METAL a1, get 1) 113, the interlayer dielectric layer (Inter-LAYER DIELECTRIC, ILD) 114, the first metal layer (SD 1) 115, the first flat layer (Planarization Layer a1, pln 1) 116, the second flat layer (Planarization Layer a2, pln 2) 117, and the cathode 118, as shown in fig. 1 and 2, since the first metal layer 115 is covered with the first flat layer 116, there is an ashing (Ash) etching step in the patterning process of the first flat layer 116, and an intermediate etching step (DRY ETCHING) in the patterning process of the second metal layer in the subsequent display area, the two etching steps may cause excessive etching at the first flat layer 116, possibly cause the first flat layer 116 to be exposed at the climbing of the first metal layer 115, resulting in the problem of shorting the first metal layer 116 and the cathode 117, and further cause the display panel to have a poor display.
Disclosure of Invention
The application provides a display panel, a display device and a display panel preparation method, which are used for solving the problem that a metal layer of a non-display area in the existing display panel is easy to expose.
In one aspect, the present application provides a display panel including a display region including a first metal layer and a non-display region surrounding the display region, the non-display region including:
A substrate layer;
the first grid electrode layer is arranged on the surface of one side of the substrate layer;
an interlayer dielectric layer arranged on the surface of one side of the first grid layer far away from the substrate layer;
The second metal layer is arranged on the surface of one side, far away from the substrate layer, of the interlayer dielectric layer, extends from the non-display area to the display area and is electrically connected with the first metal layer;
And the second flat layer is arranged on the surface of one side of the second metal layer, which is far away from the substrate layer.
In a possible implementation manner of the present application, the non-display area further includes a pixel defining layer, where the pixel defining layer is disposed on a surface of the second flat layer, which is far away from the substrate layer.
In one possible implementation of the present application, the substrate layer includes:
A first flexible layer;
the first buffer layer is arranged on the surface of one side of the first flexible layer;
The second flexible layer is arranged on the surface of one side, away from the first flexible layer, of the first buffer layer;
And the second buffer layer is arranged on the surface of the second flexible layer, which is far away from one side of the first flexible layer.
In one possible implementation of the present application, the non-display area further includes:
the first grid electrode is arranged on the surface of one side of the first insulating layer, far away from the substrate layer;
and the second insulating layer is arranged on the surface of one side, away from the flexible layer, of the first insulating layer.
In a possible implementation manner of the present application, the non-display area further includes a first via hole, the first via hole is disposed on the interlayer dielectric layer, and the second metal layer penetrates through the interlayer dielectric layer through the first via hole and extends to the surface of the first gate layer.
In one possible implementation of the present application, the surface and the side surface of the second metal layer form an inclination angle, and the surface of the second metal layer is a surface far away from the flexible layer.
In a possible implementation of the present application, the non-display area further includes a cathode, where the cathode is disposed on a surface of the pixel defining layer on a side away from the flexible layer.
In one possible implementation of the present application, the display area further includes: a first planarization layer and a substrate layer formed by extending the non-display region, an interlayer dielectric layer, a first gate layer, a second metal layer, and a second planarization layer;
the interlayer dielectric layer is arranged on the surface of one side of the substrate layer;
The first grid electrode layer is arranged on the surface of one side, far away from the substrate layer, of the interlayer dielectric layer;
The first metal layer is arranged on the surface of one side, far away from the substrate layer, of the first grid electrode layer;
The first flat layer is arranged on the surface of one side, far away from the substrate layer, of the first metal layer;
the second metal layer is arranged on the surface of one side, far away from the substrate layer, of the first flat layer;
the second flat layer is arranged on the surface of one side, far away from the substrate layer, of the second metal layer.
On the other hand, the application also provides a display device which comprises the display panel.
In another aspect, the present application also provides a method for preparing a display panel, the method comprising:
providing a substrate layer;
Preparing a first grid layer on the surface of one side of the substrate layer;
Preparing an interlayer dielectric layer on the surface of one side of the first grid electrode layer far away from the substrate layer;
preparing a second metal layer on the surface of one side of the interlayer dielectric layer far away from the substrate layer;
And preparing a second flat layer on the surface of the side, away from the substrate layer, of the second metal layer.
According to the application, the first metal layer and the first flat layer which extend from the display area to the non-display area are etched, and the second metal layer and the second flat layer of the display area are extended to the non-display area, so that the width loss of the second metal layer caused by the etching step of the second metal layer and the flat layer in the non-display area is reduced, the exposure risk of the metal layer of the non-display area is reduced, and the stability of the panel is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic view of a prior art display panel with exposed metal layer in the non-display area;
FIG. 2 is a schematic diagram of a structure of a non-display area of a prior art display panel;
Fig. 3 is a schematic structural diagram of a display area of a display panel according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a structure of a non-display area of a display panel according to an embodiment of the present application;
FIG. 5 is a schematic top view of a non-display area of a display panel according to an embodiment of the present application;
Fig. 6 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been described in detail so as not to obscure the description of the application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
The embodiment of the application provides a display panel, a display device and a preparation method of the display panel, and the detailed description is given below.
Referring to fig. 3, the present embodiment provides a display panel, which includes a display area 100 and a non-display area 200 surrounding the display area, wherein, as shown in fig. 3, the display area 100 includes: a substrate layer 1, a first gate layer 31, an interlayer dielectric layer 4, a first metal layer 51, a first planarization layer 61, a second metal layer 52, and a second planarization layer 62.
Wherein, in some embodiments, the substrate layer 1 comprises: a first flexible layer 11, a first barrier layer 12, a second flexible layer 13 and a second barrier layer 14.
The first barrier layer 12 is arranged on one side surface of the first flexible layer 11; the second flexible layer 13 is arranged on the surface of the first barrier layer 12 on the side away from the first flexible layer 11; a second barrier layer 14 is provided on the surface of the second flexible layer 13 on the side remote from the first flexible layer 11. The first flexible layer 11 and the second flexible layer 13 may be made of Polyimide (PI), or may be made of one or more materials selected from acryl, hexamethyldisiloxane, polyacrylate, polycarbonate, polystyrene, and the like. The first barrier layer 12 and the second barrier layer 14 are made of inorganic materials to block the invasion of external water and oxygen.
The interlayer dielectric layer 4 is arranged on the surface of one side of the substrate layer 1; the first gate layer 31 is disposed on a surface of the interlayer dielectric layer 4, which is far away from the substrate layer 1, and is used for manufacturing a gate of a TFT device switch, and the first gate layer may be a three-layer structure formed by three layers of Ti/Al/Ti materials, or a double-layer structure formed by two layers of Ti/Al materials.
The first metal layer 51 is disposed on a surface of the first gate layer 31, which is far from the substrate layer 1; the first metal layer 51 is used as a Data Line (Data Line), a Vdd Line (Vdd Line), an initialization (START VERTICAL, STV) signal Line, etc. of the display panel. The first planarization layer 61 is disposed on a surface of the first metal layer 51 on a side away from the substrate layer 1, and the first planarization layer 61 is used for planarizing the surface of the first metal layer 51.
The second metal layer 52 is disposed on the surface of the first flat layer 61 away from the substrate layer 1, the second metal layer 52 forms source/drain electrodes and data traces of the driving thin film transistor, the second metal layer 52 is connected with the first metal layer 51 through contact holes, and Vdd traces are made into a mesh structure, so that uniformity of the display panel is better. The second planarization layer 62 is disposed on a surface of the second metal layer 52 on a side away from the substrate layer 1, and the second planarization layer 62 is used for planarizing the surface of the second metal layer 52.
In the display area, the second metal layer 51 is electrically connected with the first metal layer 52 through the contact hole to form a double-layer wiring structure, after any one of the first metal layer 51 and the second metal layer 52 is broken, the other metal layer can still keep signal transmission, so that the risk of signal incapability of transmitting caused by long-term bending and breaking of the signal wiring is reduced, and the yield of the display panel is improved.
The display area 100 further includes a third metal layer 53 and a Pixel defining layer (Pixel DEFINE LAYER, PDL) 7, where the third metal layer is an anode metal layer, the second metal layer 52 and the third metal layer (anode metal layer) 53 are connected by a contact hole, and the second metal layer 52 is further connected with the first metal layer 51 by a contact hole.
The pixel defining layer 7 is disposed on a surface of the third metal layer 53 away from the substrate layer 1, and a support Pillar (PS) 9 is further disposed on the pixel defining layer 7, where the support pillar 9 is formed by patterning a reserved area of the pixel defining layer 7.
As shown in fig. 3 and 4, the non-display area 200 includes: the substrate layer 1, the first gate layer 31, the interlayer dielectric layer 4, the second metal layer 52, and the second planarization layer 62 are sequentially formed by extending the display region 100.
The first gate layer 31 is arranged on the surface of one side of the substrate layer 1; the interlayer dielectric layer 4 is arranged on the surface of the first gate layer 31, which is far away from the side of the substrate layer 1; the second metal layer 52 is disposed on a surface of the interlayer dielectric layer 4 away from the substrate layer 1 and is electrically connected to the first metal layer 51; the second flat layer 62 is disposed on a surface of the second metal layer 52 on a side away from the substrate layer 1.
The display panel provided in this embodiment etches away the first metal layer 51 and the first flat layer 61 that extend from the display area 100 to the non-display area 200, and extends the second metal layer 52 and the second flat layer 62 of the display area 100 to the non-display area 200, thereby reducing the width loss of the second metal layer 52 caused by the etching step of the second metal layer 52 and the second flat layer 61 in the non-display area 200, and thus reducing the risk of exposing the second metal layer 62 of the non-display area, and improving the stability of the display panel.
In some embodiments, the non-display area further comprises a cathode 8 and a pixel defining layer 7 formed by extending the display area, wherein the pixel defining layer 7 is disposed on a surface of the second flat layer on a side away from the substrate layer 1. The cathode 8 is formed by covering the second metal layer 52 with the second flat layer 62, followed by deposition of a cathode metal and patterning.
In some embodiments, the non-display region 200 further includes a combined insulating layer 2 formed by extension of the display region, the combined insulating layer 2 including: a first insulating layer 21 and a second insulating layer 22. The first insulating layer 21 is disposed on a surface of the substrate layer 1, and the first gate electrode 31 is disposed on a surface of the first insulating layer away from the substrate layer 1; the second insulating layer 22 is disposed on a surface of the first insulating layer on a side away from the flexible layer. The first insulating layer 21 and the second insulating layer 22 are both made of inorganic insulating materials. In the display area, the metal trace corresponding to the first metal layer is disposed in the second insulating layer 32.
As shown in fig. 5, in some embodiments, the non-display area 200 further includes a first via (CNT) 41, where the first via 41 is disposed on the interlayer dielectric layer 4, and the second metal layer 52 extends to the surface of the first gate layer 31 through the first via 41 penetrating the interlayer dielectric layer 4.
In some embodiments, the surface and the side surface of the second metal layer 52 form an inclination angle, and the surface of the second metal layer 52 is a surface far away from the substrate layer 1, and the inclination angle may be formed on the surface of the second metal layer 52 in the non-display area or on the surface of the second metal layer 52 in the display area, where the formation of the inclination angle is beneficial to increasing the coverage of the next film layer of the second metal layer 52, reducing the component disconnection problem or the impedance increase problem.
The embodiment of the application also provides a display device, which comprises the display panel. The display device in this embodiment may be: wearable equipment, mobile phones, tablet computers, televisions, displays, notebook computers, electronic books, electronic newspapers, digital photo frames, navigator and any other products or components with display functions. The wearable device comprises a smart bracelet, a smart watch, a VR (Virtual Reality) device and the like.
As shown in fig. 6, the embodiment of the application further provides a method for preparing a display panel, which includes:
Step S101, providing a substrate layer;
step S102, preparing a first grid layer on the surface of one side of the substrate layer;
step S103, preparing an interlayer dielectric layer on the surface of one side of the first grid layer far away from the substrate layer;
step S104, preparing a second metal layer on the surface of one side of the interlayer dielectric layer far away from the substrate layer;
Step S105, preparing a second flat layer on the surface of the second metal layer far from the side of the substrate layer.
In some embodiments, after the step S105, the method may further include:
a pixel defining layer is prepared on a surface of the second planar layer on a side remote from the first flexible layer.
According to the preparation method of the display panel, the existing first metal layer and the first flat layer in the non-display area are etched, the second metal layer is prepared on the interlayer dielectric layer in sequence, patterning treatment is carried out on the second metal layer, the second flat layer is plated, patterning treatment is carried out on the second flat layer, and therefore the etching step of patterning treatment of the metal layer and the flat layer in the non-display area is reduced, the width loss caused by etching of the metal layer in the non-display area in the etching step is reduced, the exposure risk of the metal layer in the non-display area is reduced, and the stability of the display panel is improved.
The display panel, the display device and the method for manufacturing the display panel provided by the embodiment of the application are described in detail, and specific examples are applied to illustrate the principle and the implementation of the application, and the description of the above examples is only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (7)
1. The utility model provides a display panel, its characterized in that, display panel includes display area and around the non-display area of display area, the display area includes first metal level, first metal level is the net face structure, the non-display area includes:
A substrate layer;
the first grid electrode layer is arranged on the surface of one side of the substrate layer;
an interlayer dielectric layer arranged on the surface of one side of the first grid layer far away from the substrate layer;
the second metal layer is arranged on the surface of one side, far away from the substrate layer, of the interlayer dielectric layer, is adjacent to the interlayer dielectric layer, extends from the non-display area to the display area and is electrically connected with the first grid electrode layer;
the second flat layer is arranged on the surface of one side, far away from the substrate layer, of the second metal layer;
The first through hole is arranged on the interlayer dielectric layer, and the second metal layer penetrates through the interlayer dielectric layer through the first through hole and extends to the surface of the first grid electrode layer;
Wherein the display area further comprises: a first planarization layer and a substrate layer formed by extending the non-display region, an interlayer dielectric layer, a first gate layer, a second metal layer, and a second planarization layer;
The first grid layer is arranged on the surface of one side of the substrate layer;
the interlayer dielectric layer is arranged on the surface of one side, far away from the substrate layer, of the first grid layer;
The first metal layer is arranged on the surface of one side, far away from the substrate layer, of the interlayer dielectric layer;
The first flat layer is arranged on the surface of one side, far away from the substrate layer, of the first metal layer;
the second metal layer is arranged on the surface of one side, far away from the substrate layer, of the first flat layer;
the second flat layer is arranged on the surface of one side, far away from the substrate layer, of the second metal layer.
2. The display panel of claim 1, wherein the non-display region further comprises a pixel definition layer disposed on a surface of the second planar layer on a side away from the substrate layer.
3. The display panel of claim 1, wherein the substrate layer comprises:
A first flexible layer;
the first buffer layer is arranged on the surface of one side of the first flexible layer;
The second flexible layer is arranged on the surface of one side, away from the first flexible layer, of the first buffer layer;
And the second buffer layer is arranged on the surface of the second flexible layer, which is far away from one side of the first flexible layer.
4. The display panel of claim 1, wherein the non-display area further comprises:
the first grid electrode is arranged on the surface of one side of the first insulating layer, far away from the substrate layer;
The second insulating layer is arranged on the surface of one side, far away from the substrate layer, of the first insulating layer.
5. The display panel of claim 1, wherein the second metal layer surface and the side surface form an oblique angle, and the second metal layer surface is a surface of the second metal layer away from the substrate layer.
6. The display panel of claim 2, wherein the non-display region further comprises a cathode disposed on a surface of the pixel defining layer on a side away from the substrate layer.
7. A display device comprising the display panel according to any one of claims 1-6.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105807523A (en) * | 2016-05-27 | 2016-07-27 | 厦门天马微电子有限公司 | Array substrate, display panel comprising same and display device |
| CN106483726A (en) * | 2016-12-21 | 2017-03-08 | 昆山龙腾光电有限公司 | Thin-film transistor array base-plate and preparation method and display panels |
| CN109491121A (en) * | 2018-12-24 | 2019-03-19 | 上海中航光电子有限公司 | Display panel and display device |
| CN109920800A (en) * | 2019-02-28 | 2019-06-21 | 武汉华星光电半导体显示技术有限公司 | A kind of display device and preparation method thereof |
| CN111446266A (en) * | 2020-05-12 | 2020-07-24 | 武汉华星光电技术有限公司 | Display panel and preparation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101967905B1 (en) * | 2012-07-24 | 2019-04-11 | 삼성디스플레이 주식회사 | Display Apparatus |
-
2020
- 2020-10-28 CN CN202011170361.2A patent/CN112310124B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105807523A (en) * | 2016-05-27 | 2016-07-27 | 厦门天马微电子有限公司 | Array substrate, display panel comprising same and display device |
| CN106483726A (en) * | 2016-12-21 | 2017-03-08 | 昆山龙腾光电有限公司 | Thin-film transistor array base-plate and preparation method and display panels |
| CN109491121A (en) * | 2018-12-24 | 2019-03-19 | 上海中航光电子有限公司 | Display panel and display device |
| CN109920800A (en) * | 2019-02-28 | 2019-06-21 | 武汉华星光电半导体显示技术有限公司 | A kind of display device and preparation method thereof |
| CN111446266A (en) * | 2020-05-12 | 2020-07-24 | 武汉华星光电技术有限公司 | Display panel and preparation method thereof |
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