CN112309879A - Embedded RDL packaging forming method - Google Patents
Embedded RDL packaging forming method Download PDFInfo
- Publication number
- CN112309879A CN112309879A CN202011203967.1A CN202011203967A CN112309879A CN 112309879 A CN112309879 A CN 112309879A CN 202011203967 A CN202011203967 A CN 202011203967A CN 112309879 A CN112309879 A CN 112309879A
- Authority
- CN
- China
- Prior art keywords
- rdl
- layer
- opening
- passivation layer
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02311—Additive methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02317—Manufacturing methods of the redistribution layers by local deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02373—Layout of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
Abstract
The invention belongs to the technical field of RDL rewiring, and discloses a pre-embedded type RDL packaging forming method, which comprises the following steps: providing a wafer, wherein the upper surface of the wafer is provided with electrodes of semiconductor chips; coating the upper surface of the wafer twice to form a first PI passivation layer, wherein the first PI passivation layer is provided with a stepped opening for exposing the electrode, and a miniature RDL layer which is not in contact with the upper surface of the wafer is pre-buried on one side of the stepped opening; arranging a standard RDL layer on the upper surface of the first PI passivation layer, wherein the standard RDL layer is filled in the stepped opening and is in contact with the electrode on the upper surface of the wafer; forming a second PI passivation layer, wherein the second PI passivation layer covers the standard RDL layer and the first PI passivation layer, and a pit exposing a part of the standard RDL layer is formed in the second PI passivation layer; growing a bump in the pit to complete packaging; in conclusion, based on the method, the current amount which can be passed by the whole packaging structure can be effectively increased or the thickness of the whole packaging structure can be reduced.
Description
Technical Field
The invention belongs to the technical field of RDL rewiring, and particularly relates to a pre-embedded type RDL packaging forming method.
Background
With the development of wafer level packaging (WLCSP) and fan-out packaging in electronic products, the RDL rewiring technology is becoming widely used.
When meeting the requirement of large current, the RDL rewiring generally needs two layers of PI passivation layers according to the existing design rule; wherein: the first PI passivation layer mainly has a buffering function so as to improve the compatibility of the package; the second PI passivation layer mainly plays a role in protecting rewiring and plays a certain role in bump buffering.
However, according to the current PI properties, design rules and product thickness requirements, after the design of the first PI passivation layer and the RDL layer is completed, the designable thickness reserved to the second PI passivation layer is not more than 10um, so that the actual thickness of the second PI passivation layer is mostly less than 10 um. Under the condition, the second layer of PI passivation layer is easy to cause the phenomenon that the RDL layer cannot be completely covered, so that the oxidation of copper is caused, and the reliability of packaging and products is influenced.
Disclosure of Invention
The invention aims to provide a pre-buried RDL packaging forming method to solve the existing problems.
In order to achieve the purpose, the invention provides the following technical scheme: a pre-buried RDL packaging forming method comprises the following steps:
s1, providing a wafer, wherein the upper surface of the wafer is provided with an electrode of a semiconductor chip;
s2, coating twice to form a first PI passivation layer on the upper surface of the wafer in a covering mode, wherein the first PI passivation layer is provided with a stepped opening exposing the electrode, and a miniature RDL layer which is not in contact with the upper surface of the wafer is pre-buried on one side of the stepped opening;
s3, arranging a standard RDL layer on the upper surface of the first PI passivation layer, wherein the standard RDL layer is filled in the stepped opening and is in contact with the electrode on the upper surface of the wafer;
s4, forming a second PI passivation layer, wherein the second PI passivation layer covers the standard RDL layer and the first PI passivation layer; a pit on the second PI passivation layer exposing a portion of the standard RDL layer;
and S5, growing a convex block in the concave pit to finish packaging.
Preferably, in the two coating of step S2:
s21, first coating: coating and curing the upper surface of the wafer to form a first film layer of 3um, wherein the first film layer is provided with a first opening;
s22, coating for the second time: coating and curing the upper surface of the first film layer to form a second film layer of 6-20um, wherein the second film layer is provided with a second opening;
the first opening size is smaller than the second opening size, and the first opening and the second opening are stacked to form a stepped opening.
Preferably, the second opening edge is expanded by 5um more than the first opening edge.
Preferably, in the miniature RDL layer, one side edge far away from the stepped opening is taken as a positioning edge, and the positioning edge of the miniature RDL layer is retracted by 2um compared with the corresponding edge of the standard RDL layer.
Preferably, in the step S3, a distance between an upper surface of the standard RDL layer and an upper surface of the first PI passivation layer is not more than 10 um.
Preferably, in each of the steps S2 and S3, the setting of the miniature RDL layer and the standard RDL layer includes:
gluing: coating photoresist at the specified setting position of the RDL;
photoetching: exposing the photoresist by adopting a photoetching technology, and developing to form a residual photoresist pattern;
etching: etching and modifying the residual photoresist pattern by adopting an etching process to obtain a photoresist substrate pattern;
electroplating: and electroplating metal on the photoresist substrate pattern, and removing the photoresist substrate pattern.
Preferably, the metal is plated using electrochemical plating.
Preferably, the metals electroplated in the miniature RDL layer and the standard RDL layer are both copper.
Preferably, the photoresist substrate pattern is removed by a wet process.
Compared with the prior art, the invention has the following beneficial effects:
(1) in the invention, the thickness of the whole RDL is effectively increased through the matching between the standard RDL layer and the pre-embedded miniature RDL layer, so that the current amount which can be passed by the whole packaging structure is effectively increased, and the actual product requirements are met.
(2) In the invention, the thickness of the standard RDL layer is reduced through the design of the pre-buried miniature RDL layer, so that the second PI passivation layer can effectively cover the whole RDL under the condition of not increasing the thickness; and the thickness of the whole packaging structure and the product can be effectively reduced.
Drawings
FIG. 1 is a flow chart of a method provided by the present invention;
FIG. 2 is a schematic view of a wafer structure provided when the method of the present invention is performed;
FIG. 3 is a schematic structural diagram of a cured first film layer during the method of the present invention;
FIG. 4 is a schematic structural diagram of a second film layer after curing when the method of the present invention is performed;
FIG. 5 is a schematic diagram of a standard RDL layer after forming when the method provided by the present invention is performed;
FIG. 6 is a schematic structural diagram of a second PI passivation layer after forming when the method of the present invention is performed;
FIG. 7 is a schematic diagram illustrating a bump after growth is completed when the method of the present invention is performed;
fig. 8 is a schematic diagram of an RDL package structure formed in the prior art.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a pre-buried RDL packaging forming method, which is shown in a combined figure 1 and specifically comprises the following steps:
s1, providing a wafer 1, wherein the upper surface of the wafer 1 is provided with an electrode of a semiconductor chip;
s2, coating twice to cover the upper surface of the wafer 1 to form a first PI passivation layer 2, wherein the first PI passivation layer 2 is provided with a stepped opening 3 for exposing an electrode, and a miniature RDL layer 4 which is not in contact with the upper surface of the wafer 1 is embedded in one side of the stepped opening 3;
s3, arranging a standard RDL layer 5 on the upper surface of the first PI passivation layer 2, wherein the standard RDL layer 5 is filled in the stepped opening 3 and is in contact with the electrode on the upper surface of the wafer 1;
s4, forming a second PI passivation layer 6, wherein the second PI passivation layer 6 covers the standard RDL layer 5 and the first PI passivation layer 2; a pit 7 on the second PI passivation layer 6 exposing a portion of the standard RDL layer 5;
s5, growing the convex block 8 in the pit 7 to finish packaging.
Above, in the two-pass coating of step S2:
s21, first coating: coating and curing the upper surface of the wafer 1 to form a first film layer 21 of 3um, wherein the first film layer 21 is provided with a first opening 31;
s22, coating for the second time: coating and curing the upper surface of the first film layer 21 to form a second film layer 22 of 6-20um, wherein the second film layer 22 is provided with a second opening 32;
the first opening 31 is smaller than the second opening 32, and the first opening 31 and the second opening 32 are stacked to form the stepped opening 3.
In the above, the setting of the mini RDL layer 4 and the standard RDL layer 5 in steps S2 and S3 includes:
gluing: coating photoresist at the specified setting position of the RDL;
photoetching: exposing the photoresist by adopting a photoetching technology, and developing to form a residual photoresist pattern;
etching: etching and modifying the residual photoresist pattern by adopting an etching process to obtain a photoresist substrate pattern;
electroplating: and electroplating copper on the photoresist substrate pattern by adopting an electrochemical plating method, and removing the photoresist substrate pattern by adopting a wet process.
In view of the above disclosed method, the following embodiments are provided herein:
example 1
S1, as shown in a figure 2, providing a wafer 1, wherein the upper surface of the wafer 1 is provided with an electrode of a semiconductor chip;
s2, as shown in figure 3, coating for the first time: coating and curing the upper surface of the wafer 1 to form a first film layer 21 of 3um, wherein the first film layer 21 is provided with a first opening 31;
s3, as shown in figure 4, coating for the second time: coating and curing the upper surface of the first film layer 21 to form a second film layer 22 of 7um, wherein the second film layer 22 is provided with a second opening 32;
the first film layer 21 and the second film layer 22 are stacked to form the first PI passivation layer 2; the edge of the second opening 32 is expanded by 5um than the edge of the first opening 31, and the first opening 31 and the second opening 32 are stacked to form a stepped opening 3; embedding a miniature RDL layer 4 with the thickness of 7um at one side of the second opening 32, specifically in FIG. 4, the miniature RDL layer 4 is arranged at the right side of the second opening 32;
s4, as shown in FIG. 5, an 8um standard RDL layer 5 is arranged on the upper surface of the second film layer 22, and the standard RDL layer 5 is filled in the stepped opening 3 and is in contact with the electrode on the upper surface of the wafer 1; specifically, the right edge of the standard RDL layer 5 is extended by 2um compared with the right edge of the scaled RDL layer 4;
s5, as shown in FIG. 6, forming a 12um second PI passivation layer 6, wherein the second PI passivation layer 6 covers the standard RDL layer 5 and the first PI passivation layer 2; a pit 7 on the second PI passivation layer 6 exposing a portion of the standard RDL layer 5;
s5, as shown in figure 7, growing a convex block 8 in the concave pit 7 to finish packaging.
As can be seen from the above, the thickness from the upper surface of the wafer 1 to the upper surface of the second PI passivation layer 6 in the overall package structure formed in this embodiment is 30 um; wherein: the thickness of the first PI passivation layer 2 is 10 um; the overall thickness of the miniature RDL layer 4 and the standard RDL layer 5 is 15 um; the second PI passivation layer 6 is 12um thick.
Example 2
S1, as shown in a figure 2, providing a wafer 1, wherein the upper surface of the wafer 1 is provided with an electrode of a semiconductor chip;
s2, as shown in figure 3, coating for the first time: coating and curing the upper surface of the wafer 1 to form a first film layer 21 of 3um, wherein the first film layer 21 is provided with a first opening 31;
s3, as shown in figure 4, coating for the second time: coating and curing the upper surface of the first film layer 21 to form a second film layer 22 of 7um, wherein the second film layer 22 is provided with a second opening 32;
the first film layer 21 and the second film layer 22 are stacked to form the first PI passivation layer 2; the edge of the second opening 32 is expanded by 5um than the edge of the first opening 31, and the first opening 31 and the second opening 32 are stacked to form a stepped opening 3; embedding a miniature RDL layer 4 with the thickness of 5um at one side of the second opening 32;
s4, as shown in FIG. 5, a 5um standard RDL layer 5 is arranged on the upper surface of the second film layer 22, and the standard RDL layer 5 is filled in the stepped opening 3 and is in contact with the electrode on the upper surface of the wafer 1;
s5, as shown in FIG. 6, forming a second PI passivation layer 6 of 8um, wherein the second PI passivation layer 6 covers the standard RDL layer 5 and the first PI passivation layer 2; a pit 7 on the second PI passivation layer 6 exposing a portion of the standard RDL layer 5;
s5, as shown in figure 7, growing a convex block 8 in the concave pit 7 to finish packaging.
As can be seen from the above, the thickness from the upper surface of the wafer 1 to the upper surface of the second PI passivation layer 6 in the overall package structure formed in this embodiment is 23 um; wherein: the thickness of the first PI passivation layer 2 is 10 um; the overall thickness of the miniature RDL layer 4 and the standard RDL layer 5 is 10 um; the second PI passivation layer 6 is 8um thick.
Specifically, the structures shown in fig. 1 to 7 do not relate to the dimensions exemplified in the above-described embodiments 1 and 2, and fig. 1 to 7 are all used as structural references.
Comparative examples of the prior art
S1, providing a wafer a, wherein the upper surface of the wafer a is provided with an electrode of a semiconductor chip;
s2, coating and curing the upper surface of the wafer a once to form a first PI passivation layer b of 10 um;
s3, arranging a 10um RDL layer c on the upper surface of the first PI passivation layer b;
s4, setting a second PI passivation layer d of 10um, and covering the first PI passivation layer b and the RDL layer c;
and S5, growing a bump e on the second PI passivation layer d.
In summary, the package structure shown in fig. 8 is formed, and the thickness from the upper surface of the wafer a to the upper surface of the second PI passivation layer d in the overall package structure of the present embodiment is 30 um; wherein: the thickness of the first PI passivation layer b is 10 um; the thickness of the RDL layer c is 10 um; the thickness of the second PI passivation layer d is 10 um.
Comparing the above embodiment 1 with the comparative embodiment of the prior art, it can be seen that, in the case of manufacturing the packaged chip with the same thickness, the overall thickness of the overall miniature RDL layer 4 and the standard RDL layer 5 provided in the embodiment 1 is higher than that of the RDL layer c, and therefore, the method provided by the present invention can effectively increase the thickness of the overall RDL, thereby effectively increasing the amount of current that can be passed by the overall package structure, so as to meet the actual product requirements.
Comparing the above example 2 with the comparative example of the prior art, it can be seen that the thickness of the whole package structure in the example 2 is smaller than that of the comparative example of the prior art under the condition of preparing the RDL with the same thickness, and thus, the method provided by the present invention can effectively reduce the thickness of the whole package structure and the product thickness on the premise of ensuring the product performance.
In addition, in both of the above embodiments 1 and 2, the second PI passivation layer 6 can be ensured to completely cover the standard RDL layer 5, thereby ensuring the reliability of the entire package structure.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (9)
1. A pre-buried RDL packaging forming method is characterized by comprising the following steps:
s1, providing a wafer, wherein the upper surface of the wafer is provided with an electrode of a semiconductor chip;
s2, coating twice to form a first PI passivation layer on the upper surface of the wafer in a covering mode, wherein the first PI passivation layer is provided with a stepped opening exposing the electrode, and a miniature RDL layer which is not in contact with the upper surface of the wafer is pre-buried on one side of the stepped opening;
s3, arranging a standard RDL layer on the upper surface of the first PI passivation layer, wherein the standard RDL layer is filled in the stepped opening and is in contact with the electrode on the upper surface of the wafer;
s4, forming a second PI passivation layer, wherein the second PI passivation layer covers the standard RDL layer and the first PI passivation layer; a pit on the second PI passivation layer exposing a portion of the standard RDL layer;
and S5, growing a convex block in the concave pit to finish packaging.
2. The RDL on-board forming method of claim 1, wherein in the two-pass coating of step S2:
s21, first coating: coating and curing the upper surface of the wafer to form a first film layer of 3um, wherein the first film layer is provided with a first opening;
s22, coating for the second time: coating and curing the upper surface of the first film layer to form a second film layer of 6-20um, wherein the second film layer is provided with a second opening;
the first opening size is smaller than the second opening size, and the first opening and the second opening are stacked to form a stepped opening.
3. The method of claim 2, wherein the second opening edge is 5um wider than the first opening edge.
4. The method for forming the pre-buried RDL package according to claim 1, wherein: in the miniature RDL layer, one side edge far away from the stepped opening is used as a positioning edge, and the positioning edge of the miniature RDL layer is retracted by 2um compared with the corresponding edge of the standard RDL layer.
5. The pre-buried RDL package forming method according to claim 1, wherein in the step S3, a distance between an upper surface of the standard RDL layer and an upper surface of the first PI passivation layer is not more than 10 um.
6. The method according to claim 1, wherein in each of the steps S2 and S3, the setting of the miniature RDL layer and the standard RDL layer includes:
gluing: coating photoresist at the specified setting position of the RDL;
photoetching: exposing the photoresist by adopting a photoetching technology, and developing to form a residual photoresist pattern;
etching: etching and modifying the residual photoresist pattern by adopting an etching process to obtain a photoresist substrate pattern;
electroplating: and electroplating metal on the photoresist substrate pattern, and removing the photoresist substrate pattern.
7. The method for forming the pre-buried RDL package according to claim 6, wherein: electroplating metal by electrochemical plating.
8. The method for forming the pre-buried RDL package according to claim 7, wherein: the metals electroplated in the miniature RDL layer and the standard RDL layer are both copper.
9. The method for forming the pre-buried RDL package according to claim 6, wherein: and removing the photoresist substrate pattern by adopting a wet process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011203967.1A CN112309879A (en) | 2020-11-02 | 2020-11-02 | Embedded RDL packaging forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011203967.1A CN112309879A (en) | 2020-11-02 | 2020-11-02 | Embedded RDL packaging forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112309879A true CN112309879A (en) | 2021-02-02 |
Family
ID=74333638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011203967.1A Pending CN112309879A (en) | 2020-11-02 | 2020-11-02 | Embedded RDL packaging forming method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112309879A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101138084A (en) * | 2004-10-29 | 2008-03-05 | 弗利普芯片国际有限公司 | Semiconductor device package with bump overlying a polymer layer |
| KR20120054840A (en) * | 2010-11-22 | 2012-05-31 | 삼성전기주식회사 | Wafer level package and method for manufacturing the same |
| CN107452707A (en) * | 2016-05-30 | 2017-12-08 | 英飞凌科技股份有限公司 | The chip carrier and semiconductor devices of the redistribution structure improved containing heat, electrical property |
| CN110739287A (en) * | 2019-12-06 | 2020-01-31 | 山东傲天环保科技有限公司 | kinds of integrated chip package structure |
-
2020
- 2020-11-02 CN CN202011203967.1A patent/CN112309879A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101138084A (en) * | 2004-10-29 | 2008-03-05 | 弗利普芯片国际有限公司 | Semiconductor device package with bump overlying a polymer layer |
| KR20120054840A (en) * | 2010-11-22 | 2012-05-31 | 삼성전기주식회사 | Wafer level package and method for manufacturing the same |
| CN107452707A (en) * | 2016-05-30 | 2017-12-08 | 英飞凌科技股份有限公司 | The chip carrier and semiconductor devices of the redistribution structure improved containing heat, electrical property |
| CN110739287A (en) * | 2019-12-06 | 2020-01-31 | 山东傲天环保科技有限公司 | kinds of integrated chip package structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7969003B2 (en) | Bump structure having a reinforcement member | |
| US7847407B2 (en) | Semiconductor device with interface peeling preventing rewiring layer | |
| US7205660B2 (en) | Wafer level chip scale package having a gap and method for manufacturing the same | |
| JP5291485B2 (en) | Manufacturing method of semiconductor device | |
| US7906856B2 (en) | Semiconductor device and method for manufacturing semiconductor device | |
| US20140329385A1 (en) | Method for manufacturing semiconductor thick metal structure | |
| US10546826B2 (en) | Device containing and method of providing carbon covered copper layer | |
| KR102646248B1 (en) | Chip rewiring structure and manufacturing method thereof | |
| CN112309879A (en) | Embedded RDL packaging forming method | |
| CN111883433B (en) | Semiconductor chip package and method for forming the same | |
| CN105070698B (en) | Wafer scale scolding tin micro convex point and preparation method thereof | |
| TW201307184A (en) | Thin film structure for high density inductors and redistribution in wafer level packaging | |
| US20160240464A1 (en) | Hybrid circuit board and method for making the same, and semiconductor package structure | |
| US8476760B2 (en) | Electroplated posts with reduced topography and stress | |
| KR100401516B1 (en) | Method of fabricating package having runner metal | |
| US11791207B2 (en) | Unit specific variable or adaptive metal fill and system and method for the same | |
| CN113380650A (en) | Manufacturing method of metal bump and metal bump structure | |
| CN116364682A (en) | Semiconductor structure and preparation method thereof | |
| CN105097576A (en) | Method for manufacturing high-reliability wafer-level soldering micro bumps | |
| TWI339416B (en) | Method of forming conductive bumps with different diameters | |
| TW202329338A (en) | System and method for redistribution layer (rdl) repair | |
| KR20010048002A (en) | Method for manufacturing semiconductor device | |
| JPS6235646A (en) | Manufacture of semiconductor device | |
| JPH03132036A (en) | Manufacture of semiconductor device | |
| JPH05136142A (en) | Substrate for forming transfer bump plating |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210202 |
|
| RJ01 | Rejection of invention patent application after publication |