CN112305412B - DDR3 function test platform based on digital signal integrated circuit test system - Google Patents
DDR3 function test platform based on digital signal integrated circuit test system Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31704—Design for test; Design verification
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31721—Power aspects, e.g. power supplies for test circuits, power saving during test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention belongs to the field of digital integrated circuit testing, and particularly relates to a DDR3 function testing platform based on a digital signal integrated circuit testing system EVA100, which comprises an EVA100 testing machine, an FPGA central control board and a DDR3 chip to be tested, wherein the FPGA central control board comprises an FPGA minimum system, a power supply distribution network, an LED circuit, a DDR3 circuit and an EVA control interface circuit, and the FPGA minimum system comprises an FPGA chip, a clock circuit, a reset circuit and a configuration circuit; the FPGA chip comprises a signal synchronous processing module and a DDR3 measurement and control module, wherein the signal synchronous processing module realizes data receiving and transmitting with an EVA100 test machine through an EVA control interface circuit, synchronously analyzes data frames from the EVA100 test machine, selects a test operation mode according to analysis results, completes specified functional test operation through the DDR3 measurement and control module, and finally synchronously feeds back test results to the EVA100 test machine; the DDR3 measurement and control module realizes the control of the test flow and the functional test of the DDR3 chip to be tested.
Description
Technical Field
The invention belongs to the field of digital integrated circuit testing, and particularly relates to a DDR3 functional test platform based on a digital signal integrated circuit testing system EVA 100.
Background
DDR3 is a 3 rd generation high performance DDR SDRAM proposed to adapt to the development of computer technology, the data rate span of DDR3 is from 800Mbps to 1.6Gbps at present, while the DDR3 can keep lower power consumption while bringing faster performance experience to users, and the data rate is reduced by about 20% compared with the DDR2 of the previous generation. With the rapid development of the electronic information technology industry, the requirement on the running speed of hardware devices is higher and higher, and the use of DDR3 as a cache in design is more and more common, so that an efficient and low-cost DDR3 test scheme will be the focus of attention.
Due to the increase in speed, the test platform must provide a higher test frequency to verify the reliability of the DDR3 chip, as well as a more accurate means to make the measurement of the time parameter. Challenges faced by DDR3 testing include: higher test frequency, I/O dead zone problem, non-negligible signal jitter, etc., the AC/DC parameter and function test of DDR3 chip can be completed by means of large scale integrated test system and special test board card.
Currently, the DDR3 test in the prior art has the following disadvantages:
1. DDR3 has high working frequency, and a larger scale integrated test system, such as V93000HSM3G, T5503 with higher cost performance, is required to be relied on, and a special resource module is required to be adopted by a test machine to complete the test of DDR 3. Meanwhile, DDR3 has higher requirements on electromagnetic compatibility, the manufacturing of a test board becomes more difficult, and the whole test development cost is higher.
2. DDR3 has a large capacity, and test time at lower frequencies increases in multiples with capacity.
3. Neither the large-scale integrated test system J750 nor the digital signal integrated circuit test system EVA100 has direct test conditions of DDR3, and no effective DDR3 test scheme based on the EVA100 test system exists at present.
Disclosure of Invention
In order to solve the technical problems, the invention provides a DDR3 function test platform based on a digital signal integrated circuit test system EVA100, which comprises an EVA100 test machine, an FPGA central control board and a DDR3 chip to be tested, wherein the EVA100 test machine is communicated with the FPGA central control board, and the DDR3 chip to be tested is connected with the FPGA central control board;
the FPGA central control board comprises an FPGA minimum system, a power supply distribution network, an LED circuit, a DDR3 circuit and an EVA control interface circuit;
the EVA control interface circuit realizes the data interaction between the EVA100 test machine and the FPGA central control board;
the FPGA minimum system comprises an FPGA chip, a clock circuit, a reset circuit and a configuration circuit; the FPGA chip comprises a signal synchronous processing module and a DDR3 measurement and control module; the signal synchronous processing module realizes data receiving and transmitting with the EVA100 test machine through the EVA control interface circuit, synchronously analyzes the data frame from the EVA100 test machine, selects a test operation mode according to the analysis result, completes specified functional test operation through the DDR3 measurement and control module, and finally synchronously feeds back the test result to the EVA100 test machine; the DDR3 measurement and control module realizes the control of the test flow and the functional test of the DDR3 chip to be tested;
the DDR3 circuit provides peripheral circuits necessary for normal operation of the DDR3 chip to be tested, and simultaneously provides a transmission interface of the DDR3 chip to be tested and the FPGA chip;
the power supply distribution network supplies power for the FPGA central control panel and the DDR3 chip to be tested;
and the LED circuit displays the current test state in real time through the LEDs.
In the scheme, a clock circuit in the minimum FPGA system provides two paths of clock sources of 50MHz and 125MHz for an FPGA chip; the reset circuit provides stable and reliable reset pulse output for the FPGA chip, and adopts a MAX811 chip as a reset pulse output chip; the configuration circuit mainly adopts an AS configuration mode and adopts a JTAG boundary scan interface for program debugging and solidification programming.
In the above scheme, the test operation mode includes a write mode, a read mode, a self-charging write mode, a self-charging read mode, a refresh mode, a functional test mode, and a termination operation.
In the above scheme, the current test state displayed in real time by the LED includes a test operation mode and a test operation flag, wherein a test operation flag of 0 indicates stop operation, a test operation flag of 1 indicates failure and terminates operation, and a test operation flag blinks to indicate normal operation.
In the scheme, the power supply distribution network comprises a main distribution network and an EVA distribution network, wherein the main distribution network adopts a 5V power supply adapter to supply power, and the power supply network supplies power for the FPGA central control panel and the DDR3 chip to be tested through the LDO and the integrated power supply chip; the EVA power distribution network is characterized in that an EVA100 test machine supplies power to an FPGA central control panel and a DDR3 chip to be tested through controlling a power relay; in normal operation, only the main power distribution network or the EVA power distribution network supplies power, and the main power distribution network and the EVA power distribution network do not influence each other.
In the scheme, the EVA100 test machine comprises an EVA control module, the EVA control module is designed by adopting a program development environment matched with the EVA100 test machine, data interaction is carried out between the EVA control interface circuit and the FPGA central control board, and the EVA control module realizes control of the DDR3 test process by combining a circulation waiting mode with a conditional triggering jump function.
In the scheme, the FPGA chip adopts the Xilinx Spartan6FPGA chip XC6SLX75, the DDR3 measurement and control module comprises a DDR3 driving module, the full-coverage high-speed reading and writing function of the sector of the DDR3 chip to be measured is completed through the DDR3 driving module, meanwhile, the DDR3 driving module is configured to output a100 MHz FPGA system working clock and a 400MHz DDR3 working clock, and the DDR3 driving module adopts the Xilinx official IP core for design.
The invention has the beneficial effects that:
1. the non-special DDR3 test machine EVA100 is utilized, and the testing of the dynamic and static power supply current and the function of the DDR3 chip is solved in an indirect mode, so that the full-sector coverage function test of multiple modes and multiple data and the accurate test of the dynamic and static current are realized. The use of a larger-scale integrated test system is avoided, and the test cost is reduced.
2. The DDR3 IP core of the XLix FPGA is fully utilized to complete the logic control of DDR3, thereby meeting the requirement of the normal operation of DDR3 and being easy to realize the control of different working modes. And an independent DDR3 layout wiring layer is adopted, so that the stability of the whole test platform is further enhanced.
3. Because the DDR3 operation frequency is improved, the test time is reduced, the test efficiency is greatly improved, and the test cost is also reduced.
4. The test program is simple and convenient to operate, has a one-key test function, is convenient for a tester to carry out screening test, and can be used for a long time after solidification.
5. The test platform is small in size and has mobility, and the platform adopts two power-on modes of external power supply and EVA power supply, and when only a function test is needed, the external power supply mode is selected for one-key starting.
Drawings
FIG. 1 is a block diagram of the overall structure of a DDR3 functional test platform;
FIG. 2 is a hardware block diagram of a control board in an FPGA;
FIG. 3 is a software functional block diagram of the DDR3 functional test platform;
FIG. 4 is a flowchart of the EVA control software;
FIG. 5 is a flowchart of the DDR3 test software.
FIG. 6 is a diagram of DDR3 state machine operation process
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings.
The integral structure block diagram of the DDR3 function test platform based on the digital signal integrated circuit test system EVA100 is shown in figure 1, and the test platform mainly comprises an Aidewan EVA100 test machine, an FPGA central control board and a DDR3 chip to be tested. Because the system has low requirements on the trigger control signals, the EVA100 test machine adopts a direct connection mode to communicate with the FPGA central control board. The FPGA central control board adopts an Xilinx Spartan6FPGA chip XC6SLX75 to build DDR3 test platform hardware, and comprises a Spartan6FPGA minimum system, a power supply distribution network (Power Distributed Network, PDN for short), an LED circuit, a DDR3 circuit and an EVA control interface circuit. The automatic DDR3 testing software is designed based on the Spartan6FPGA and used for realizing automatic measurement and control of the DDR3 chip to be tested, and finally, the testing result is fed back to the EVA100 testing machine. And the DDR3 chip to be tested is connected with the FPGA central control board through a special DDR3 test fixture.
The hardware structure of the FPGA central control board is shown in fig. 2, and comprises a Spartan6FPGA minimum system, a PDN, an LED circuit, a DDR3 circuit and an EVA control interface circuit.
The Spartan6FPGA minimum system is a minimum basic unit which can maintain normal operation of the Spartan6 except a power supply, and comprises an FPGA chip, a clock circuit, a reset circuit and a configuration circuit.
The clock circuit provides necessary working clock sources for the FPGA. The clock circuit is respectively designed with two paths of clock sources of 50MHz and 125MHz, and mainly provides selectable reference clocks for design, thereby reducing hardware modification as much as possible.
The reset circuit provides stable and reliable reset pulse output for the FPGA, and adopts a MAX811 chip as a reset pulse output chip, and the chip outputs reset pulse of at least 140ms when reset is effective, so that the reset requirements of the FPGA and DDR3 can be met.
The configuration circuit mainly adopts an AS configuration mode, and adopts a HWD32P which is self-developed by a company AS an AS configuration chip. Meanwhile, the configuration circuit adopts a JTAG boundary scan interface for program debugging, solidification programming and the like.
In the FPGA central control board, the power supply requirements are shown in table 1. In view of the diversity of power supply requirements of the control boards in the FPGA, the PDN design mainly comprises a main power distribution network and an EVA power distribution network. The EVA100 test machine supplies power to the system through control of the power relay, provides a power interface for EVA control software, and can be used for testing static and dynamic current parameters. In normal operation, only a single power distribution network supplies power, and the two networks do not influence each other.
Table 1 FPGA central control panel power supply requirement meter
| Circuit module | Power supply demand |
| Spartan6FPGA minimum system | 0.75V、1.2V、1.5V、1.8V、3.3V |
| DDR3 circuit | 0.75V、1.5V、3.3V |
The LEDs mainly realize circuit indication and are used for software debugging, and the LEDs are connected in a common power supply mode to obtain higher driving capability.
The DDR3 circuit provides peripheral circuits necessary for normal operation of the DDR3 chip to be tested, and simultaneously provides a transmission interface of the DDR3 chip to be tested and the FPGA chip. In order to ensure the reliability of the DDR3 circuit, a MAX17510 chip is adopted to provide a reliable reference power supply for the DDR 3. To improve signal integrity, a 40 Ω termination resistance is used on the transmission line, while a 40 Ω dynamic termination matching resistance is also provided at the FPAG terminal. Since DDR3 is a high-speed chip, testing by an external backplane is not allowed.
The software design of the whole platform comprises two parts of EVA control software and DDR3 test software, the two parts are respectively operated in an Aide Wan EVA100 test machine and an FPGA central control board, and the software functional structure is shown in figure 3.
The EVA control software is a general test program designed based on an EVA100 test machine matched program development environment, program construction is carried out by adopting a GUI+test excitation mode, data interaction is carried out between an EVA control interface on an FPGA central control board and DDR3 test software, and finally, the DDR3 direct current parameter and the read-write function are tested and controlled. The DDR3 test software mainly controls the current test process of the DDR3 chip to be tested, and reports the test result to the EVA control software in real time through the EVA control interface, and the DDR3 test software mainly comprises a signal synchronous processing module and a DDR3 measurement and control module. The signal synchronous processing module realizes data receiving and transmitting with the EVA100 test machine, mainly completes analysis of data frames and synchronous feedback of test results, and the DDR3 measurement and control module realizes test flow control and functional test of the DDR3 chip to be tested, and simultaneously provides stable synchronous clock and reset for logic design.
EVA control software realizes the control of DDR3 test process by combining the condition triggering jump function in a cyclic waiting mode. In the independent test item, the setting of the content of the test item and the configuration of the test parameters are completed, and the output of the control signal is realized through the self-defined test excitation. The workflow of the EVA control software is shown in fig. 4. After the EVA100 test machine is used for powering up the DDR3 chip, a calibration feedback signal (see table 2) fed back by the control board in the FPGA needs to be detected, and after DDR3 test software finishes calibrating DDR3, the EVA control software simultaneously sends a configured test running mode (see table 2) and a starting signal to the DDR3 test software. In the test process, the software always monitors the test completion signal and makes a judgment, outputs a test result and sends a stop signal.
The DDR3 test software is mainly used for testing flow control and functional test of the DDR3 chip to be tested, and feeds back flow operation information to EVA control software running on an EVA100 test machine in real time, and mainly comprises a signal synchronization processing module and a DDR3 measurement and control module; the DDR3 measurement and control module comprises a DDR3 driving module, the DDR3 driving module is designed by adopting an Xilinx official IP core, and a stable synchronous 100MHz system working clock and a synchronous reset signal are provided for the FPGA.
The workflow of DDR3 test software is shown in FIG. 5. The DDR3 chip can be calibrated by two methods of power-up and soft reset. After the calibration is passed, the signal synchronization processing module is always in an on-line monitoring state until the EVA control software sends out a starting signal, the signal synchronization processing module synchronously analyzes a data frame from the EVA control software through the EVA control interface circuit, selects a test operation mode according to an analysis result, completes specified functional test operation through the DDR3 measurement and control module, and finally synchronously feeds back the test result to the EVA control software.
The current test state is displayed in real time through the LEDs, so that state identification is facilitated, and the definition of the output test state is shown in a table 3, wherein the data type and the flow type in the table 3 are the same as those in the table 2.
TABLE 2 DDR3 test related data definition
TABLE 3 LED status output display
The DDR3 measurement and control module completes the full-coverage high-speed read-write function of sectors of the DDR3 chip through the DDR3 driving module according to the test operation mode selected in the table 2, and simultaneously configures the DDR3 driving module to output an FPGA system working clock of 100MHz and a DDR3 working clock of 400 MHz. The design completed the DDR3 drive logic function using the state machine defined in Table 4, the state machine operation is shown in FIG. 6.
TABLE 4 State machine definition
| State definition | Meaning of |
| IDLE | Idle state |
| ACTIVE | Active state |
| WRITE | Write operation |
| WRITE_AP | Writing with auto-prechargeOperation of |
| READ | Read operation |
| READ_AP | Read operation with auto-precharge |
| FUN_TEST | Automatic full coverage functional test |
| REFRESH | Refresh operation |
The above embodiments are only preferred embodiments of the present invention, and are not intended to limit the present invention, but any modifications, equivalents, improvements, etc. within the principle of the idea of the present invention should be included in the scope of protection of the present invention.
Claims (8)
1. The DDR3 function test platform based on the digital signal integrated circuit test system EVA100 is characterized by comprising an EVA100 test machine, an FPGA central control board and a DDR3 chip to be tested, wherein the EVA100 test machine is communicated with the FPGA central control board, and the DDR3 chip to be tested is connected with the FPGA central control board;
the FPGA central control board comprises an FPGA minimum system, a power supply distribution network, an LED circuit, a DDR3 circuit and an EVA control interface circuit;
the EVA control interface circuit realizes the data interaction between the EVA100 test machine and the FPGA central control board;
the FPGA minimum system comprises an FPGA chip, a clock circuit, a reset circuit and a configuration circuit; the FPGA chip comprises a signal synchronous processing module and a DDR3 measurement and control module; the signal synchronous processing module realizes data receiving and transmitting with the EVA100 test machine through the EVA control interface circuit, synchronously analyzes the data frame from the EVA100 test machine, selects a test operation mode according to the analysis result, completes specified functional test operation through the DDR3 measurement and control module, and finally synchronously feeds back the test result to the EVA100 test machine; the DDR3 measurement and control module realizes the control of the test flow and the function test of the DDR3 chip to be tested, the DDR3 measurement and control module comprises a DDR3 driving module, the full-coverage high-speed read-write function of the sector of the DDR3 chip to be tested is completed through the DDR3 driving module, and simultaneously the DDR3 driving module is configured to output an FPGA system working clock of 100MHz and a DDR3 working clock of 400 MHz;
the DDR3 circuit provides peripheral circuits necessary for normal operation of the DDR3 chip to be tested, and simultaneously provides a transmission interface of the DDR3 chip to be tested and the FPGA chip;
the power supply distribution network supplies power for the FPGA central control panel and the DDR3 chip to be tested;
and the LED circuit displays the current test state in real time through the LEDs.
2. The DDR3 functional test platform of claim 1, wherein the clock circuit in the FPGA minimum system provides two clock sources of 50MHz and 125MHz for the FPGA chip; the reset circuit provides stable and reliable reset pulse output for the FPGA chip, and adopts a MAX811 chip as a reset pulse output chip; the configuration circuit mainly adopts an AS configuration mode and adopts a JTAG boundary scan interface for program debugging and solidification programming.
3. The DDR3 functional test platform of claim 1, wherein the test operational modes comprise a write mode, a read mode, an accompanying self-charging write mode, an accompanying self-charging read mode, a refresh mode, a functional test mode, a termination operation.
4. The DDR3 functional test platform of claim 1, wherein the current test status of the LED real-time display comprises a test run mode and a test run flag, the test run flag being 0 to indicate stop running, the test run flag being 1 to indicate failure and terminate running, the test run flag flashing to indicate normal running.
5. The DDR3 functional test platform of claim 1, wherein the power supply distribution network comprises a main distribution network and an EVA distribution network, wherein the main distribution network adopts a 5V power adapter to supply power, and supplies power to the FPGA central control panel and the DDR3 chip to be tested through a low dropout linear regulator LDO and an integrated power supply chip; the EVA power distribution network is characterized in that an EVA100 test machine supplies power to an FPGA central control panel and a DDR3 chip to be tested through controlling a power relay; in normal operation, only the main power distribution network or the EVA power distribution network supplies power, and the main power distribution network and the EVA power distribution network do not influence each other.
6. The DDR3 function test platform of claim 1, wherein the EVA100 test machine comprises an EVA control module, the EVA control module is designed by adopting a program development environment matched with the EVA100 test machine, and performs data interaction with an FPGA central control board through an EVA control interface circuit, and the EVA control module realizes control of the DDR3 test process by combining a cyclic waiting mode with a conditional trigger jump function.
7. The DDR3 functional test platform of claim 1, wherein the FPGA chip employs an Xilinx Spartan6FPGA chip XC6SLX75.
8. The DDR3 functional test platform of claim 7, wherein the DDR3 driver module is designed with an Xilinx official IP core.
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