CN112289738B - Method for forming metal interconnection structure - Google Patents
Method for forming metal interconnection structure Download PDFInfo
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- CN112289738B CN112289738B CN202011096734.6A CN202011096734A CN112289738B CN 112289738 B CN112289738 B CN 112289738B CN 202011096734 A CN202011096734 A CN 202011096734A CN 112289738 B CN112289738 B CN 112289738B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 132
- 239000002184 metal Substances 0.000 title claims abstract description 132
- 238000000034 method Methods 0.000 title claims abstract description 103
- 238000005530 etching Methods 0.000 claims abstract description 46
- 208000037909 invasive meningococcal disease Diseases 0.000 claims description 76
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000005034 decoration Methods 0.000 claims 1
- 238000000605 extraction Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 92
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
The application discloses a method for forming a metal interconnection structure, which comprises the following steps: etching the first IMD to form a first through hole, wherein a high-voltage device is formed under the first IMD; forming a first metal layer, carrying out planarization treatment on the first metal layer, removing the first metal layer in other areas outside the first through hole, and forming a first contact through hole by the first metal layer in the first through hole; forming a second IMD on the first IMD; etching the second IMD to form a second through hole; forming a second metal layer, carrying out planarization treatment on the second metal layer, removing the second metal layer in other areas outside the second through hole, and forming a second contact through hole by the second metal layer in the second through hole; when the sum of the thicknesses of the first IMD and the second IMD is greater than a target thickness, the second contact via is used to connect with an electrode formed in a subsequent process, and the target thickness is greater than 6 micrometers. The metal interconnection structure of the high-voltage device is formed through the same process superposition, and the extraction of the high-voltage device is realized on the basis of saving cost.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a method for forming a metal interconnection structure.
Background
In a back end of line (BEOL) process of semiconductor manufacturing, a trench for forming a contact via (via) is etched in an interlayer metal dielectric (inter metal dielectric, IMD), then filled with a metal, and then planarized to form a contact via for connection with an electrode formed in a subsequent process.
For High Voltage (HV) devices (applied to semiconductor devices in power environments where ac voltages are above 1000 volts (V), or dc voltages are above 1500V), it is desirable to form a thicker IMD (typically greater than 6 micrometers (μm)) to protect the devices underlying the IMD. However, the thickness of the IMD of the single layer is limited by the deposition time of the device and the consistency of the subsequent planarization process, and is generally maintained within 3 microns, and for this reason, the related art proposes to implement the extraction of the high voltage device in a layered growth superposition manner.
Referring to fig. 1, a schematic cross-sectional view of a metal interconnect structure of a high voltage device formed in the related art is shown. As shown in fig. 1, the metal interconnect structure includes a first IMD111, a first contact via 1110 formed in the first IMD111, a metal layer 120 formed on the first IMD111, a second IMD112 formed on the metal layer 120, and a second contact via 1120 formed in the second IMD 112. Wherein the bottom of the second contact via 1120 is connected to the top of the metal layer 120, and the top of the first contact via 1110 is connected to the bottom of the metal layer 120. The second contact via 1120 is used for forming electrode connection in the subsequent process, and the sum of the thicknesses of the first IMD111 and the second IMD112 is greater than the IMD thickness required by the high voltage device.
However, the metal interconnection structure of the high voltage device provided in the related art requires additional photolithography and deposition processes because a metal layer needs to be formed during the formation process, the formation process is complicated, and the manufacturing cost is high.
Disclosure of Invention
The application provides a method for forming a metal interconnection structure, which can solve the problem of high manufacturing cost caused by complex forming process in the method for forming the metal interconnection structure of a high-voltage device in the related technology.
In one aspect, an embodiment of the present application provides a method for forming a metal interconnection structure, where the method is applied to a back-end process of a high-voltage device, and the method includes:
etching the first IMD to form a first through hole, wherein the high-voltage device is formed under the first IMD;
forming a first metal layer, wherein the first metal layer fills the first through hole, flattening the first metal layer, removing the first metal layer in other areas outside the first through hole, and forming a first contact through hole by the first metal layer in the first through hole;
forming a second IMD on the first IMD;
etching the second IMD to form a second through hole, wherein a mask plate used for etching the second IMD is the same as a mask plate used for etching the first IMD;
forming a second metal layer, wherein the second metal layer fills the second through hole, flattening the second metal layer, removing the second metal layer in other areas outside the second through hole, forming a second contact through hole in the second metal layer, and connecting the bottom of the second contact through hole with the top of the first contact through hole;
and when the sum of the thicknesses of the first IMD and the second IMD is larger than a target thickness, the second contact through hole is used for being connected with an electrode formed in a subsequent process, and the target thickness is larger than 6 microns.
Optionally, the top of the first through hole comprises a first opening with a trapezoid cross section;
the etching the first IMD comprises the following steps:
covering photoresist on the first IMD in other areas except for a first target area through a photoetching process, wherein the first target area is an area corresponding to the first through hole;
performing isotropic etching to form the first opening in the first target area;
performing anisotropic etching, namely etching downwards from the first opening to a target depth;
and removing the photoresist.
Optionally, the etching the second IMD includes:
covering photoresist on other areas except a target area on the second IMD through a photoetching process, wherein the second target area is an area corresponding to the second through hole;
performing anisotropic etching until the first contact through hole is exposed;
and removing the photoresist.
Optionally, at least two first contact through holes are formed in the first IMD, the number of second contact through holes formed in the second IMD is the same as the number of first contact through holes formed in the first IMD, and one first contact through hole is connected below each second contact through hole.
Optionally, the forming a first metal layer includes:
an aluminum layer is deposited on the first IMD by a physical vapor immersion (physical vapor deposition, PVD) process to form the first metal layer.
Optionally, the forming the second metal layer includes:
and depositing an aluminum layer on the second IMD through a PVD process to form the second metal layer.
Optionally, the forming a first metal layer includes:
a tungsten layer is deposited on the first IMD by a chemical vapor deposition (chemical vapor deposition, CVD) process to form the first metal layer.
Optionally, the forming the second metal layer includes:
and depositing a tungsten layer on the second IMD through a CVD process to form the second metal layer.
Optionally, the forming a first metal layer includes:
and forming a copper layer on the first IMD through an electroplating process to form the first metal layer.
Optionally, the forming the second metal layer includes:
and forming a copper layer on the second IMD through an electroplating process to form the second metal layer.
Optionally, when the sum of the thicknesses of the first IMD and the second IMD is smaller than the target thickness, after the planarization process is performed on the second metal layer, the method further includes:
forming an iIMD on the second IMD, wherein i is a natural number, and i is more than or equal to 3;
etching the iIMD to form an i-th through hole, wherein a mask plate used for etching the iIMD is the same as a mask plate used for etching the first IMD;
forming an ith metal layer, filling the ith through hole by the ith metal layer, carrying out planarization treatment on the ith metal layer, and removing the ith metal layer in other areas outside the ith through hole, wherein the ith metal layer in the ith through hole forms an ith contact through hole;
when the sum of the thicknesses of the first IMD and the iIMD is smaller than the target thickness, the steps are repeated until the sum of the thicknesses of the formed IMDs is larger than the target thickness, an n-th contact through hole formed in the uppermost nIMD is used for being connected with an electrode formed in a subsequent process, n is a natural number, and n is larger than or equal to i.
Optionally, at least two first contact through holes are formed in the first IMD;
the number of the second contact through holes formed in the second IMD is the same as that of the first contact through holes formed in the first IMD, and one first contact through hole is connected below each second contact through hole;
the number of the ith contact through holes formed in the ith IMD is the same as that of the first contact through holes formed in the first IMD, and one ith-1 contact through hole is connected below each ith contact through hole.
The technical scheme of the application at least comprises the following advantages:
through in the back-end process of the high-voltage device, a first IMD, a first contact through hole in the first IMD, a second IMD and a second contact through hole in the second IMD are sequentially formed above the high-voltage device, the bottom of the second contact through hole is connected with the top of the first contact through hole, the sum of the thicknesses of the first IMD and the second IMD is the thickness of the IMD required by the high-voltage device, and as a metal layer is not required to be formed between the first IMD and the second IMD, the process adopted for forming each layer of IMD and the contact through hole is the same, and the mask plates are the same, so that the process is simpler, and the manufacturing cost of the high-voltage device is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a metal interconnect structure of a high voltage device formed in the related art;
FIG. 2 is a flowchart of a method of forming a metal interconnect structure provided in one exemplary embodiment of the present application;
fig. 3 to 13 are schematic views illustrating a process of forming a metal interconnection structure according to an exemplary embodiment of the present application;
fig. 14 is a flowchart of a method of forming a metal interconnect structure provided in an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
Referring to fig. 2, a flowchart of a method for forming a metal interconnection structure according to an exemplary embodiment of the present application is shown, where the method may be applied to a back-end process of a high-voltage device, and the method includes:
in step 201, the first IMD is etched to form a first via, and a high voltage device is formed under the first IMD.
Optionally, in the embodiment of the present application, step 201 includes, but is not limited to: covering the photoresist on other areas except the first target area on the first IMD through a photoetching process, wherein the first target area is an area corresponding to the first through hole; performing isotropic etching to form a first opening in a first target area; performing anisotropic etching, namely etching downwards from the first opening to a target depth; and removing the photoresist.
Referring to fig. 3, a schematic cross-sectional view of a photoresist overhanging a first IMD is shown; referring to fig. 4, a schematic cross-sectional view of a blanket photoresist is shown; referring to fig. 4, a schematic cross-sectional view of a first target area after exposure and development is shown; referring to fig. 5, a schematic cross-sectional view of isotropic etching of a first target region is shown; referring to fig. 6, a schematic cross-sectional view of anisotropically etching a first target area is shown.
As shown in fig. 3-6, a photoresist 301 is suspended over a first IMD311, optionally, the first IMD311 has a thickness of less than 3 microns; exposing and developing the first target area; isotropic etching is carried out on the first target area, and a first opening (shown by a dotted line in fig. 5) is formed by etching, wherein the cross section of the first opening is trapezoidal; an anisotropic etch is performed down from the first opening to a target depth, exposing structures (not shown in fig. 6) under the first IMD311, forming a first via 3011, wherein the direction of the anisotropic etch is vertically down (i.e., the direction of the film thickness).
The first opening is formed firstly through isotropic etching, and then the first through hole is formed through anisotropic etching downwards, and the width D1 of the first opening is larger than the width D2 of the through hole formed through anisotropic etching, so that the difficulty in alignment between the second contact through hole and the first contact through hole of the upper layer formed in the subsequent process can be reduced, and the manufacturing yield of the device is improved.
Step 202, forming a first metal layer, filling the first through hole with the first metal layer, performing planarization treatment on the first metal layer, removing the first metal layer in other areas outside the first through hole, and forming a first contact through hole by the first metal layer in the first through hole.
Referring to fig. 7, a schematic cross-sectional view of forming a first metal layer is shown. Alternatively, in the embodiment of the present application, the first metal layer 320 may be formed by any one of the following methods from method 1.1 to method 1.3:
method 1.1: depositing an aluminum layer on the first IMD311 by a PVD process to form a first metal layer 320, which fills the first via 3011; method 1.2: depositing a tungsten layer on the first IMD311 by a CVD process, forming a first metal layer 320, which fills the first via 3011; a copper layer is formed on the first IMD311 through an electroplating process, forming a first metal layer 320, which fills the first via 3011.
Referring to fig. 8, a schematic cross-sectional view of the first metal layer after planarization is shown. For example, the first metal layer 320 in other regions outside the first via 3011 may be removed by a chemical mechanical polishing (chemical mechanical polishing, CMP) process, so that the first IMD311 in other regions is exposed, and the remaining first metal layer 320 forms the first contact via 321.
In step 203, a second IMD is formed on the first IMD.
Referring to fig. 9, a schematic cross-sectional view of forming a second IMD on a first IMD is shown. Illustratively, as shown in fig. 9, a second IMD312 may be formed on the first IMD311 by a CVD process. Optionally, second IMD312 has a thickness of less than 3 microns.
And 204, etching the second IMD to form a second through hole, wherein the mask plate used for etching the second IMD is the same as the mask plate used for etching the first IMD.
Optionally, in an embodiment of the present application, step 204 includes, but is not limited to: covering the photoresist on other areas except the target area on the second IMD through a photoetching process, wherein the second target area is an area corresponding to the second through hole; performing anisotropic etching until the first contact through hole is exposed; and removing the photoresist.
Referring to fig. 10, a schematic cross-sectional view of a photoresist overlaid on a second IMD by a photolithographic process is shown; referring to fig. 11, a schematic cross-sectional view of etching to form a second via is shown.
As shown in fig. 10 and 11, a photoresist 301 may be suspended over a second IMD 312; exposing and developing a second target area, which is located above the first contact via 321; the second target region is etched until the first contact via 321 is exposed, forming a second via 3012, wherein the direction of the anisotropic etching is vertically downward (i.e., the direction of the film thickness).
And 205, forming a second metal layer, filling the second through hole with the second metal layer, carrying out planarization treatment on the second metal layer, removing the second metal layer in other areas outside the second through hole, forming a second contact through hole by the second metal layer in the second through hole, and connecting the bottom of the second contact through hole with the top of the first contact through hole.
Referring to fig. 12, a schematic cross-sectional view of forming a second metal layer is shown. Alternatively, in the embodiment of the present application, the forming methods of the first metal layer 320 and the second metal layer 330 are the same, that is:
if the first metal layer 320 is formed by depositing an aluminum layer on the first IMD311 by PVD process, then depositing an aluminum layer on the second IMD312 by PVD process to form a second metal layer 330 that fills the second via 3012; if first metal layer 320 is formed by depositing a tungsten layer on first IMD311 by a CVD process, then second metal layer 330 is formed by depositing a tungsten layer on second IMD312 by a CVD process, which fills second via 3012; if the first metal layer 320 is formed by forming a copper layer on the first IMD311 through an electroplating process, a copper layer is formed on the second IMD312 through an electroplating process, forming a second metal layer 330, which fills the second via 3012.
Referring to fig. 13, a schematic cross-sectional view of the second metal layer after planarization is shown. For example, the second metal layer 330 may be removed from other areas outside the second via 3012 by a CMP process, exposing the second IMD312 in other areas, and the remaining second metal layer 330 forms the second contact via 322.
When the sum of the thicknesses of the first IMD311 and the second IMD312 is greater than a target thickness, the second contact via 322 is formed for connection with an electrode formed in a subsequent process, the target thickness being greater than 6 μm.
In summary, in this embodiment of the present application, in a back-end process of a high-voltage device, a first IMD, a first contact via in the first IMD, a second IMD, and a second contact via in the second IMD are sequentially generated above the high-voltage device, the bottom of the second contact via is connected to the top of the first contact via, and the sum of thicknesses of the first IMD and the second IMD is the IMD thickness required by the high-voltage device.
In an alternative embodiment, at least two first contact vias 321 are formed in the first IMD311 (corresponding to the need to etch at least two first via 3011 in step 201), the number of second contact vias 322 formed in the second IMD312 is the same as the number of first contact vias 321 formed in the first IMD311 (corresponding to the need to etch at least two second via 3012, each second via 3012 being located above a corresponding first contact via 321), and one first contact via 321 is connected below each second contact via 322.
When the target thickness is greater, and the sum of the thicknesses of the first IMD311 and the second IMD312 does not reach the target thickness, it is necessary to continue forming the interconnect structure on the second IMD312. See the following examples:
referring to fig. 14, a flowchart illustrating a method for forming a metal interconnection structure according to an exemplary embodiment of the present application may be a method performed after step 205 of the embodiment of fig. 2, the method includes:
in step 1401, an iIMD is formed on the second IMD, i is a natural number, and i is not less than 3.
The method of forming the iiimd may refer to the method in step 203 in the above embodiment, and will not be described herein.
Step 1402, etching the iIMD to form an i-th through hole, wherein a mask used for etching the iIMD is the same as a mask used for etching the first IMD.
The method of etching the ith through hole may refer to the method in step 201 or step 204 in the above embodiment, and will not be described herein.
Step 1403, forming an ith metal layer, filling the ith through hole with the ith metal layer, performing planarization treatment on the ith metal layer, removing the ith metal layer in other areas outside the ith through hole, and forming an ith contact through hole in the ith metal layer in the ith through hole.
The method of forming the ith contact hole may refer to the methods in step 202 and step 205 in the above embodiments, and will not be described herein. The method of forming the first metal layer 320, the second metal layer 330, and the i-th metal layer is the same.
When the sum of the thicknesses of the first IMD and the iIMD is smaller than the target thickness, the steps are repeated until the sum of the thicknesses of the formed IMDs is larger than the target thickness, the n-th contact through hole formed in the uppermost nIMD is used for being connected with an electrode formed in a subsequent process, n is a natural number, and n is larger than or equal to i.
The method of forming the first metal layer 320 and the second metal layer 330 to the n-th metal layer is the same. Alternatively, in the present embodiment, the method of forming the first through-hole 3011, the second through-hole 3012 to the (n-1) th through-hole is the same as that in fig. 3 to 6, that is, the first through-hole 3011, the second through-hole 3012 to the (n-1) th through-hole all include openings; the method of forming the n-th via is the same as in fig. 10 and 11, i.e., the n-th via does not include an opening.
Optionally, in this embodiment, at least two first contact vias 321 are formed in the first IMD311 (correspondingly, in step 201, at least two first vias 3011 need to be etched to form them); the number of second contact holes 322 formed in the second IMD312 is the same as the number of first contact holes 321 formed in the first IMD311 (accordingly, in step 204, at least two second contact holes 3012 are required to be etched, each second contact hole 3012 is located above a corresponding first contact hole 321), and one first contact hole 321 is connected to the lower side of each second contact hole 322; the number of the ith contact through holes formed in the ith IMD is the same as the number of the first contact through holes 321 formed in the first IMD311 (accordingly, in step 1402, at least two ith contact through holes, each of which is located above a corresponding (i-1) th contact through hole, are required to be etched, and one (i-1) th contact through hole is connected to the lower side of each of the ith contact through holes.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (11)
1. A method for forming a metal interconnect structure, wherein the method is applied to a back-end process of a high-voltage device, the method comprising:
covering photoresist on other areas except a first target area on a first IMD (in-mold decoration) through a photoetching process, wherein the first target area is an area corresponding to a first through hole, and the high-voltage device is formed under the first IMD;
performing isotropic etching to form a first opening in the first target area, wherein the cross section of the first opening is trapezoidal;
performing anisotropic etching, namely etching downwards from the first opening to a target depth to form a first through hole, wherein the top of the first through hole is the first opening;
removing the photoresist;
forming a first metal layer, wherein the first metal layer fills the first through hole, flattening the first metal layer, removing the first metal layer in other areas outside the first through hole, and forming a first contact through hole by the first metal layer in the first through hole;
forming a second IMD on the first IMD;
etching the second IMD to form a second through hole, wherein a mask plate used for etching the second IMD is the same as a mask plate used for etching the first IMD;
forming a second metal layer, wherein the second metal layer fills the second through hole, flattening the second metal layer, removing the second metal layer in other areas outside the second through hole, forming a second contact through hole in the second metal layer, and connecting the bottom of the second contact through hole with the top of the first contact through hole;
and when the sum of the thicknesses of the first IMD and the second IMD is larger than a target thickness, the second contact through hole is used for being connected with an electrode formed in a subsequent process, and the target thickness is larger than 6 microns.
2. The method of claim 1, wherein the etching the second IMD comprises:
covering photoresist on the second IMD in other areas except for a second target area through a photoetching process, wherein the second target area is an area corresponding to the second through hole;
performing anisotropic etching until the first contact through hole is exposed;
and removing the photoresist.
3. The method according to claim 1 or 2, wherein at least two first contact vias are formed in the first IMD, the number of second contact vias formed in the second IMD is the same as the number of first contact vias formed in the first IMD, and one first contact via is connected below each of the second contact vias.
4. The method of claim 1 or 2, wherein forming the first metal layer comprises:
and depositing an aluminum layer on the first IMD through a PVD process to form the first metal layer.
5. The method of claim 4, wherein forming the second metal layer comprises:
and depositing an aluminum layer on the second IMD through a PVD process to form the second metal layer.
6. The method of claim 1 or 2, wherein forming the first metal layer comprises:
and depositing a tungsten layer on the first IMD through a CVD process to form the first metal layer.
7. The method of claim 6, wherein forming the second metal layer comprises:
and depositing a tungsten layer on the second IMD through a CVD process to form the second metal layer.
8. The method of claim 1 or 2, wherein forming the first metal layer comprises:
and forming a copper layer on the first IMD through an electroplating process to form the first metal layer.
9. The method of claim 8, wherein forming the second metal layer comprises:
and forming a copper layer on the second IMD through an electroplating process to form the second metal layer.
10. The method of claim 3, wherein when the sum of the thicknesses of the first IMD and the second IMD is less than a target thickness, the planarizing the second metal layer further comprises:
forming an iIMD on the second IMD, wherein i is a natural number, and i is more than or equal to 3;
etching the iIMD to form an i-th through hole, wherein a mask plate used for etching the iIMD is the same as a mask plate used for etching the first IMD;
forming an ith metal layer, filling the ith through hole by the ith metal layer, carrying out planarization treatment on the ith metal layer, and removing the ith metal layer in other areas outside the ith through hole, wherein the ith metal layer in the ith through hole forms an ith contact through hole;
when the sum of the thicknesses of the first IMD and the iIMD is smaller than the target thickness, the steps are repeated until the sum of the thicknesses of the formed IMDs is larger than the target thickness, an n-th contact through hole formed in the uppermost nIMD is used for being connected with an electrode formed in a subsequent process, n is a natural number, and n is larger than or equal to i.
11. The method of claim 10, wherein at least two of the first contact vias are formed in the first IMD;
the number of the second contact through holes formed in the second IMD is the same as that of the first contact through holes formed in the first IMD, and one first contact through hole is connected below each second contact through hole;
the number of the ith contact through holes formed in the ith IMD is the same as that of the first contact through holes formed in the first IMD, and one ith-1 contact through hole is connected below each ith contact through hole.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207566B1 (en) * | 1999-12-02 | 2001-03-27 | United Microelectronics Corp. | Method for forming a metal plug on a semiconductor wafer |
| KR100781455B1 (en) * | 2006-11-24 | 2007-12-03 | 동부일렉트로닉스 주식회사 | Method for manufacturing wine glass type contact hole of the semiconductor device |
| CN101819943A (en) * | 2009-02-26 | 2010-09-01 | 中芯国际集成电路制造(上海)有限公司 | Processing method of fuse wire on copper interconnection layer and semiconductor device thereof |
| CN103594416A (en) * | 2012-08-13 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Method for forming double-mosaic structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100382729B1 (en) * | 2000-12-09 | 2003-05-09 | 삼성전자주식회사 | Metal contact structure in semiconductor device and forming method thereof |
| KR100505658B1 (en) * | 2002-12-11 | 2005-08-03 | 삼성전자주식회사 | Semiconductor device having MIM capacitor |
| KR100729126B1 (en) * | 2005-11-15 | 2007-06-14 | 동부일렉트로닉스 주식회사 | Metal line formation of semiconductor device and manufacturing method thereof |
-
2020
- 2020-10-14 CN CN202011096734.6A patent/CN112289738B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207566B1 (en) * | 1999-12-02 | 2001-03-27 | United Microelectronics Corp. | Method for forming a metal plug on a semiconductor wafer |
| KR100781455B1 (en) * | 2006-11-24 | 2007-12-03 | 동부일렉트로닉스 주식회사 | Method for manufacturing wine glass type contact hole of the semiconductor device |
| CN101819943A (en) * | 2009-02-26 | 2010-09-01 | 中芯国际集成电路制造(上海)有限公司 | Processing method of fuse wire on copper interconnection layer and semiconductor device thereof |
| CN103594416A (en) * | 2012-08-13 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Method for forming double-mosaic structure |
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