CN112289686B - Method for manufacturing semiconductor device and method for doping substrate - Google Patents
Method for manufacturing semiconductor device and method for doping substrate Download PDFInfo
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- CN112289686B CN112289686B CN201910671956.7A CN201910671956A CN112289686B CN 112289686 B CN112289686 B CN 112289686B CN 201910671956 A CN201910671956 A CN 201910671956A CN 112289686 B CN112289686 B CN 112289686B
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- 238000000034 method Methods 0.000 title claims abstract description 82
- 239000000758 substrate Substances 0.000 title claims abstract description 69
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 69
- 238000002955 isolation Methods 0.000 claims abstract description 53
- 230000007704 transition Effects 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims description 50
- -1 boron ions Chemical class 0.000 claims description 20
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000002513 implantation Methods 0.000 claims description 14
- 229910015900 BF3 Inorganic materials 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 12
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- 239000007789 gas Substances 0.000 description 41
- 239000000463 material Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000002035 prolonged effect Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010494 dissociation reaction Methods 0.000 description 2
- 230000005593 dissociations Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical group [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
Abstract
The disclosure provides a doping method of a substrate and a manufacturing method of a semiconductor device, and relates to the technical field of semiconductors. The doping method comprises the following steps: providing a wafer, wherein the wafer comprises a substrate, a first grid structure and a second grid structure, the first grid structure and the second grid structure are arranged on the substrate, and the substrate is provided with a shallow trench isolation area and a first well region and a second well region which are arranged on two sides of the shallow trench isolation area; the first gate structure covers a partial region of the first well region, and the second gate structure covers a partial region of the second well region. And performing first ion implantation on the first well region and the second well region by taking the first gate structure and the second gate structure as masks and the first gas as an ion source to form a first doped region in the first well region and a transition doped region in the second well region. And performing secondary ion implantation on the second well region by using a second gas as an ion source through a mask process to invert the doping type of at least part of the transitional doping region to obtain a second doping region.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor device and a method for doping a substrate.
Background
In a semiconductor process, ion implantation is a commonly used doping process, and in the manufacturing process of semiconductor devices such as transistors, ion implantation can be performed on a substrate to form a source region and a drain region, and the doping types are N doping and P doping according to the difference of implanted ions. At present, ion implantation is generally carried out on different areas by forming ion beams through an ion implanter, but the process is complex, so that the service life of the ion implanter is difficult to improve.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to overcome the above-mentioned deficiencies of the prior art and to provide a method for manufacturing a semiconductor device and a method for doping a substrate, which can simplify the process and prolong the lifetime of an ion implanter.
According to an aspect of the present disclosure, there is provided a doping method of a substrate, including:
providing a wafer, wherein the wafer comprises a substrate, and a first gate structure and a second gate structure which are arranged on the substrate, and the substrate is provided with a shallow trench isolation region, a first well region and a second well region which are separated from two sides of the shallow trench isolation region; the doping types of the first well region and the second well region are different; the first gate structure and the second gate structure are separated from two sides of the shallow trench isolation region, the first gate structure covers a partial region of the first well region, and the second gate structure covers a partial region of the second well region;
performing first ion implantation on the first well region and the second well region by using the first gate structure and the second gate structure as masks and using a first gas as an ion source through a first ion implantation process to form a first doped region in the first well region and a transition doped region in the second well region;
performing secondary ion implantation on the second well region by using a mask process by taking a second gas as an ion source to invert the doping type of at least one part of the transitional doping region to obtain a second doping region; the depth of the first ion implantation is less than the depth of the second ion implantation, and the corrosiveness of the first gas is greater than that of the second gas.
In an exemplary embodiment of the present disclosure, the first well region is an N-well, and the second well region is a P-well; the first doped region is a P-type doped region, and the second doped region is an N-type doped region.
In one exemplary embodiment of the present disclosure, the first gas comprises boron fluoride and the second gas comprises phosphine; the ions of the first ion implantation comprise boron ions, and the ions of the second ion implantation comprise phosphorus ions.
In an exemplary embodiment of the present disclosure, the implantation dose of the boron ions is 1E13/cm2To 8E13/cm2The implantation dosage of the phosphorus ions is 6E14/cm2To 3E15/cm2。
In an exemplary embodiment of the disclosure, performing a second ion implantation on the second well region through a mask process with a second gas as an ion source to invert a doping type of at least a part of the transition doping region, so as to obtain a second doping region, includes:
forming a mask layer covering the substrate, the first gate structure and the second gate structure, wherein the mask layer shields the first well region and exposes the second well region;
performing second ion implantation on the second well region through the mask layer to invert the doping type of at least one part of the transitional doping region to obtain a second doping region;
and removing the mask layer.
In an exemplary embodiment of the disclosure, a region of the mask layer covering the first well region extends to the shallow trench isolation region toward the second well region.
In an exemplary embodiment of the present disclosure, the first gate structure includes a plurality of first gates, the first gates are spaced apart from each other in a direction away from the shallow trench isolation region, and each of the first gates covers a partial region of the first well region;
the second grid structure comprises a plurality of second grids which are distributed at intervals along the direction far away from the shallow trench isolation region; each second gate electrode covers a partial region of the second well region.
In an exemplary embodiment of the present disclosure, the number of the first gates is two, and one of the first gates is located entirely in the first well region, and the other of the first gates is partially located in the first well region; the first doped region comprises a first source region and a first drain region which are mutually spaced, the first source region is positioned between the first drain region and the shallow trench isolation region, the first grid electrode which is completely positioned in the first well region is connected between the first source region and the first drain region, and the first grid electrode which is partially positioned in the first well region is connected with the first drain region;
the number of the second grid electrodes is two, one second grid electrode is completely positioned in the second well region, and the other second grid electrode is partially positioned in the second well region; the second doped region comprises a second source region and a second drain region which are spaced from each other, the second source region is located between the second drain region and the shallow trench isolation region, the second gate electrode which is located in the second well region is connected between the second source region and the second drain region, and the second gate electrode which is located in the second well region is connected with the second drain region.
In an exemplary embodiment of the present disclosure, each of the first gate structure and the second gate structure includes a gate oxide layer, a polysilicon layer, a metal layer, and a support layer sequentially stacked on the substrate.
According to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including:
forming a substrate, wherein the substrate is provided with a shallow trench isolation region, a first well region and a second well region which are separated from two sides of the shallow trench isolation region; the doping types of the first well region and the second well region are different;
forming a first gate structure and a second gate structure on the substrate, wherein the first gate structure and the second gate structure are separated from two sides of the shallow trench isolation region, the first gate structure covers a partial region of the first well region, and the second gate structure covers a partial region of the second well region;
performing first ion implantation on the first well region and the second well region by using the first gate structure and the second gate structure as masks and using a first gas as an ion source through a first ion implantation process to form a first doped region in the first well region and a transition doped region in the second well region;
performing secondary ion implantation on the second well region by using a mask process by taking a second gas as an ion source to invert the doping type of at least one part of the transitional doping region to obtain a second doping region; the depth of the first ion implantation is less than the depth of the second ion implantation, and the corrosiveness of the first gas is greater than that of the second gas.
The doping method and the manufacturing method of the present disclosure may first dope the first well region and the second well region, then shield the first well region, and perform a second ion implantation on the transition doping region of the second well region, so as to invert the doping type of at least a portion of the transition doping region, thereby obtaining the second doping region. In the process, only two ion sources are needed to be adopted, and doping ions for controlling the first ion implantation depth are not needed to be implanted, so that the process is simplified, the cost is reduced, and the production efficiency is improved. Meanwhile, the corrosivity of the first gas is stronger than that of the second gas, but the depth of the first ion implantation is smaller, so that the time for introducing the first gas into the ion implanter is shortened, the loss of the ion implanter is reduced, and the service life is prolonged.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a flow chart of an embodiment of a doping method according to the present disclosure.
Fig. 2 is a flowchart of step S130 of an embodiment of the doping method of the disclosure.
Fig. 3 is a schematic diagram of step S110 according to an embodiment of the doping method of the disclosure.
Fig. 4 is a schematic diagram of step S120 of an embodiment of the doping method of the disclosure.
Fig. 5 is a schematic diagram of step S1310 according to an embodiment of the doping method of the disclosure.
Fig. 6 is a schematic diagram of step S1320 of an embodiment of the doping method according to the disclosure.
Fig. 7 is a schematic diagram of step S1330 in one embodiment of the doping method of the present disclosure.
FIG. 8 is a flow chart of one embodiment of a method of manufacturing the present disclosure.
Description of reference numerals:
1. a substrate; 101. a first surface; 102. a second surface; 11. shallow trench isolation regions; 12. a first well region; 121. a first doped region; 1211. a first source region; 1212. a first drain region; 13. a second well region; 131. a second doped region; 1311. a second source region; 1312. a second drain region; 14. a transition doped region; 141. a source transition region; 142. a drain transition region; 21. a first gate structure; 211. a first gate electrode; 22. a second gate structure; 221. a second gate electrode; 201. a gate oxide layer; 202. a polysilicon layer; 203. a metal layer; 204. a support layer; 205. an isolation layer; 100. and (5) masking the layer.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first" and "second" are used merely as labels, and are not limiting on the number of their objects.
In the related art, a process of doping a semiconductor substrate is widely applied to various semiconductor devices, such as transistors, Dynamic Random Access Memories (DRAMs), and the like. Ion implantation is a common doping process, and it is usually performed by implanting ions into a specific region of a substrate by using an ion implanter to obtain a source region and a drain region. Of course, it can also be used for the formation of N-well and P-well.
Taking a substrate with a double-well structure as an example, the substrate is provided with a P well, an N well and a shallow trench isolation area for separating the P well and the N well, and gates are formed on the P well and the N well. When doping the substrate to obtain a source region and a drain region:
phosphine (PH) can be first used3) The method comprises the following steps of (1) taking gas as an ion source, carrying out first ion implantation by using an ion implanter, forming N doped regions on a P trap and an N trap, wherein the N doped regions of the P trap are a source region and a drain region of the P trap;
then, shielding the P trap by using a mask, carrying out secondary ion implantation on the N trap, and carrying out indium doping so as to limit the implantation depth of carrying out P doping by using boron ions subsequently;
then, Boron Fluoride (BF) is used3) Using gas as an ion source, performing third ion implantation on the N trap by using an ion implanter, and limiting the implantation depth of boron ions by indium doping; and inverting the N doped region of the N well into a P doped region to obtain a source region and a drain region of the N well. The implantation dosage of the boron ions can be 8E14/cm2-5E15/cm2The implantation dosage of the phosphorus ions can be 2E13/cm2-1E14/cm2。
In this process, in order to improve the throughput and ensure that the implantation amount is enough to invert the N-doped region into the P-doped region, the third ion implantation has a larger dose and requires higher energy, but in order to realize the shallow implantation, the implantation depth of boron ions needs to be limited by indium doping.
Applicants have found that the lifetime of an ion implanter using boron fluoride gas alone is shorter than that of phosphine gas alone, and that in general, the maintenance cycle of an ion implanter using boron fluoride gas alone is only about one week, whereas the maintenance cycle of phosphine gas alone is about 10 to 12 days. Meanwhile, the filament of the gas dissociation cavity of the ion implanter is made of tungsten, boron fluoride gas can continuously impact the filament in the dissociation process, so that the filament mechanism is loose, and plasma dissociated from boron fluoride can deposit a film on the surface of the filament, so that the service life and the injection effect of the ion implanter are influenced.
The embodiment of the present disclosure provides a doping method of a substrate, as shown in fig. 1, the doping method includes steps S110 to S130, wherein:
step S110, providing a substrate, wherein the substrate comprises a substrate, and a first gate structure and a second gate structure which are arranged on the substrate, and the substrate is provided with a shallow trench isolation region, and a first well region and a second well region which are separated from two sides of the shallow trench isolation region; the doping types of the first well region and the second well region are different; the first gate structure and the second gate structure are separated from two sides of the shallow trench isolation region, the first gate structure covers a partial region of the first well region, and the second gate structure covers a partial region of the second well region.
Step S120, with the first gate structure and the second gate structure as masks and a first gas as an ion source, performing a first ion implantation process on the first well region and the second well region to form a first doped region in the first well region and a transition doped region in the second well region.
Step S130, taking a second gas as an ion source, and performing second ion implantation on the second well region through a mask process to invert the doping type of at least one part of the transitional doping region to obtain a second doping region; the depth of the first ion implantation is less than the depth of the second ion implantation, and the corrosiveness of the first gas is greater than that of the second gas.
In the doping method of the embodiment of the disclosure, the first doping may be performed on the first well region and the second well region, the first doping region of the first well region is then shielded, and the second ion implantation may be performed on the transition doping region of the second well region, so that the doping type of at least a part of the transition doping region is reversed, and the second doping region is obtained. In the process, only two ion sources are needed, shallow layer injection can be realized firstly, and ions for controlling the first ion injection depth are not injected, such as indium doping, so that the process is simplified, the cost is reduced, and the production efficiency is improved. Meanwhile, the corrosivity of the first gas is stronger than that of the second gas, but the depth of the first ion implantation is smaller, so that the time for introducing the first gas into the ion implanter is shortened, the loss of the ion implanter is reduced, and the service life is prolonged.
The following describes the steps of the doping method according to the embodiment of the present disclosure in detail:
in step S110, as shown in fig. 3, the base includes a substrate 1, a first gate structure 21 and a second gate structure 22, wherein:
the material of the substrate 1 may be monocrystalline silicon, but also other semiconductor materials, such as sapphire and silicon carbide. The substrate 1 may have a shallow trench isolation region 11, a first well region 12 and a second well region 13, where the first well region 12 and the second well region 13 are located at two sides of the shallow trench isolation region 11 and are separated by the shallow trench isolation region 11.
In the thickness direction, the substrate 1 has a first surface 101 and a second surface 102 opposite to each other, the shallow trench isolation 11 is located on a side of the first surface 101 close to the second surface 102, and a surface of the shallow trench isolation 11 away from the second surface 102 is flush with the first surface 101, that is, located on the same plane.
Both the first well region 12 and the second well region 13 may be formed by a doping process, but the doping types of the first well region 12 and the second well region 13 are different, for example: the first well region 12 is an N-well, and the second well region 13 is a P-well; alternatively, the first well region 12 is a P-well and the second well region 13 is an N-well.
As shown in fig. 3, the first gate structure 21 and the second gate structure 22 may be disposed on the substrate 1, for example, on the first surface 101, the shallow trench isolation 11 is separated between the first gate structure 21 and the second gate structure 22, and the first gate structure 21 covers a partial area of the first well region 12, that is, an orthographic projection of the first gate structure 21 on the substrate 1 coincides with a partial area of the first well region 12. The second gate structure 22 covers a partial area of the second well region 13, i.e. an orthographic projection of the second gate structure 22 on the substrate 1 coincides with the partial area of the second well region 13.
In an embodiment, as shown in fig. 3, each of the first gate structure 21 and the second gate structure 22 includes a gate oxide layer 201, a polysilicon layer 202, a metal layer 203, and a support layer 204 sequentially stacked on the substrate 1 in a direction away from the substrate 1, wherein:
the material of the gate oxide layer 201 may be an oxide such as silicon dioxide. The polysilicon layer 202 is disposed on the surface of the gate oxide layer 201 away from the substrate 1. The metal layer 203 is disposed on the surface of the polysilicon layer 202 away from the substrate 1, and the material of the metal layer 203 may be tungsten or other metals so as to improve the conductivity; the contact interface of the metal layer 203 and the polysilicon layer 202 may have a silicide layer of the metal, for example, the material of the metal layer 203 is tungsten, and the silicide layer is tungsten silicide. The support layer 204 is disposed on a surface of the metal layer 203 away from the substrate 1, and the support layer 204 may be a hard material such as silicon nitride, so as to enhance the strength of the first gate structure 21 and the second gate structure 22.
For the first gate structure 21 and the second gate structure 22, the gate oxide layer 201 of both may be formed by one patterning process, the polysilicon layer 202 of both may be formed by one patterning process, the metal layer 203 of both may be formed by one patterning process, and the support layer 204 of both may be formed by one patterning process.
The first gate structure 21 includes a plurality of first gates 211, each of the first gates 211 is spaced apart from the shallow trench isolation 11, and each of the first gates 211 covers a portion of the first well region 12.
The second gate structure 22 includes a plurality of second gates 221, and the second gates 221 are distributed at intervals along a direction away from the shallow trench isolation region 11; each of the second gates 221 covers a partial region of the second well region 13.
In addition, as shown in fig. 3, in an embodiment, each of the first gate 211 and the second gate 221 includes the gate oxide 201, the polysilicon layer 202, the metal layer 203, and the support layer 204, which are sequentially stacked on the substrate 1, and meanwhile, an outer surface of each of the first gate 211 and the second gate 221 is further covered with an isolation layer 205, and the isolation layer 205 includes a side portion covering a sidewall of the first gate 211 and a sidewall of the second gate 221, and a top portion covering a surface of the support layer 204 away from the substrate 1.
In step S120, as shown in fig. 4, the first gate structure 21 and the second gate structure 22 shield a partial region of the substrate 1, specifically, the first gate structure 21 shields a partial region of the first well region 12, and the second gate structure 22 shields a partial region of the second well region 13. The first gate structure 21 and the second gate structure 22 may be used as a mask of the substrate 1, and a first gas is used as an ion source to perform a first ion implantation process on the first well region 12 and the second well region 13 through a first ion implantation process, so as to form a first doped region 121 in the first well region 12 and a transitional doped region 14 in the second well region 13, where the first doped region 121 and the transitional doped region 14 are formed through the first ion implantation process, and thus the doping types of the two regions are the same.
As shown in fig. 4, in an embodiment, the number of the first gate electrodes 211 of the first gate structure 21 is two, and one first gate electrode 211 is entirely located in the first well region 12, and the other first gate electrode 211 is partially located in the first well region 12; the first doped region 121 includes a first source region 1211 and a first drain region 1212 which are spaced apart from each other, the first source region 1211 is located between the first drain region 1212 and the shallow trench isolation 11, the first gate 211 completely located in the first well region 12 is connected between the first source region 1211 and the first drain region 1212, and the first gate 211 located in the first well region 12 is connected to a side of the first drain region 1212 which is far from the first source region 1211.
The number of the second gates 221 of the second gate structure 22 is two, and one second gate 221 is entirely located in the second well region 13, and the other second gate 221 is partially located in the second well region 13. The transitional doping region 14 includes a source transitional region 141 and a drain transitional region 142 that are spaced from each other, the source transitional region 141 is located between the shallow trench isolation region 11 and the drain transitional region 142, all of the second gates 221 located in the second well region 13 are connected between the source transitional region 141 and the drain transitional region 142, and the portion of the second gates 221 located in the second well region 13 are connected to a side of the drain transitional region 142 away from the source transitional region 141.
The doping type of the first doping region 121 may be a P-type doping region, and accordingly, the composition of the first gas may include boron fluoride, and boron ions may be implanted by an ion implanter into a region of the substrate 1 not shielded by the first gate structure 21 and the second gate structure 22, so as to implement P-doping.
In step S130, as shown in fig. 5 and fig. 6, the first doping region 121 of the first well region 12 is not doped, i.e., ion implantation is not required; the second well region 13 needs to be doped for the second time, i.e. the second ion implantation, so as to invert the type of at least a partial region of the transitional doping region 14 of the second well region 13, thereby obtaining a second doping region 131. Specifically, the second gas may be used as an ion source, and the second ion implantation may be performed on the second well region 13 through a mask process. The second gas may be phosphine and, correspondingly, the ions for the second ion implantation are phosphorous ions, although other gases are possible.
In one embodiment, the source transition region 141 is inverted to become the second source region 1311 of the second doping region 131, and the drain transition region 142 is inverted to become the second drain region 1312 of the second doping region 131. The second source region 1311 is located between the second drain region 1312 and the shallow trench isolation region 11, the second gate 221, which is located entirely in the second well region 13, is connected between the second source region 1311 and the second drain region 1312, and the second gate 221, which is located partially in the second well region 13, is connected to a side of the second drain region 1312, which is far from the second source region 1311.
The depth of the first ion implantation is smaller than that of the second ion implantation, and the first ion implantation does not realize the inversion of the doping type, so that the ion implantation can be completed without higher dosage and energy, the service time of the first gas can be shortened, the corrosivity of the first gas is higher than that of the second gas, for example, the second gas is phosphine, and the first gas is boron fluoride. Therefore, the loss of the ion implanter can be reduced, and the service life is prolonged.
The process of performing the second ion implantation through the mask process in step S130 is exemplarily described as follows:
as shown in fig. 2, in an embodiment, a second ion implantation is performed on the second well region through a mask process to invert the doping type of at least a portion of the transitional doping region, so as to obtain a second doping region, i.e., step S130, which includes steps S1310-S1330, wherein:
in step S1310, a mask layer is formed to cover the substrate, the first gate structure 21 and the second gate structure 22, and the mask layer covers the first well region and exposes the second well region.
As shown in fig. 5, the material of the mask layer 100 may be a photoresist, which may have a shielding region and an exposed region, wherein the shielding region shields the first well region 12 and the first gate structure 21 thereon, and the exposed region exposes the second well region 13 and the second gate structure 22 thereon.
Meanwhile, the region of the mask layer 100 covering the first well region 12 may extend toward the second well region 13 and extend onto the shallow trench isolation region 11, so as to expand the shielding range without shielding the second well region 13, and to prevent the second ion implantation from being performed on the first well region 12 to the greatest extent.
The forming of the mask layer 100 may include: a photoresist layer may be first applied by spin coating or the like, and the photoresist layer covers the substrate 1, the first gate structure 21 and the second gate structure 22. And then exposing and developing the photoresist layer to form a shielding area and an exposed area. Of course, the mask layer 100 may be other materials such as silicon nitride, and the formation process thereof depends on the materials and is not described in detail herein.
Step S1320, performing a second ion implantation on the second well region through the mask layer to invert the doping type of at least a part of the transitional doping region, so as to obtain a second doping region.
As shown in fig. 6, a second ion implantation may be performed on the substrate 1 from a side of the mask layer 100 away from the substrate 1, and since the shielding region shields the first well region 12, the second ion implantation does not implant ions into the first well region 12, but implants ions into the second well region 13, so as to realize inversion of the transition doped region 14, thereby obtaining a second doped region 131.
Step S1330, the mask layer is removed.
As shown in fig. 7, the process of removing the mask layer 100 depends on the material, for example, the mask layer 100 is a photoresist and can be removed by ashing or the like, and if the material is a metal or silicon nitride and the like, the process can be removed by etching, which is not described in detail herein.
In one embodiment, as shown in fig. 7, the first well region 12 of the substrate 1 is an N-well, and the second well region 13 is a P-well; the first doped region 121 is a P-type doped region, and the second doped region 131 is an N-type doped region. The first ion implantation adopts boron fluoride gas, the implanted ions comprise boron ions, the second ion implantation adopts phosphine gas, the implanted ions comprise phosphorus ions, wherein the implantation dosage of the boron ions is 1E13/cm2To 8E13/cm2For example 1E13/cm2、3E13/cm2Or 8E13/cm2And the implantation dosage of the phosphorus ions is 6E14/cm2To 3E15/cm2E.g. 6E14/cm- 2、3E15/cm2And the like. It can be seen that the implantation amount of boron ions of the present disclosure is significantly lower than that of the related art, and the service life of the ion implanter can be extended because boron fluoride has a large loss to the ion implanter.
The embodiments of the present disclosure also provide a method for manufacturing a semiconductor device, which may be a transistor with a double-well structure, and may also be a memory including the transistor, such as a DRAM, and the like, which are not listed here. As shown in fig. 8, the manufacturing method includes steps S210 to S240, in which:
step S210, forming a substrate, wherein the substrate is provided with a shallow trench isolation region, a first well region and a second well region which are separated from two sides of the shallow trench isolation region; the doping types of the first well region and the second well region are different.
Step S220, forming a first gate structure and a second gate structure on the substrate, the first gate structure and the second gate structure being separated from each other at two sides of the shallow trench isolation region, the first gate structure covering a partial region of the first well region, and the second gate structure covering a partial region of the second well region.
Step S230, using the first gate structure and the second gate structure as masks, performing a first ion implantation on the first well region and the second well region through a first ion implantation process, so as to form a first doped region in the first well region and a transition doped region in the second well region.
Step S240, performing a second ion implantation on the second well region through a mask process to invert the doping type of at least a part of the transition doping region, so as to obtain a second doping region.
The manufacturing method of the embodiment of the present disclosure includes the above doping method, and thus has the same beneficial effects, and is not described herein again.
In step S210, the structure of the substrate can refer to the above description of step S110, and is not described in detail here. Wherein, forming the substrate, i.e. step S210, may include:
step S2110, forming a semiconductor material layer;
step S2120, a trench is formed on the semiconductor material layer, and an isolation material is filled in the trench to obtain a shallow trench isolation region.
Step 2130 of forming a first well region on one side of the shallow trench isolation region through a mask process, and forming a second well region on one side of the shallow trench isolation region away from the first well region, wherein the first well region and the second well region are different in doping type.
In step S220, the specific structure of the first gate structure and the second gate structure can refer to the above description of the first gate structure and the second gate structure in the doping method, and will not be described in detail here. For example, the first gate structure and the second gate structure each include a gate oxide layer, a polysilicon layer, a metal layer, and a support layer stacked in sequence on the substrate, and further include an isolation layer covering the first gate and the second gate, and the gate oxide layer, the polysilicon layer, the metal layer, the support layer, and the isolation layer may be formed layer by multiple mask processes.
The details of step S230 and step S240 have already been described in detail in step S120 and step S130 above, and are not described again here.
It should be noted that although the various steps of the doping method and the fabrication method of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (10)
1. A method of doping a substrate, comprising:
providing a wafer, wherein the wafer comprises a substrate, and a first gate structure and a second gate structure which are arranged on the substrate, and the substrate is provided with a shallow trench isolation region, a first well region and a second well region which are separated from two sides of the shallow trench isolation region; the doping types of the first well region and the second well region are different; the first gate structure and the second gate structure are separated from two sides of the shallow trench isolation region, the first gate structure covers a partial region of the first well region, and the second gate structure covers a partial region of the second well region;
performing first ion implantation on the first well region and the second well region by using the first gate structure and the second gate structure as masks and using a first gas as an ion source through a first ion implantation process to form a first doped region in the first well region and a transition doped region in the second well region;
performing secondary ion implantation on the second well region by using a mask process by taking a second gas as an ion source to invert the doping type of at least one part of the transitional doping region to obtain a second doping region; the depth of the first ion implantation is less than the depth of the second ion implantation, and the corrosiveness of the first gas is greater than that of the second gas.
2. The doping method according to claim 1, wherein the first well region is an N-well, and the second well region is a P-well; the first doped region is a P-type doped region, and the second doped region is an N-type doped region.
3. The doping method according to claim 2, wherein the first gas comprises boron fluoride and the second gas comprises phosphine; the ions of the first ion implantation comprise boron ions, and the ions of the second ion implantation comprise phosphorus ions.
4. The doping method according to claim 3, wherein the implantation dose of the boron ions is 1E13/cm2To 8E13/cm2The implantation dosage of the phosphorus ions is 6E14/cm2To 3E15/cm2。
5. The doping method according to claim 1, wherein performing a second ion implantation on the second well region through a mask process using a second gas as an ion source to invert the doping type of at least a portion of the transitional doping region, so as to obtain a second doping region, comprises:
forming a mask layer covering the substrate, the first gate structure and the second gate structure, wherein the mask layer shields the first well region and exposes the second well region;
performing second ion implantation on the second well region through the mask layer to invert the doping type of at least one part of the transitional doping region to obtain a second doping region;
and removing the mask layer.
6. The method of claim 5, wherein the mask layer covers a region of the first well region extending over the shallow trench isolation region toward the second well region.
7. The doping method according to claim 1, wherein the first gate structure includes a plurality of first gates, the first gates are spaced apart from each other in a direction away from the shallow trench isolation region, and each of the first gates covers a partial region of the first well region;
the second grid structure comprises a plurality of second grids which are distributed at intervals along the direction far away from the shallow trench isolation region; each second gate electrode covers a partial region of the second well region.
8. The doping method according to claim 7, wherein an area of an orthographic projection of the first gate on the substrate is smaller than an area of the first well region; the number of the first grid electrodes is two, one first grid electrode is completely positioned in the first well region, and the other first grid electrode is partially positioned in the first well region; the first doped region comprises a first source region and a first drain region which are mutually spaced, the first source region is positioned between the first drain region and the shallow trench isolation region, the first grid electrode which is completely positioned in the first well region is connected between the first source region and the first drain region, and the first grid electrode which is partially positioned in the first well region is connected with the first drain region;
the area of the orthographic projection of the second grid electrode on the substrate is smaller than that of the second well region; the number of the second grid electrodes is two, one second grid electrode is completely positioned in the second well region, and the other second grid electrode is partially positioned in the second well region; the second doped region comprises a second source region and a second drain region which are spaced from each other, the second source region is located between the second drain region and the shallow trench isolation region, the second gate electrode which is located in the second well region is connected between the second source region and the second drain region, and the second gate electrode which is located in the second well region is connected with the second drain region.
9. The doping method according to claim 1, wherein the first gate structure and the second gate structure each comprise a gate oxide layer, a polysilicon layer, a metal layer and a support layer sequentially stacked on the substrate.
10. A method of manufacturing a semiconductor device, comprising:
forming a substrate, wherein the substrate is provided with a shallow trench isolation region, a first well region and a second well region which are separated from two sides of the shallow trench isolation region; the doping types of the first well region and the second well region are different;
forming a first gate structure and a second gate structure on the substrate, wherein the first gate structure and the second gate structure are separated from two sides of the shallow trench isolation region, the first gate structure covers a partial region of the first well region, and the second gate structure covers a partial region of the second well region;
performing first ion implantation on the first well region and the second well region by using the first gate structure and the second gate structure as masks and using a first gas as an ion source through a first ion implantation process to form a first doped region in the first well region and a transition doped region in the second well region;
performing secondary ion implantation on the second well region by using a mask process by taking a second gas as an ion source to invert the doping type of at least one part of the transitional doping region to obtain a second doping region; the depth of the first ion implantation is less than the depth of the second ion implantation, and the corrosiveness of the first gas is greater than that of the second gas.
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