CN112271229B - 一种硅基背照pin器件结构 - Google Patents
一种硅基背照pin器件结构 Download PDFInfo
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Abstract
本发明公开一种硅基背照PIN器件结构,包括基片,基片正面边缘注入有P+离子层,基片正面沉积有外延层,外延层表面设有氧化层;外延层设有与P+离子层相对应的P阱;外延层还设有N+保护环,P+隔离区以及N‑光敏区;氧化层上形成四象限分布的四个N‑光敏区,氧化层还设有实现器件结构自连与互连的Al引线;所述基片背面设有抗反射膜,抗反射膜外表面设有对背面光敏区进行四象限隔离的Al金属层;该PIN器件结构组件体积至少减小三分之二,实现PIN光电探测器P+与N+处于横向互连,基于背照PIN结构,完成了PIN结构光电探测器系统集成一体化,同时满足光电性能要求。
Description
技术领域
本发明涉及半导体光电技术领域,具体是一种硅基背照PIN器件结构。
背景技术
耗尽型光电探测器PIN光电二极管经常被使用在激光方位探测中,之所以这种器件叫做PIN 光电二极管,主要就是因为有一层本征层(I 层)在P--N结之间。
PIN结构光电探测器具有高灵敏度和高分辨率、低功耗、响应速度快等特点,广泛应用于光通信、其他快速光电自动控制装备系统领域;PIN光敏二极管由于其结构的优越性和良好的光电响应特性,在光通信、光测距、光度测量及光电控制等方面有着重要的应用。
为了更好地改善波长范围和频响,往往对控制本征层的厚度进行有效地控制,这样减少其和反偏压下耗尽层宽度的差距。器件的灵敏度和频响在很大程度上取决于PIN光电二极管中的本征层。这主要是因为本征层和P区N区比较是高阻区,本征层是反向偏压比较集中的区域,也正是因为如此,高电场区就在这个区间形成,而高电场区的电阻大,故而减小了暗电流。本征层引入之后能够加大耗尽层区,因此光电转换的有效区域得以增加,从而明显提高了其灵敏性。
P区非常薄,加之本征层的作用,所以在本征层内入射光子就能都被吸收,这样也就形成了电子--空穴对。在强电场作用下,光生载流子加速运动,这就缩短了截流子的渡越时间。由于加宽了耗尽层,导致结电容Cd 减小,从而电容时间常数也相应地减小,这样就使光电二极管的频响得到了很好地改善。若是光电二极管的性能良好,则其一般会有10-10s量级的扩散与漂移时间,故而电路时间常数是影响光电二极管频响的主因,一般来讲,光电二极管的结电容通常为几个皮法。如果将反向偏压适当增大的话,还会使减小。为了得到高响应频率性能,在实际的应用中,需要注意的就是合理选择负载电阻 。
目前,诸多PIN光电探测器件得到了广泛应用,现有的PIN光电探测器都是前照式,通过各组件组装而成,体积大,已经不能适应复杂环境下的应用。
发明内容
本发明的目的在于提供一种硅基背照PIN器件结构,该PIN器件结构组件体积至少减小三分之二,实现PIN光电探测器P+与N+处于横向互连,基于背照PIN结构,完成了PIN结构光电探测器系统集成一体化,同时满足光电性能要求。
本发明解决其技术问题所采用的技术方案是:
一种硅基背照PIN器件结构,包括基片,基片正面边缘注入有P+离子层,基片正面沉积有外延层,外延层表面设有氧化层;外延层设有与P+离子层相对应的P阱;外延层还设有N+保护环,P+隔离区以及N-光敏区;氧化层上形成四象限分布的四个N-光敏区,N-光敏区通过P+隔离区实现相互隔离;N+保护环作为N-光敏区的欧姆接触,并将N-光敏区包围;氧化层设有与N+保护环,P+隔离区以及N-光敏区相对应的开窗;氧化层还设有实现器件结构自连与互连的Al引线;所述基片背面设有抗反射膜,抗反射膜外表面设有对背面光敏区进行四象限隔离的Al金属层。
本发明的有益效果是,将传统的PIN光电探测器组件大体积组装进行微系统化集成,通过背照PIN结构植球压焊方式将PIN光电探测器组件体积至少减小三分之二,实现PIN光电探测器P+与N+处于横向互连,基于背照PIN结构,完成了PIN结构光电探测器系统集成一体化,同时其光电性能参数满足设计要求。
附图说明
下面结合附图和实施例对本发明进一步说明:
图1是本发明的结构示意图;
图2是本发明的俯视图。
具体实施方式
结合图1与图2所示,本发明提供一种硅基背照PIN器件结构,包括基片1,基片1正面边缘注入有P+离子层2,基片1正面沉积有外延层3,外延层3表面设有氧化层4;外延层设有与P+离子层相对应的P阱5;外延层还设有N+保护环6,P+隔离区7以及N-光敏区8;氧化层上形成四象限分布的四个N-光敏区,N-光敏区通过P+隔离区实现相互隔离;N+保护环作为N-光敏区的欧姆接触,并将N-光敏区包围;氧化层设有与N+保护环,P+隔离区以及N-光敏区相对应的开窗9;氧化层还设有实现器件结构自连与互连的Al引线10;所述基片背面设有抗反射膜11,抗反射膜11外表面设有对背面光敏区进行四象限隔离的Al金属层12。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制;任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同替换、等效变化及修饰,均仍属于本发明技术方案保护的范围内。
Claims (1)
1.一种硅基背照PIN器件结构,其特征在于,包括基片,基片正面边缘注入有P+离子层,基片正面沉积有外延层,外延层表面设有氧化层;外延层设有与P+离子层相对应的P阱;外延层还设有N+保护环,P+隔离区以及N-光敏区;氧化层上形成四象限分布的四个N-光敏区,N-光敏区通过P+隔离区实现相互隔离;N+保护环作为N-光敏区的欧姆接触,并将N-光敏区包围;氧化层设有与N+保护环,P+隔离区以及N-光敏区相对应的开窗;氧化层还设有实现器件结构自连与互连的Al引线;所述基片背面设有抗反射膜,抗反射膜外表面设有对背面光敏区进行四象限隔离的Al金属层。
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CN101494244A (zh) * | 2009-03-04 | 2009-07-29 | 中国科学院上海技术物理研究所 | 背照射平面型PIN结构GaN基紫外探测器及制备方法 |
US7576371B1 (en) * | 2006-03-03 | 2009-08-18 | Array Optronix, Inc. | Structures and methods to improve the crosstalk between adjacent pixels of back-illuminated photodiode arrays |
CN102176470A (zh) * | 2011-03-26 | 2011-09-07 | 电子科技大学 | 一种以黑硅材料为光敏层的背照式Si-PIN光电探测器及其制备方法 |
CN103400887A (zh) * | 2013-08-08 | 2013-11-20 | 电子科技大学 | 一种背照式Si-PIN光电探测器及其制备方法 |
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US7576371B1 (en) * | 2006-03-03 | 2009-08-18 | Array Optronix, Inc. | Structures and methods to improve the crosstalk between adjacent pixels of back-illuminated photodiode arrays |
CN101494244A (zh) * | 2009-03-04 | 2009-07-29 | 中国科学院上海技术物理研究所 | 背照射平面型PIN结构GaN基紫外探测器及制备方法 |
CN102176470A (zh) * | 2011-03-26 | 2011-09-07 | 电子科技大学 | 一种以黑硅材料为光敏层的背照式Si-PIN光电探测器及其制备方法 |
CN103400887A (zh) * | 2013-08-08 | 2013-11-20 | 电子科技大学 | 一种背照式Si-PIN光电探测器及其制备方法 |
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