CN112271147A - Chip information checking method - Google Patents
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- CN112271147A CN112271147A CN202011141226.5A CN202011141226A CN112271147A CN 112271147 A CN112271147 A CN 112271147A CN 202011141226 A CN202011141226 A CN 202011141226A CN 112271147 A CN112271147 A CN 112271147A
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- H—ELECTRICITY
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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Abstract
Providing a method for checking chip information, and providing an integrated circuit wafer which comprises a plurality of tested chips; acquiring identification chip information of a tested chip; comparing the background chip information and the identification chip information of the same tested chip to confirm whether the background chip information and the identification chip information are matched; if not, searching for a mismatching reason, correcting the mismatching reason after the reason is found, and returning to obtain the identification chip information of each tested chip; and if so, recording the test data and the test result of the tested chip. According to the method, on the premise that the testing efficiency is not influenced, the chip information is compared and verified in real time, the chip information error is found at the first time, the error reason is found, retesting caused by later finding or unqualified chips are prevented from flowing into the next link, and loss which cannot be compensated is avoided; on the premise that the testing time is not changed, whether the chip information of the tested chip is correct or not is checked and recorded in real time, and the chip information traceability of the tested chip is improved.
Description
Technical Field
The invention relates to the field of semiconductor testing, in particular to a chip information verification method.
Background
In the testing process of the integrated circuit wafer, the test data and the test results of all the tested chips are usually stored, and the chip information of each tested chip on each integrated circuit wafer needs to be in one-to-one correspondence with the specific test data and the test results thereof. Therefore, during testing, information such as lot number, chip number, and position coordinates of the chip under test, which is identified by Optical Character Recognition (OCR), is read back from an integrated circuit probe station (Prober) through a General-Purpose Interface Bus (GPIB), and the information is recorded, and then detailed test data and test results corresponding to the chip under test are saved.
However, the OCR recognition may be abnormal, resulting in a lot number error of the tested chip; or, the position coordinate of the tested chip is wrong due to the abnormal GPIB communication, which causes the final recorded information error of the tested chip, so that the information errors cannot correspond to the actual test data one by one, and the information errors cannot correspond to the actual test result one by one. If the problems are not found in time, the tested chips with unqualified actual test results flow into the next link, so that the tested chips cannot be traced.
Disclosure of Invention
The invention aims to provide a chip information verification method to solve the problem that in the prior art, a tested chip with wrong information record flows into the next link, or information errors are discovered later, so that retesting is caused.
In order to solve the above problems, the present invention provides a method for verifying chip information, comprising the following steps:
step S1: providing an integrated circuit wafer, wherein the integrated circuit wafer comprises a plurality of tested chips, the tested chips are subjected to a plurality of test items, and each tested chip comprises background chip information;
step S2: acquiring identification chip information of each tested chip;
step S3: comparing the background chip information and the identification chip information of the same tested chip to confirm whether the background chip information and the identification chip information of the tested chip are matched or not;
step S4: if the background chip information and the identification chip information of the tested chip are not matched, searching for a mismatch reason, correcting the mismatch reason after the reason is found, and returning to the step S2; or if the background chip information of the tested chip is matched with the identification chip information, recording the test data and the test result of the tested chip.
Optionally, the background chip information of each of the chips under test is binary data.
Further, the batch number, the chip number, the position coordinates, the streaming chip factory code and the test factory code of each tested chip are firstly converted by ASCII codes, and then binary translation is carried out to obtain the background chip information.
Optionally, step S2 includes:
reading back the identification chip information of each tested chip by optical characters from the integrated circuit probe station through a universal interface bus;
and recording the identification chip information, and correspondingly storing the test result and the test data of each tested chip.
Further, the identification chip information includes information such as a lot number, a chip number, a position coordinate, a tape-out factory code, and a test factory code of the tested chip.
Further, the test data specifically includes test data in formats of rawdata, stdf, txt, and the like.
Further, the test data includes at least one screening identification.
Further, the test data includes HardBi and SoftBin.
Optionally, when the background chip information of the chip to be tested is not matched with the identification chip information, the chip information of the chip to be tested in the integrated circuit wafer is recorded incorrectly.
Further, when the background chip information and the identification chip information of the tested chip are not matched, the batch number of the tested chip is wrong; or, the communication error of the universal interface bus interface; or, the position coordinate of the tested chip is set to be wrong.
Compared with the prior art, the method has the following beneficial effects:
the invention provides a method for verifying chip information, which comprises the following steps: step S1: providing an integrated circuit wafer, wherein the integrated circuit wafer comprises a plurality of tested chips, the tested chips are subjected to a plurality of test items, and each tested chip comprises background chip information; step S2: acquiring identification chip information of each tested chip; step S3: comparing the background chip information and the identification chip information of the same tested chip to confirm whether the background chip information and the identification chip information of the tested chip are matched or not; step S4: if the background chip information and the identification chip information of the tested chip are not matched, searching for a mismatch reason, correcting the mismatch reason after the reason is found, and returning to the step S2; or if the background chip information of the tested chip is matched with the identification chip information, recording the test data and the test result of the tested chip. The method of the invention utilizes the chip information to compare and verify in real time on the premise of not influencing the testing efficiency, finds out the chip information error at the first time and finds out the reason of the error, and avoids the situation that the chip information error of the tested chip is later found out, so that the chip which needs to be retested or has unqualified testing result directly flows into the next link, thereby avoiding the loss which can not be compensated; and on the premise of unchanging the testing time, the chip information of the tested chip is checked and recorded in real time to determine whether the chip information is correct or not, so that the chip information traceability of the tested chip is improved.
Drawings
FIG. 1a is a schematic illustration of a map with positional coordinate errors;
FIG. 1b is a schematic illustration of a map with position coordinates set correctly;
fig. 2 is a flowchart illustrating a method for verifying chip information according to an embodiment of the present invention;
FIG. 3 is a diagram of a chip test map of an integrated circuit wafer according to an embodiment of the invention.
Description of reference numerals:
1-an integrated circuit wafer; 10-chip under test.
Detailed Description
As described in the background, for example, when the tested chips pass the multi-station parallel test, before the test starts, the tested chips need to be arranged corresponding to the positions on the probe card and position coordinates are set as required, for example, the test setup schemes of the position arrangement of 16 tested chips include 2 × 8 arrangement, 8 × 2 arrangement, 4 × 4 arrangement, and the like. When a setting error occurs in setting the position coordinates, for example, 2 × 8 arrangement is set to 8 × 2 arrangement, and the actual results of the tested chips and the test results of the tested chips cannot be in one-to-one correspondence. FIG. 1a is a schematic diagram of a map with a wrong position coordinate set, and FIG. 1b is a schematic diagram of a map with a correct position coordinate set. As shown in fig. 1a and 1b, the correct map is a circle of unqualified dies (i.e. a circle of black dies at the edge of the ic wafer) at the outermost circle, and the map with the wrong position coordinate setting is shifted as a whole, so that a circle of unqualified dies (i.e. a circle of black dies at the left edge of the ic wafer) is added at the left edge of the map. Those that cannot be found will flow into the next link, so that the chips under test cannot be traced.
In the prior art, various problems caused by information errors of a tested chip cannot be completely avoided, testing time may be wasted due to testing performed again after the chip is found, and errors which cannot be compensated are caused because the tested chip with unqualified testing result flows into the next link due to misplacement of information records.
The core idea of the invention is to provide a method for verifying chip information, which can verify and record whether the chip information of a tested chip is correct or not in real time on the premise that the testing time of an integrated circuit wafer is not changed, thereby improving the traceability of the chip information.
A method for verifying chip information according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
Fig. 2 is a flowchart illustrating a method for verifying chip information according to this embodiment. As shown in fig. 2, the present embodiment provides a method for verifying chip information, where the method for verifying chip information is a method for verifying chip information of an integrated circuit wafer in a test process.
The method comprises the following steps:
step S1: providing an integrated circuit wafer, wherein the integrated circuit wafer comprises a plurality of tested chips, the tested chips are subjected to a plurality of test items, and each tested chip comprises background chip information;
step S2: acquiring identification chip information of each tested chip;
step S3: comparing the background chip information and the identification chip information of the same tested chip to confirm whether the background chip information and the identification chip information of the tested chip are matched or not;
step S4: if the background chip information and the identification chip information of the tested chip are not matched, searching for a mismatch reason, correcting the mismatch reason after the reason is found, and returning to the step S2; or,
and if the background chip information of the tested chip is matched with the identification chip information, recording the test data and the test result of the tested chip.
A method for verifying chip information according to an embodiment of the present invention is described in detail below with reference to fig. 2 to 3.
First, step S1 is executed to provide an integrated circuit wafer 1, where the integrated circuit wafer 1 includes a plurality of chips 10 under test, the chips 10 under test are subjected to a plurality of test items, and each chip 10 under test includes background chip information.
The information such as the lot number, the chip number, the position coordinates, the flow factory code, and the test factory code of each of the tested chips 10 is converted into ASCII code, and then translated into binary data, and the binary data is used to generate the background chip information of each of the tested chips 10, thereby generating the background chip information database of all the tested chips 10 in the integrated circuit wafer 1. The plurality of test items are, for example, all test items of the chip under test 10.
Fig. 3 is a chip test map of the integrated circuit wafer according to the embodiment. As shown in fig. 3, in the present embodiment, the integrated circuit wafer 1 has 615 tested chips 10 in total, each of the tested chips 10 may include information such as lot number, sheet number, position coordinates, tape-out factory code, and test factory code, for example, the lot number of each of the tested chips 10 is 7ECA 23; the chip number is 1# -25 #; the position coordinates comprise an X coordinate position and a Y coordinate position, the coordinate range of the X coordinate position is 1-28, and the coordinate range of the Y coordinate position is 1-25. The tested chip 10 passes through a double-station test, the two stations are arranged up and down, the coordinate of the first tested chip 10 is (X ═ 9, Y ═ 2), and according to the optimal walking method designed during the test of the tested chip 10, the test coordinates of the tested chip 10 are calculated to be (9, 2), (10, 2), (11, 1), (11, 2), (12, 1), (12, 2) … … (17, 1), (17, 2), (18, 2), (19, 2), (22, 4), (21, 3), (21, 4), (20, 3), (20, 4) … … in sequence. The stream factory code is for example SC and the test factory code is for example TC. According to the information, a program is written, numbers, letters, symbols and the like in the batch number, the chip number and the position coordinate are all converted into ASCII codes, the ASCII codes are translated into binary data, background chip information of each tested chip 10 is generated, and accordingly background chip information databases of all the tested chips 10 in the integrated circuit wafer 1 are generated, and the background chip information databases comprise chip information of each tested chip 10 of the integrated circuit wafer 1.
As shown in the following table, the binary data in each row represents background chip information of one chip to be tested, the first 48 bits of binary data in each row represent a lot number of the chip to be tested, the 48 th to 56 th bits of binary data represent a chip number of the chip to be tested, the 57 th to 72 th bits of binary data represent position coordinates of the chip to be tested, the 73 th to 88 th bits of binary data represent a tape-out code of the chip to be tested, and the 89 th to 104 th bits of binary data represent a test code of the chip to be tested, where the table is a background chip information database of all chips to be tested in the integrated circuit wafer 1 of the present embodiment.
Then, step S2 is executed to obtain the identification chip information of each of the chips under test.
In particular, the method comprises the following steps of,
first, the identification chip information of each of the chips under test is identified by reading Optical Characters (OCR) from an integrated circuit probe station (Prober) through a General-Purpose Interface Bus (GPIB).
The identification chip information comprises information such as a batch number, a chip number and a position coordinate of the tested chip, a tape-out factory code, a test factory code and the like.
And then, recording the identification chip information, and correspondingly storing the test result and the test data of each tested chip, wherein the test data specifically comprises the test data in the formats of rawdata, stdf, txt and the like. The test data includes at least one screening identifier, such as HardBin and SoftBin, wherein HardBin is used for identifying that the tested chip is a chip falling position when the corresponding test item is qualified, SoftBin is also used for identifying screening of the tested chip, the screening is subdivided after HardBin classification, the screening is stored in a table as a structure only for being viewed by a client, and the result includes related expressions for the test item. The test results include pass (pass) and fail (fail).
As shown in fig. 3, the black tested chips 10 in the integrated circuit wafer are the chips that fail the test items, and the white tested chips 10 that are not displayed in the integrated circuit wafer are the chips that pass the test items.
Next, step S3 is executed to compare the background chip information and the identification chip information of the same chip under test 10 to determine whether the background chip information and the identification chip information of the chip under test match. Specifically, the identification chip information of each of the chips 10 to be tested is compared with the corresponding background chip information to determine whether the background chip information and the identification chip information of the chip to be tested are matched.
Step S4 is then executed: if the background chip information and the identification chip information of the tested chip are not matched, searching for a mismatch reason, correcting the mismatch reason after the reason is found, and returning to the step S2; or if the background chip information is matched with the identification chip information, recording the test data and the test result of the tested chip.
In particular, the method comprises the following steps of,
when the identification chip information of each of the tested chips 10 matches the corresponding background chip information (i.e., the identification chip information of each of the tested chips 10 is identical to the corresponding background chip information), it indicates that the chip information record of each of the tested chips 10 in the integrated circuit wafer 1 is correct, and thus the test for verifying the chip information is finished.
When the identification chip information of each of the chips 10 under test is not matched with the corresponding background chip information (the identification chip information of each of the chips 10 under test is not consistent with the corresponding background chip information), it indicates that a chip information recording error of the chip 10 under test (for example, a lot number error of the chip 10 under test, or a GPIB communication error, or a position coordinate setting error, etc.) needs to be temporarily stopped, the test is performed to check for finding the cause of the error, after finding the cause of the error, the correction is performed in time, and after correcting the error, the step S2 is returned to re-acquire the identification chip information of each of the chips under test, and the background chip information and the identification chip information of the same chip under test are compared to confirm whether the background chip information and the identification chip information of the chip under test are matched, if the background chip information and the identification chip information are matched, the test is finished; if the background chip information and the identification chip information are not matched, continuously checking to find the reason causing the error, correcting in time after finding the reason causing the error, returning to the step S2 after correcting the error until the background chip information and the identification chip information are matched, recording the test data and the test result of the tested chip, and finishing the test of chip information verification. According to the method, on the premise that the testing efficiency is not influenced, the chip information is compared and verified in real time, the chip information error is found at the first time, the reason of the error is found, and the situation that the chip information error of the tested chip is later found, the chip which needs to be retested or is unqualified in the testing result directly flows into the next link is avoided, so that the loss which cannot be made up is avoided; and on the premise of unchanging the testing time, the chip information of the tested chip is checked and recorded in real time to determine whether the chip information is correct or not, so that the chip information traceability of the tested chip is improved.
In summary, the present invention provides a method for verifying chip information, which includes the following steps: step S1: providing an integrated circuit wafer, wherein the integrated circuit wafer comprises a plurality of tested chips, the tested chips are subjected to a plurality of test items, and each tested chip comprises background chip information; step S2: acquiring identification chip information of each tested chip; step S3: comparing the background chip information and the identification chip information of the same tested chip to confirm whether the background chip information and the identification chip information of the tested chip are matched or not; step S4: if the background chip information and the identification chip information of the tested chip are not matched, searching for a mismatch reason, correcting the mismatch reason after the reason is found, and returning to the step S2; or if the background chip information of the tested chip is matched with the identification chip information, recording the test data and the test result of the tested chip. The method of the invention utilizes the chip information to compare and verify in real time on the premise of not influencing the testing efficiency, finds out the chip information error at the first time and finds out the reason of the error, and avoids the situation that the chip information error of the tested chip is later found out, so that the chip which needs to be retested or has unqualified testing result directly flows into the next link, thereby avoiding the loss which can not be compensated; and on the premise of unchanging the testing time, the chip information of the tested chip is checked and recorded in real time to determine whether the chip information is correct or not, so that the chip information traceability of the tested chip is improved.
In addition, unless otherwise specified or indicated, the description of the terms "first" and "second" in the specification is only used for distinguishing various components, elements, steps and the like in the specification, and is not used for representing logical relationships or sequential relationships among the various components, elements, steps and the like. It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. A method for verifying chip information is characterized by comprising the following steps:
step S1: providing an integrated circuit wafer, wherein the integrated circuit wafer comprises a plurality of tested chips, the tested chips are subjected to a plurality of test items, and each tested chip comprises background chip information;
step S2: acquiring identification chip information of each tested chip;
step S3: comparing the background chip information and the identification chip information of the same tested chip to confirm whether the background chip information and the identification chip information of the tested chip are matched or not;
step S4: if the background chip information and the identification chip information of the tested chip are not matched, searching for a mismatch reason, correcting the mismatch reason after the reason is found, and returning to the step S2; or if the background chip information of the tested chip is matched with the identification chip information, recording the test data and the test result of the tested chip.
2. The method of claim 1, wherein the background chip information of each of the chips under test is binary data.
3. The method of claim 2, wherein the lot number, the chip number, the position coordinates, the tape carrier code, and the tester code of each of the chips under test are first converted into ASCII code, and then binary translated to obtain the background chip information.
4. The method of claim 1, wherein step S2 includes:
reading back the identification chip information of each tested chip by optical characters from the integrated circuit probe station through a universal interface bus;
and recording the identification chip information, and correspondingly storing the test result and the test data of each tested chip.
5. The method of claim 4, wherein the identification chip information includes lot number, chip number, and location coordinates of the chip under test, tape-out code, and test-run code.
6. The method of claim 4, wherein the test data specifically includes test data in the format of rawdata, stdf, txt, etc.
7. The method of claim 4, wherein the test data includes at least one screening identification.
8. The method of claim 7, wherein the test data comprises HardBi and SoftBin.
9. The method of claim 8, wherein the recording of the chip information of the dut in the ic wafer is incorrect when the background chip information and the identification chip information of the dut do not match.
10. The method of claim 9, wherein when the background chip information and the identification chip information of the chip under test do not match, the lot number of the chip under test is incorrect; or, the communication error of the universal interface bus interface; or, the position coordinate of the tested chip is set to be wrong.
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