CN112260239B

CN112260239B - Chip compact relay protection device

Info

Publication number: CN112260239B
Application number: CN202011082057.2A
Authority: CN
Inventors: 李肖博; 李鹏; 习伟; 姚浩; 于杨; 蔡田田; 陈军健; 陶伟; 邓清唐
Original assignee: Southern Power Grid Digital Grid Research Institute Co Ltd
Current assignee: Southern Power Grid Digital Grid Research Institute Co Ltd
Priority date: 2020-10-12
Filing date: 2020-10-12
Publication date: 2023-06-27
Anticipated expiration: 2040-10-12
Also published as: CN112260239A

Abstract

The application relates to a chip compact relay protection device, which comprises a CPU plug-in unit, a communication management plug-in unit, an opening plug-in unit and an interaction panel, wherein the CPU plug-in unit is connected with the communication management plug-in unit, the opening plug-in unit and the opening plug-in unit, and the communication management plug-in unit is connected with the interaction panel; the CPU plug-in is interacted with external equipment data through the plug-in and the plug-in, display information is generated according to the acquired data, and the display information is sent to the interaction panel for display through the communication management plug-in. The application can reduce the use of the board card, so that the structure is more compact, the whole volume can be reduced, and the occupied space is reduced.

Description

Chip compact relay protection device

Technical Field

The application relates to the technical field of power systems, in particular to a chip compact relay protection device.

Background

The relay protection device is a common device in the power system, the working state of the relay protection device directly affects the whole power system, and the relay protection device plays an important role in protecting the safe and stable operation of the power system.

At present, relay protection devices manufactured by major relay protection factories at home and abroad are conventional relay protection devices or digital relay protection devices, and generally have two forms: a plug-in box form of multiple boards is disclosed, different boards are communicated through buses, communication protocols among boards are various, nonstandard and complex, communication speed is low, each device is provided with 5-8 boards, each board is provided with at least one CPU chip, and the number of CPU chips of a single device is more than 5, so that the size is large. The other is represented by a protection device produced by SEL in the united states, and the multiprocessor is arranged on a board card by adopting a large-plate design, but the protection device also has the problem of large volume and occupies more space.

Disclosure of Invention

In view of the above, it is necessary to provide a compact relay protection device with a reduced size.

The chip compact relay protection device comprises a CPU plug-in unit, a communication management plug-in unit, an opening plug-in unit and an interactive panel, wherein the CPU plug-in unit is connected with the communication management plug-in unit, the opening plug-in unit and the opening plug-in unit, and the communication management plug-in unit is connected with the interactive panel;

and the CPU plug-in is interacted with external equipment data through the opening plug-in and the opening plug-in, generates display information according to the acquired data and sends the display information to the interaction panel for display through the communication management plug-in.

In one embodiment, the CPU plug-in comprises a dual-core chip and an external memory, wherein the dual-core chip comprises a master core, a slave core, a front-end data processing module, an internal memory and a memory management module;

the master core is connected with the opening plug-in unit and the opening plug-in unit, the slave core is connected with the communication management plug-in unit, the master core and the front end data processing module are connected with the internal memory, the master core, the slave core and the front end data processing module are all connected with the storage management module, and the storage management module is connected with the external memory.

In one embodiment, the front-end data processing module receives analog sampling data sent by an external device and sends the analog sampling data to the internal memory, and the master kernel reads the analog sampling data from the internal memory to perform logic operation.

In one embodiment, the CPU card further includes a first PHY chip and an optical fiber ethernet port, where the first PHY chip is connected to the front-end data processing module and the optical fiber ethernet port, respectively.

In one embodiment, the CPU card further includes a light difference channel, and the front-end data processing module is connected to the light difference channel.

In one embodiment, the communication management plug-in includes a single core chip and an FPGA, the single core chip connecting the FPGA, the CPU plug-in, and the interactive panel.

In one embodiment, the communication management plug-in further includes a second PHY chip and an electrical port ethernet port, where the second PHY chip is connected to the FPGA and the electrical port ethernet port, respectively.

In one embodiment, the communication management plug-in further comprises a time synchronization interface and/or a printing serial port connected with the FPGA.

In one embodiment, the opening plug-in includes a plurality of relays that connect the CPU plug-in and the external device.

In one embodiment, the above-mentioned chip-based compact relay protection device further includes a power plug-in unit, where the power plug-in unit is connected to the CPU plug-in unit, the communication management plug-in unit, the switch-in plug-in unit, the switch-out plug-in unit, and the interactive panel.

In the chip compact relay protection device, the CPU plug-in is interacted with external equipment through the plug-in and the plug-in, so that data can be acquired, display information is generated according to the acquired data, and the communication management plug-in sends the display information to the interaction panel for display so as to be convenient for a user to check; the CPU plug-in realizes the functions of data interaction and processing, reduces the use of the board card, and has more compact structure, thereby reducing the whole volume and the occupied space.

Drawings

In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a schematic diagram of a chip-based compact relay protection device in one embodiment;

FIG. 2 is a schematic diagram of the internal architecture of a CPU package in one embodiment;

FIG. 3 is a schematic diagram showing the internal structure of a CPU card according to another embodiment;

FIG. 4 is a schematic diagram of the power circuit of the CPU package in one embodiment;

FIG. 5 is a schematic diagram of a clock design of a CPU card in one embodiment;

FIG. 6 is a block diagram of a communication management plug-in one embodiment;

FIG. 7 (a) is a schematic diagram of a portion of a circuit of an add-in one embodiment;

FIG. 7 (b) is a schematic diagram of another portion of the circuit schematic of the add-in card of one embodiment;

fig. 7 (c) is a schematic view of a terminal corresponding to fig. 7 (a) and 7 (b);

FIG. 8 (a) is a schematic diagram of a portion of a circuit of an embodiment of the opening insert;

FIG. 8 (b) is a schematic diagram of another portion of a circuit of the opening insert in one embodiment;

fig. 8 (c) is a schematic view of a terminal corresponding to fig. 8 (a) and 8 (b);

FIG. 9 is a schematic circuit diagram of a power supply package in one embodiment;

FIG. 10 is a schematic diagram of the appearance of a chip-based compact relay protection device in one embodiment;

fig. 11 is a circuit protection device hardware configuration diagram of a chip-based compact relay protection device in one embodiment.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments should be understood as "electrical connection", "communication connection", and the like if there is transmission of electrical signals or data between objects to be connected.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.

Referring to fig. 1, in one embodiment, a chip-based compact relay protection device is provided, including a CPU plug-in 110, a communication management plug-in 120, an in plug-out 130, an out plug-in 140, and an interactive panel 150, where the CPU plug-in 110 is connected to the communication management plug-in 120, the in plug-out 130, and the out plug-in 140, and the communication management plug-in 120 is connected to the interactive panel 150.

The CPU plug-in 110 interacts with external device data through the add-in 130 and the add-out 140, generates display information according to the acquired data, and sends the display information to the interaction panel 150 for display through the communication management plug-in 120.

The external device may be a field device provided with a chip-type compact relay protection device, and may provide data required for relay protection and receive information output by the CPU plug-in 110. The CPU plug-in 110 is a core of the chip compact relay protection device, and can realize a protection function, for example, the CPU plug-in can perform processing analysis according to the acquired data, determine whether tripping is required according to an analysis result, or perform processing analysis according to the acquired data, and generate display information which needs to be notified to a user according to the analysis result; the data acquired by the CPU plug-in 110 may be data output by an external device received through the on plug-in 130. The communication management plug-in 120 is a plug-in that can implement a communication management function, for example, by being connected to the CPU plug-in 110 and the interactive panel 150, and sending display information sent by the CPU plug-in 110 to the interactive panel 150; the interactive panel 150 is a device that can display information, and is displayed for a user to view after receiving the display information.

In particular, the CPU card 110, the communication management card 120, the add-in card 130, the add-out card 140, and the interactive panel 150 may be integrated on the back plane of one chip, i.e., integrally chipped.

In the above-mentioned chip-based compact relay protection device, the CPU plug-in 110 interacts with external equipment data through the in-plug-in 130 and the out-plug-in 140, so that data can be obtained, display information is generated according to the obtained data, and the communication management plug-in 120 sends the display information to the interaction panel 150 for display, so that a user can view the display information; the CPU plug-in 110 realizes the functions of data interaction and processing, reduces the use of a board card, and ensures that the structure is more compact, thereby reducing the whole volume and the occupied space.

In one embodiment, CPU package 110 includes a dual core chip and an external memory, the dual core chip including a master core, a slave core, a front end data processing module, an internal memory, and a memory management module. The master kernel is connected with the switch-in plug-in 130 and the switch-out plug-in 140, the slave kernel is connected with the communication management plug-in 120, the master kernel and the front end data processing module are connected with the internal memory, the master kernel, the slave kernel and the front end data processing module are all connected with the storage management module, and the storage management module is connected with the external memory.

The front-end data processing module can be communicated with an external device to collect data and send the data to the internal memory, so that data collection is realized; specifically, the front-end data processing module can write data into the internal memory, and the main kernel can read data from the internal memory for processing, so that data processing is realized. Specifically, the main kernel, the auxiliary kernel and the front-end data processing module can exchange data through an external memory connected with the storage management module, so that internal data interaction is realized. Specifically, the master kernel, the slave kernel and the front-end data processing module can read and write data from the external memory through the memory management module, so that the master kernel, the slave kernel and the front-end data processing module can exchange data through the external memory. Through adopting dual-core chip, realize the CPU plug-in components of dual-core structure, powerful can realize data acquisition, processing and mutual at a CPU plug-in components, with multiple functions integration in a plug-in components, realize miniaturized, high integrated design scheme, reduce the use of integrated circuit board, overall structure is compacter to reduce the volume.

In one embodiment, the front-end data processing module receives analog sampling data sent by the external device and sends the analog sampling data to the internal memory, and the main kernel reads the analog sampling data from the internal memory to perform logic operation.

Specifically, the front-end data processing module may receive a data packet sent by an external device through a network interface, process the data packet to obtain analog sampling data, and directly store the analog sampling data in an internal memory, for example, the processing process of the data includes SV decoding, storm suppression, low-pass filtering, message distribution and interpolation synchronization; the main kernel acquires analog sampling data from the internal memory and carries out logic operation in the secondary cache, wherein the logic operation comprises processing of the analog sampling data in relay protection. Through the on-chip interaction with the front-end data processing module, the data sampling, calculation and interaction functions completed by a plurality of boards of the traditional relay protection device are integrated in a chip, the integration level is high, and the use quantity of the boards is reduced.

Specifically, the dual-core chip uses a master multi-slave mode, the master core grasps the highest authority, and the slave core and the front-end data processing module are supervised and controlled. The master CORE and the slave CORE can be ARM COREs of hardware, as shown in fig. 2, the master CORE1 and the slave CORE2 adopt ARM Cortex-A9 COREs, the master CORE1 manages shared resources, the slave CORE2 only has use rights on the shared resources, only one party of configuration and management of the shared resources is guaranteed, and data interaction management of the device is effectively guaranteed. In general, physically dual cores share a 4GB address space, with each core having access to all of the address space, if one core software fails, it may cause another core to run abnormally. Thus, for security reasons, an additional protection mechanism is added, allocating different address spaces to the two COREs, limiting the master CORE1 and the slave CORE2 to access only the address spaces belonging to themselves by setting an MMU (Memory Management Unit memory management unit) inside the COREs. Meanwhile, by modifying the CORE code of the operating system of the slave CORE2, the reset of the CORE code is ensured not to influence the operation of the master CORE1, and even if the slave CORE2 fails, the operation of a protection function is not influenced, so that the requirement of high reliability is met. The main kernel realizes protection logic operation and mainly comprises GOOSE analysis, a protection algorithm, GOOSE opening, tripping logic, GOOSE opening and the like; the slave CORE2 mainly realizes device management and device communication and mainly comprises management communication applications such as MMS (Microsoft Media Server Protocol Microsoft media service protocol) message, wave recording, communication, management and the like. The key data such as the protection fixed value, the soft pressing plate data, the analog sampling value, the protection starting and alarming sign and the like are transmitted through the internal memory, and other non-key data are transmitted and interacted through the external memory, so that the data transmission of a split channel and a split path is realized, and the priority and the independence of the key data transmission are ensured.

As shown in fig. 2, the front-end data processing module may be an FPGA (Field Programmable Gate Array field programmable gate array) and the internal memory may be RAM (Random Access Memory random access memory). The external memory 200 may be a DDR (Double Data Rate) memory. The CPU plug-in may also include FLASH for storing program files of the cores and FPGA, EEPROM (Electrically Erasable Programmable read only memory live erasable programmable read only memory), DDR shared by 2 cores. In addition, an RTC (real time clock) may be added from the CORE 2.

In one embodiment, referring to fig. 3, the cpu card 110 further includes a first PHY chip and a fiber ethernet port, where the first PHY chip is connected to the front-end data processing module and the fiber ethernet port, respectively.

Specifically, the front-end data processing module is an FPGA, that is, the FPGA is connected to the optical fiber ethernet port through the first PHY chip. The CPU plug-in 110 extends the optical fiber ethernet interface through the first PHY chip, so as to implement multiple SV/GOOSE packet transmission, and communication is convenient.

Specifically, the optical fiber Ethernet port can comprise 2-8 paths of SV/GOOSE integrated interfaces, the SV/GOOSE integrated interfaces can transmit SV messages and GOOSE messages, and the convenience of network communication can be improved by adopting the external multipath SV/GOOSE integrated interfaces.

In one embodiment, the CPU card 110 further includes a light difference channel, and the front-end data processing module is connected to the light difference channel.

Specifically, the front-end data processing module is an FPGA, i.e., the FPGA is connected to the light difference channel. HDLC (High-Level Data Link Control) function is realized in the FPGA, LVPECL (Low Voltage PosiTIve Emitter-coupling Logic low-voltage positive emitter coupling Logic) level is output through an external level conversion circuit, and a 2M optical module is driven, so that light difference protection of a line can be realized.

The variety of power supplies required by the CPU card 110 is very large, as shown in table 1 below.

TABLE 1

The PS (Processing System processing system) portion, PL (Programmable Logic programmable logic) portion, and hardware transceiver GTX of the CPU plug-in 110 are independently powered, and after aggregation, mainly require four voltages of 1.0V, 1.8V, 1.5V, and 3.3V, and the analog power supply is obtained after filtering using a digital power supply. The input power to the CPU plug-in 110 is 5V and is converted to the required voltage levels using a DC/DC chip or LDO (Low Dropout Regulator low dropout linear regulator), the topology of the power circuit is shown in fig. 4. The 3.3V, 1.8V, 1.5V and 1.0V uniformly adopt a DC/DC scheme, and the 1.2V is obtained by using 3.3V through LDO conversion, and the maximum output current is 1A. The DC/DC can be externally connected with a slow start capacitor, and different voltage power-on time sequences can be controlled by adjusting the size of the capacitor.

CPU card 110 requires a variety of clocks: PS clock, PHY clock, transceiver reference clock, and HDLC precision clock, as shown in table 2 below.

TABLE 2

The clock design is shown in fig. 5, and 50MHz active crystal oscillator is used for PS, PL and PHY respectively after passing through the clock driver. The 25MHz active crystal oscillator outputs 125M LVDS differential clocks after passing through the frequency doubling chip and is used as a reference clock of a hardware transceiver (GTX) to realize optical fiber Ethernet. The FPGA cannot realize accurate fractional frequency division, and 65.536MHz active crystal oscillator is externally provided for realizing HDLC protocol.

In one embodiment, communication management plug-in 120 includes a single core chip and an FPGA, the single core chip connecting the FPGA, CPU plug-in 110, and interactive panel 150.

The single-core chip is a chip with a core, and specifically, the single-core chip can be a ZYNQ chip; the communication management plug-in 120 uses a single core chip to realize the functions of time synchronization and communication management, and uses an FPGA to perform data processing and then communicate with the outside; the single-core chip can receive the display information sent by the CPU plug-in 110 and send the display information to the interactive panel 150 for display, and has a simple structure.

In one embodiment, referring to fig. 6, the communication management plug-in 120 further includes a second PHY chip and an electrical port ethernet port. The second PHY chip is respectively connected with the FPGA and the electric port Ethernet port, namely, the FPGA is connected with the electric port Ethernet port through the second PHY chip. And the second PHY chip is adopted to expand the Ethernet port of the power grid, so that multipath communication is realized, and the communication is convenient. Specifically, the electrical port ethernet ports include a 3-way electrical port ethernet port.

In one embodiment, the communication management plug-in 120 further includes a time tick interface and/or a print serial interface to connect to the FPGA. The time setting module of the FPGA realizes a time setting function and is convenient for time setting by connecting a time setting interface; by adopting the printing serial port, the printing device is convenient to connect with printing equipment for printing. By providing the time setting interface and the printing serial port, the functions are various.

For example, as shown in fig. 6, the communication management module 120 includes a time tick interface and a print serial port. In fig. 6, a Master represents a single core chip, a Master plug-in is a communication management plug-in, and the Master plug-in expands a 3-channel electric port ethernet port for an MMS network through a second PHY chip, and simultaneously, the Master plug-in is used for an external 1-channel time-setting interface and an external 1-channel printing serial port.

In one embodiment, the switch-in plug-in 130 includes a switch-in module that provides 28-way switching value inputs, the switch-in module connecting the CPU plug-in 110 and external devices. For example, as shown in fig. 7 (a), 7 (b) and 7 (c), a multi-way input is available by using a multi-way switching value input.

In one embodiment, the break-out plug-in 140 includes a plurality of relays that connect the CPU plug-in 110 to external devices. Specifically, one relay corresponds to one path of switching value output, and the number of the relays can be 16, so that 16 paths of switching value output are corresponding; the relay is closed and the CPU card 110 may output data, and in particular, whether the relay is closed may be controlled by the CPU card 110. For example, as shown in fig. 8 (a), 8 (b) and 8 (c), the multiplexing output is realized by multiplexing the switching value outputs.

In one embodiment, the relay protection device further includes a power plug-in, where the power plug-in is connected to the CPU plug-in 110, the communication management plug-in 120, the switch-in 130, the switch-out plug-in 140, and the interactive panel 150, and is configured to supply power to the CPU plug-in 110, the communication management plug-in 120, the switch-in plug-in 130, the switch-out plug-in 140, and the interactive panel 150. Specifically, the chip-type compact relay protection device may further include a back board, where the CPU plug-in 110, the communication management plug-in 120, the in-out plug-in 130, and the out-out plug-in 140 are disposed, and the power plug-in connects the CPU plug-in 110, the communication management plug-in 120, the in-out plug-in 130, the out-out plug-in 140, and the interactive panel 150 through the back board.

For example, as shown in FIG. 9, the power plug-in provides a 4-way alert on signal. The input of the power plug-in is rated voltage UN: AC/DC 110V/220V, input voltage range: 20% un; the output is rated voltage: 5V, 24V, signal: group 2.

In one embodiment, the interactive panel 150 configures 320×240 resolution liquid crystal, ethernet debug port, operation keys, and indicator lights; the interactive panel 150 supports at most 24 red-green double-color indicator lamps, the actual use number and definition CAN be customized according to the device type, and the interactive panel communicates with the communication management plug-in 120 through the CAN network, and receives and displays the display information of the communication management plug-in.

Specifically, the appearance of the chip-based compact relay protection device is shown in fig. 10, the hardware configuration and the network port function allocation are shown in fig. 11, and the plug-in list is shown in table 3 below.

TABLE 3 Table 3

In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. The chip compact relay protection device is characterized by comprising a CPU plug-in unit, a communication management plug-in unit, an opening plug-in unit and an interactive panel, wherein the CPU plug-in unit is connected with the communication management plug-in unit, the opening plug-in unit and the opening plug-in unit, and the communication management plug-in unit is connected with the interactive panel;

the CPU plug-in is interacted with external equipment data through the opening plug-in and the opening plug-in, display information is generated according to the acquired data, and the display information is sent to the interaction panel for display through the communication management plug-in;

the CPU plug-in unit comprises a dual-core chip and an external memory, wherein the dual-core chip comprises a master core, a slave core, a front-end data processing module, an internal memory and a memory management module;

2. The chipped compact relay protection device of claim 1, wherein the CPU plug-in, the communication management plug-in, the ingress plug-in, the egress plug-in, and the interaction panel are integrated into a backplane of a chip.

3. The on-chip compact relay protection device according to claim 1, wherein the front-end data processing module receives analog sampling data sent by an external device and sends the analog sampling data to the internal memory, and the main core reads the analog sampling data from the internal memory to perform a logic operation.

4. The chipped compact relay protection device of claim 1, wherein the CPU plug-in further comprises a first PHY chip and an optical fiber ethernet port, the first PHY chip being connected to the front-end data processing module and the optical fiber ethernet port, respectively.

5. The on-chip compact relay protection device of claim 4, wherein the CPU package further comprises a light differential channel, the front-end data processing module being coupled to the light differential channel.

6. The chipped compact relay protection device of claim 1, wherein the communication management plug-in includes a single core chip and an FPGA, the single core chip connecting the FPGA, the CPU plug-in, and the interactive panel.

7. The chipped compact relay protection device of claim 6, wherein the communication management plug-in further comprises a second PHY chip and an electrical port ethernet port, the second PHY chip being connected to the FPGA and the electrical port ethernet port, respectively.

8. The on-chip compact relay protection device of claim 7, wherein the communication management plug-in further comprises a time tick interface and/or a print serial port to connect the FPGA.

9. The on-chip compact relay protection device of claim 1, wherein the open plug-in includes a plurality of relays that connect the CPU plug-in and the external device.

10. The on-chip compact relay protection device of claim 1, further comprising a power plug-in that connects the CPU plug-in, the communication management plug-in, the ingress plug-in, the egress plug-in, and the interactive panel.