CN112259605A - Heterojunction semiconductor device resistant to instantaneous current impact - Google Patents
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- CN112259605A CN112259605A CN202011143648.6A CN202011143648A CN112259605A CN 112259605 A CN112259605 A CN 112259605A CN 202011143648 A CN202011143648 A CN 202011143648A CN 112259605 A CN112259605 A CN 112259605A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 119
- 230000001052 transient effect Effects 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims description 107
- 239000002184 metal Substances 0.000 claims description 107
- 239000000758 substrate Substances 0.000 claims description 49
- 239000003989 dielectric material Substances 0.000 claims description 3
- 238000010521 absorption reaction Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 230000001939 inductive effect Effects 0.000 description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 229910002601 GaN Inorganic materials 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011068 loading method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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Abstract
The invention relates to a heterojunction semiconductor device resistant to transient current surge, comprising: the structure can improve the transient current impact resistance of the device, and plays a certain role in protecting the device when the device bears transient large current.
Description
Technical Field
The invention belongs to the field of power electronic systems and semiconductor devices, and particularly relates to a heterojunction semiconductor device with instantaneous current impact resistance.
Background
Semiconductor materials have been developed from first-generation semiconductors such as silicon (Si) and germanium (Ge) and second-generation semiconductors such as gallium arsenide (GaAs) and indium antimonide (InSb), and third-generation semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) are now being developed and applied in large quantities. The third generation semiconductor is also called wide bandgap semiconductor, and the biggest advantage of the third generation semiconductor is that the bandgap is larger than that of the first two generations semiconductor, which brings many excellent electrical characteristics for the third generation semiconductor device. Among wide band gap semiconductor devices, heterojunction semiconductor devices have outstanding electrical characteristics, and for gallium nitride devices, besides large band gap, the heterojunction semiconductor devices also have the advantages of high thermal conductivity, high temperature resistance, radiation resistance, acid and alkali resistance, high strength, high hardness and the like, and have huge application prospects in the aspects of high-temperature high-power electronic devices, high-frequency devices, photodetectors and the like.
The device can encounter the situation of instantaneous increase of current in use, which brings great test to the reliability of the device, and at the moment, the device is easy to be damaged and can not work normally. In a conventional heterojunction device, which has a weak ability to withstand transient current surge, the device structure is as shown in fig. 1, and includes: the semiconductor device comprises a substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a grid electrode, an electronic channel layer formed by the second semiconductor layer and the third semiconductor layer in a contact mode, a first metal electrode and a third metal electrode on the third semiconductor layer, a second metal electrode on the grid electrode and a fourth metal electrode below the substrate.
When the instantaneous impact current is too large, the breakdown of the device can be caused, and the device cannot work normally. The existing methods for solving this problem are: the transient current surge resistance of the device is improved by connecting a branch circuit (such as a diode and the like) outside the device in parallel to provide a current surge path or reduce surge voltage. However, the integration level is low, the external parasitic inductance is large, and the effect of improving the transient current impact resistance of the device is not ideal. Therefore, it is necessary to improve the conventional heterojunction device by using a more effective structure and method under the premise of considering parasitic inductance and integration level, and it is an important work in research to improve the transient current impact resistance of the heterojunction semiconductor device. The invention designs the heterojunction semiconductor device resistant to instantaneous current impact, and improves the stability of the device.
Disclosure of Invention
The technical problem is as follows: the present invention is directed to the above-mentioned problems and provides a heterojunction semiconductor device that is resistant to transient current surges. The heterojunction semiconductor device has parasitic inductance in application, and is easy to cause instantaneous current impact on the device, thereby bringing reliability problem to the device.
The technical scheme is as follows: the technical scheme adopted by the invention is as follows:
a heterojunction semiconductor device resistant to transient current surge of the present invention includes: the semiconductor device comprises a substrate, wherein a substrate resistor area is arranged in the substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor area are sequentially arranged above the substrate, the second semiconductor layer is in contact with the third semiconductor layer to form an electronic channel, a first edge dielectric area, a first middle dielectric area, an edge metal area, a middle metal area and a second edge dielectric area are arranged above the substrate resistor area and are positioned on the edge metal area, a second middle dielectric area is positioned on the middle metal area, the first edge dielectric area is positioned beside the second edge dielectric area and the edge metal area, the first middle dielectric area is positioned beside the second middle dielectric area and the middle metal area, a first metal electrode and a third metal electrode are respectively arranged on two edges of the third semiconductor layer, and the third metal electrode covers the first edge dielectric area, the first middle dielectric area, the second edge dielectric area and the second middle dielectric area; the fourth semiconductor region is positioned between the first metal electrode and the third metal electrode, the second metal electrode is arranged on the fourth semiconductor region, the fourth metal electrode is arranged below the substrate and the substrate resistance region, and the substrate resistance region forms a resistance region with set resistivity through doping.
The second edge dielectric region and the second middle dielectric region are high dielectric constant regions, the upper parts of the second edge dielectric region and the second middle dielectric region are in direct contact with the third metal electrode, and the lower parts of the second edge dielectric region and the second middle dielectric region are in direct contact with the edge metal region and the middle metal region.
The lower parts of the edge metal region and the middle metal region are in direct contact with the substrate resistance region, and the sides of the edge metal region and the middle metal region are in direct contact with the first edge dielectric region and the first middle dielectric region.
The first edge dielectric region and the first middle dielectric region are low dielectric constant regions and are positioned between the edge metal region, the middle metal region and the first semiconductor layer, and are also positioned between the second edge dielectric region, the second middle dielectric region and the first semiconductor layer, the second semiconductor layer and the third semiconductor layer, so that the edge metal region, the middle metal region and the first semiconductor layer are isolated.
The device structures between the third metal electrode and the substrate resistance area are alternately distributed in the depth direction according to the sequence of the second edge dielectric area, the first middle dielectric area and the second middle dielectric area.
The first side dielectric area, the first middle dielectric area, the second side dielectric area and the second middle dielectric area adopt dielectrics with different dielectric constants.
Has the advantages that: compared with the prior device, the invention has the following advantages:
compared with the first two generations of semiconductor devices, the wide bandgap semiconductor device has the main electrical characteristic of stronger high voltage resistance. The heterojunction semiconductor device has the advantages that due to different principles of the generation of the conductive channel, the electron mobility in the conductive channel of the heterojunction semiconductor device is higher, and the heterojunction semiconductor device can bear larger current. The principle of electron channel generation in a heterojunction semiconductor device is: the second semiconductor layer in the device is in contact with the third semiconductor layer, and the polarization effect of the two semiconductor layers generates a two-dimensional electron gas channel, so that the electron mobility is higher. The invention designs a current absorbing structure in the device, and the structure is positioned between the third metal electrode and the fourth metal electrode. When the heterojunction semiconductor device is used, the first metal electrode and the fourth metal electrode are in a short circuit state through external connection of the device without changing the internal structure of the device. Thus, in use, the device may be equivalent to forming a current dissipation branch between the third metal electrode and the first metal electrode. When the device works normally, current flows in an electron channel below the first metal electrode and the third metal electrode. When the device is turned off, instantaneous high-frequency oscillation current is generated, at the moment, due to the fact that a plurality of parallel current absorption structures are added, namely a device internal capacitor and a substrate resistance area are formed by the third metal electrode, the second medium area and the metal area, and the high-frequency current is absorbed and dissipated through the capacitor formed by the third metal electrode, the second medium area and the metal area. Therefore, the electron channel is no longer subjected to the impact of a transient large current, and is protected.
(1) The current absorption structure is integrated in the device, so that external parasitic inductance is reduced, and adverse effects of the device caused by the parasitic inductance in application are reduced. For example, under a non-clamped inductive load switch (UIS), the external parasitic capacitance of the device is reduced, so that the instantaneous current impact suffered by the device is reduced, the device is protected, and the voltage withstanding capability of the device is improved.
(2) The device is internally integrated in a longitudinal integration mode, the traditional integration mode is in a transverse integration mode in the device, and the heat dissipation problem caused by the transverse integration often has adverse effect on an electronic channel of the device. The current absorption structure is longitudinally integrated, and the resistance area is arranged on the substrate, so that the device can dissipate heat quickly and has small influence on a channel.
(3) The first dielectric region and the second dielectric region in the device structure respectively use dielectrics with different dielectric constants. The first dielectric region uses a low dielectric constant to isolate the metal region from the first semiconductor layer and isolate the second dielectric region from the first, second and third semiconductor layers, and the second dielectric region uses a high dielectric constant to improve the current absorption capability, so that the device can dissipate larger instantaneous current and improve the instantaneous current impact resistance capability of the device.
(4) When the device is impacted by instantaneous current, a large amount of energy is dissipated by the current absorption branch circuit between the third metal electrode and the first metal electrode, and the device breakdown caused by the current flowing from the two-dimensional electron gas channel is avoided, so that the safety of the device and the whole circuit is protected, the stability of the device and the circuit is improved, and the device can be widely applied to the environments of an inductive load circuit and the like.
(5) The current absorption structures in the device are distributed alternately, so that the contact resistance between the structures and the third metal electrode is reduced, and the current absorption capacity of the device can be enhanced by connecting the current absorption structures in parallel in an alternate distribution mode.
(6) From the simulation result of fig. 4, compared with the conventional device, when the external loading conditions are the same, the voltage peak values at the source and drain ends of the improved device under the single non-clamped inductive load switch are obviously reduced, so that the improved device is effectively protected, and the device can bear higher voltage.
Drawings
Fig. 1 is a structural view of a conventional heterojunction semiconductor device;
FIG. 2a is a front two-dimensional view of a heterojunction semiconductor device resistant to transient current surges in accordance with the present invention;
FIG. 2b is a front three-dimensional view of a heterojunction semiconductor device resistant to transient current surges in accordance with the present invention;
FIGS. 3 a-3 h are process flow diagrams of a heterojunction semiconductor device resistant to transient current surges in accordance with the present invention;
FIG. 4 is a simulation comparison graph of a heterojunction semiconductor device resistant to transient current surge proposed by the present invention and a conventional heterojunction semiconductor device, the graph showing the performance result of two devices subjected to transient current surge under a single non-clamped inductive load switch; it can be seen from the figure that, when the external loading conditions are the same, the high voltage at the two ends of the source and drain of the improved device under the single-time non-clamped inductive load switch is obviously reduced, so that the improved device is effectively protected, and the device can bear higher voltage.
The figure shows that: the semiconductor device comprises a substrate 1, a substrate resistor region 2, a first semiconductor layer 3, a second semiconductor layer 4, an electron channel 4a, a third semiconductor layer 5, a first medium region 6a, a first medium region 6b, an edge metal region 7a, a medium metal region 7b, a second edge medium region 8a, a second medium region 8b, a fourth semiconductor region 9, a first metal electrode 10, a second metal electrode 11, a third metal electrode 12 and a fourth metal electrode 13.
Detailed Description
The invention relates to a heterojunction semiconductor device resistant to transient current surge, comprising: the present invention is described in detail below with reference to the accompanying drawings, in which a substrate 1 is provided with a substrate resistor region 2 in the substrate 1, a first semiconductor layer 3, a second semiconductor layer 4, a third semiconductor layer 5, and a fourth semiconductor region 9 are sequentially provided on the substrate 1, the second semiconductor layer 4 is in contact with the third semiconductor layer 5 to form an electron channel 4a, a side metal region 7a, a middle metal region 7b, a first side dielectric region 6a, a first middle dielectric region 6b, a second side dielectric region 8a, and a second middle dielectric region 8b are sequentially provided on the substrate resistor region 2, a first metal electrode 10 and a third metal electrode 12 are provided on the third semiconductor layer 5, a second metal electrode 11 is provided on the fourth semiconductor region 9, and a fourth metal electrode 13 is provided below the substrate 1.
As can be seen from fig. 3a to 3h, a heterojunction semiconductor device resistant to transient current surge includes: a substrate 1, a substrate resistance region 2 is formed in the substrate 1 by implantation, a first semiconductor layer 3 and a second semiconductor layer 4 are grown on the substrate 1, a third semiconductor layer 5 is grown on the second semiconductor layer 4 and an electron channel layer 4a is formed, a p-type GaN cap layer gate structure 9 is formed on the third semiconductor layer by deposition and etching, a first side dielectric region 6a, a first middle dielectric region 6b, a side metal region 7a, a middle metal region 7b, a second side dielectric region 8a and a second middle dielectric region 8b are sequentially formed on the substrate resistance region 2 by deep trench etching and growth, a first metal electrode 10 and a third metal electrode 12 are formed on the third semiconductor layer 5, a second metal electrode 11 is formed on the p-type GaN cap layer gate structure 9, a fourth metal electrode 13 is formed under the substrate 1, wherein the substrate resistance region 2 forms a resistance region with certain resistivity by doping, the second edge dielectric region 8a and the second middle dielectric region 8b are high dielectric constant regions, the third metal electrodes 12 at two ends of the second edge dielectric region 8a and the second middle dielectric region 7b are in direct contact with the edge metal region 7a and the middle metal region 7b, the edge metal region 7a and the middle metal region 7b are in direct contact with the substrate resistance region 2, the first edge dielectric region 6a and the first middle dielectric region 6b are low dielectric constant regions, the edge metal region 7a, the middle metal region 7b and the first semiconductor layer 3 are positioned between the edge metal region 7a and the first semiconductor layer 3, and the second edge dielectric region 8a and the second middle dielectric region 8b are positioned between the first semiconductor layer 3, the second semiconductor layer 4 and the third semiconductor layer 5, the edge metal region 7a, the middle metal region 7b and the first semiconductor layer 3 are isolated, and the device structure between the third metal electrode 12 and the substrate resistance region 2 is vertically positioned according to the first edge dielectric region 6a, The first medium region 6b, the second medium region 8a, the second medium region 8b, the first medium region 6a, the first medium region 6b, the first semiconductor layer 3, the second semiconductor layer 4 and the third semiconductor layer 5 are alternately distributed in sequence. In this embodiment, a current absorbing structure is designed between the third metal electrode and the first metal electrode. The structure improves the transient current impact resistance of the device, for example, under a non-clamping inductive load switch, when the device is turned off, a large amount of energy released by the inductor is dissipated by the current absorption branch circuit between the third metal electrode and the first metal electrode. The structure avoids the breakdown of the device caused by the current flowing from the electron gas channel, thereby protecting the safety of the device and the whole circuit, improving the stability of the device and the circuit, and being widely applied to the environments of inductive load circuits and the like.
The invention adopts the following method to prepare:
the first step is as follows: referring to fig. 3a, a substrate 1 is formed using epitaxial techniques;
the second step is that: referring to fig. 3b, a substrate resistance region 2 is formed in the middle region of the substrate 1 by implantation using an implantation process;
the third step: referring to fig. 3c, a first semiconductor layer 3, a second semiconductor layer 4, and a third semiconductor layer 5 are sequentially grown over the substrate using a deposition process, and an electron channel layer 4a is generated;
the fourth step: referring to fig. 3d, a photolithography process is used to etch a deep trench on the upper portion of the substrate resistor region 2 to the upper surface of the substrate resistor region 2;
the fifth step: referring to fig. 3e, an initial first dielectric region 6a, 6b is deposited at the deep trench using a deposition process;
and a sixth step: referring to fig. 3f, a photolithography process is used to leave a first edge dielectric region 6a and a first middle dielectric region 6b as isolation layers on the contact surfaces of the initial first edge dielectric region 6a, the first middle dielectric region 6b and the semiconductor layer, and the rest is deeply grooved to the upper surface of the substrate resistance region 2;
the seventh step: referring to fig. 3g, a deposition process is adopted to deposit and form a side metal region 7a and a middle metal region 7b at the bottom of the deep groove; and continuing to form a second edge medium region 8a and a second middle medium region 8b on the upper surface of the third semiconductor layer 5 by the deep groove deposition;
eighth step: referring to fig. 3h, a layer of p-type GaN is deposited on the surface of the device by using a deposition process and an etching process, the middle part is reserved as a p-type GaN cap layer gate 9, and the rest part is etched to the upper surface of the third semiconductor layer 5;
and finally, depositing a metal layer on the surface of the device, etching an electrode contact area extraction electrode to form a first metal electrode 10, a second metal electrode 11 and a third metal electrode 12, forming a fourth metal electrode 13 below the substrate 1, and finally performing passivation treatment.
Claims (6)
1. A heterojunction semiconductor device resistant to transient current surges, characterized in that it comprises: the semiconductor device comprises a substrate (1), a substrate resistance region (2) is arranged in the substrate (1), a first semiconductor layer (3), a second semiconductor layer (4), a third semiconductor layer (5) and a fourth semiconductor region (9) are sequentially arranged above the substrate (1), the second semiconductor layer (4) is in contact with the third semiconductor layer (5) to form an electron channel (4a), a first edge dielectric region (6a), a first middle dielectric region (6b), an edge metal region (7a), a middle metal region (7b) and a second edge dielectric region (8a) are arranged above the substrate resistance region (2), a second middle dielectric region (8b) is arranged on the middle metal region (7b), the first edge dielectric region (6a) is arranged beside the second edge dielectric region (8a) and the edge metal region (7a), the first middle dielectric region (6b) is arranged beside the second middle dielectric region (8b) and the middle metal region (7b), a first metal electrode (10) and a third metal electrode (12) are respectively arranged on two sides of the third semiconductor layer (5), and the third metal electrode (12) covers the first side medium region (6a), the first middle medium region (6b), the second side medium region (8a) and the second middle medium region (8b) at the same time; the fourth semiconductor area (9) is positioned between the first metal electrode (10) and the third metal electrode (12), the second metal electrode (11) is arranged on the fourth semiconductor area (9), the fourth metal electrode (13) is arranged below the substrate (1) and the substrate resistance area (2), and the substrate resistance area (2) forms a resistance area with set resistivity through doping.
2. A heterojunction semiconductor device resistant to transient current surge according to claim 1, wherein the second edge dielectric region (8a) and the second middle dielectric region (8b) are high dielectric constant regions, the upper portions of which are in direct contact with the third metal electrode (12), and the lower portions of which are in direct contact with the edge metal region (7a) and the middle metal region (7 b).
3. A heterojunction semiconductor device resistant to transient current surge according to claim 1, wherein the lower portions of the edge metal region (7a) and the middle metal region (7b) are in direct contact with the substrate resistance region (2) and are in direct contact with the first edge dielectric region (6a) and the first middle dielectric region (6b) beside.
4. A heterojunction semiconductor device with transient current impact resistance as claimed in claim 1, wherein the first edge dielectric region (6a) and the first middle dielectric region (6b) are low-k regions, and are located between the edge metal region (7a) and the middle metal region (7b) and the first semiconductor layer (3), and also located between the second edge dielectric region (8a) and the second middle dielectric region (8b) and the first semiconductor layer (3), the second semiconductor layer (4) and the third semiconductor layer (5), so as to isolate the edge metal region (7a) and the middle metal region (7b) from the first semiconductor layer (3).
5. A heterojunction semiconductor device resistant to transient current surge according to claim 4, wherein the device structure between the third metal electrode (12) and the substrate resistance region (2) is alternately distributed in the depth direction according to the sequence of the second side dielectric region (8a), the first side dielectric region (6a), the first middle dielectric region (6b) and the second middle dielectric region (8 b).
6. A heterojunction semiconductor device resistant to transient current surge according to claim 4, wherein the first side dielectric region (6a), the first middle dielectric region (6b) and the second side dielectric region (8a), the second middle dielectric region (8b) adopt dielectrics with different dielectric constants.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001332567A (en) * | 2000-05-22 | 2001-11-30 | Sony Corp | Protective circuit for field effect transistor |
| CN1957472A (en) * | 2004-01-30 | 2007-05-02 | 皇家飞利浦电子股份有限公司 | Integrated circuit chip with electrostatic discharge protection device |
| CN102203936A (en) * | 2009-07-30 | 2011-09-28 | 住友电气工业株式会社 | Semiconductor device and method for manufacturing same |
| US20130221408A1 (en) * | 2012-02-28 | 2013-08-29 | Sony Corporation | Semiconductor device, manufacturing method thereof, protective element, and manufacturing method thereof |
| US20150108547A1 (en) * | 2013-10-17 | 2015-04-23 | Samsung Electronics Co., Ltd. | High electron mobility transistor |
| JP2015149324A (en) * | 2014-02-05 | 2015-08-20 | ルネサスエレクトロニクス株式会社 | semiconductor device |
| JP2017059786A (en) * | 2015-09-18 | 2017-03-23 | パナソニックＩｐマネジメント株式会社 | Semiconductor device |
| CN107104102A (en) * | 2016-02-23 | 2017-08-29 | 美国亚德诺半导体公司 | The apparatus and method of transient state overstress protection in the application of compound semiconductor circuit |
| CN107180865A (en) * | 2017-06-30 | 2017-09-19 | 东南大学 | A kind of low noise low-loss and insulating grid bipolar transistor |
| CN107919353A (en) * | 2016-10-10 | 2018-04-17 | 意法半导体有限公司 | Equipment for protecting against static discharge using distributed trigger circuit |
| US20190267482A1 (en) * | 2017-07-14 | 2019-08-29 | Cambridge Enterprise Limited | Power semiconductor device with an auxiliary gate structure |
| US20190326425A1 (en) * | 2018-04-20 | 2019-10-24 | Duet Microelectronics LLC | Dual-operation depletion/enhancement mode high electron mobility transistor |
-
2020
- 2020-10-22 CN CN202011143648.6A patent/CN112259605B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001332567A (en) * | 2000-05-22 | 2001-11-30 | Sony Corp | Protective circuit for field effect transistor |
| CN1957472A (en) * | 2004-01-30 | 2007-05-02 | 皇家飞利浦电子股份有限公司 | Integrated circuit chip with electrostatic discharge protection device |
| CN102203936A (en) * | 2009-07-30 | 2011-09-28 | 住友电气工业株式会社 | Semiconductor device and method for manufacturing same |
| US20130221408A1 (en) * | 2012-02-28 | 2013-08-29 | Sony Corporation | Semiconductor device, manufacturing method thereof, protective element, and manufacturing method thereof |
| CN103296024A (en) * | 2012-02-28 | 2013-09-11 | 索尼公司 | Semiconductor device, manufacturing method thereof, protective element, and manufacturing method thereof |
| US20150108547A1 (en) * | 2013-10-17 | 2015-04-23 | Samsung Electronics Co., Ltd. | High electron mobility transistor |
| JP2015149324A (en) * | 2014-02-05 | 2015-08-20 | ルネサスエレクトロニクス株式会社 | semiconductor device |
| JP2017059786A (en) * | 2015-09-18 | 2017-03-23 | パナソニックＩｐマネジメント株式会社 | Semiconductor device |
| CN107104102A (en) * | 2016-02-23 | 2017-08-29 | 美国亚德诺半导体公司 | The apparatus and method of transient state overstress protection in the application of compound semiconductor circuit |
| CN107919353A (en) * | 2016-10-10 | 2018-04-17 | 意法半导体有限公司 | Equipment for protecting against static discharge using distributed trigger circuit |
| CN107180865A (en) * | 2017-06-30 | 2017-09-19 | 东南大学 | A kind of low noise low-loss and insulating grid bipolar transistor |
| US20190267482A1 (en) * | 2017-07-14 | 2019-08-29 | Cambridge Enterprise Limited | Power semiconductor device with an auxiliary gate structure |
| US20190326425A1 (en) * | 2018-04-20 | 2019-10-24 | Duet Microelectronics LLC | Dual-operation depletion/enhancement mode high electron mobility transistor |
Non-Patent Citations (1)
| Title |
|---|
| 严鼎 等: "GaN功率器件预驱动芯片设计与封装集成", 《电源学报》 * |
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