CN112259538A

CN112259538A - Semiconductor device and manufacturing method thereof

Info

Publication number: CN112259538A
Application number: CN202011136209.2A
Authority: CN
Inventors: 张磊; 汤召辉; 周玉婷; 曾凡清; 董明
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-10-22
Filing date: 2020-10-22
Publication date: 2021-01-22
Anticipated expiration: 2040-10-22
Also published as: CN112259538B

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a core area and a step area, and the step area is provided with a top selection area and a subarea step structure area; the top selection area is provided with a first step group extending step by step along a first direction and a second step group extending step by step along a second direction, and the second direction is vertical to the first direction; the subarea ladder structure area is provided with a third ladder group which extends along the second direction step by step; the first step group, the second step group and the third step group have the same step number, and the steps of the same step have the same thickness; the steps in the first step group are correspondingly connected with the steps in the second step group one by one to form L-shaped steps; the steps in the second step group and the steps in the third step group are aligned in the first direction. The number of photomasks can be reduced when the step region is formed, so that the manufacturing process of the semiconductor device is simplified, and the production cost is saved.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The application relates to the technical field of semiconductor devices, in particular to a semiconductor device and a manufacturing method thereof.

Background

To overcome the limitations of the two-dimensional memory device, the industry has developed a memory device having a three-dimensional (3D) structure to increase integration density by arranging memory cells three-dimensionally over a substrate.

In a three-dimensional memory such as a 3D NAND flash memory, a memory array may include a core (core) region and a staircase region. The step region has multiple steps for leading out contact portions of control gates in each layer of the memory array. These control gates are used as word lines of the memory array to perform programming, erasing, reading, etc.

The stepped region includes a Top selection region (TSG region) adjacent to the core region and for arranging a Top selection Tube (TSG), and a stepped region (SDS) located on a side of the TSG region remote from the core region and extending in a direction away from the core region. In the SDS area, a partition (at least one step provided perpendicularly to a direction away from the core area) is designed in a direction perpendicular to the step extension direction, so that the area of the step area can be reduced by half, and cost reduction can be achieved.

However, the current process for fabricating the steps of the TSG region and the SDS region is complicated and costly.

Disclosure of Invention

The application provides a semiconductor device and a manufacturing method thereof, which can reduce the number of photomasks when a step region is formed, and are beneficial to simplifying the manufacturing process of the semiconductor device and saving the production cost.

The application provides a semiconductor device, which comprises a core area and a step area, wherein the step area is provided with a top selection area and a subarea step structure area which is positioned on one side of the top selection area far away from the core area; the stepped region extends in a first direction;

the top selection area is provided with a first step group extending step by step along the first direction and a second step group extending step by step along the second direction, and the second direction is perpendicular to the first direction;

the subarea ladder structure area is provided with a third ladder group extending along the second direction step by step;

the first step group, the second step group and the third step group have the same step number, and the steps of the same step have the same thickness; the steps in the first step group are correspondingly connected with the steps in the second step group one by one to form L-shaped steps; the steps in the second step group and the steps in the third step group are aligned in the first direction.

Optionally, the number of steps of the first step group is greater than or equal to 2, and the thickness of each step is the same.

Optionally, the top selection area further includes a top step located on the first step group and close to the core area; one side of the top ladder far away from the core area is positioned on one side of the first ladder group far away from the third ladder group;

the thickness of the top step is larger than that of any step in the first step group.

Optionally, the height of the third step group is smaller than the height of the second step group, and the height difference between each step in the third step group and the corresponding step in the second step group is the same.

Optionally, the stepped region includes a plurality of partitioned stepped structure regions arranged at intervals in the second direction.

Optionally, each same step in the first step group, the second step group, and the third step group includes at least one pair of stacked gate layers and dielectric layers.

Optionally, the semiconductor device comprises a three-dimensional memory device.

The application also provides a manufacturing method of the semiconductor device, which comprises the following steps:

providing a semiconductor structure; the semiconductor structure comprises a core region and a stepped region, wherein the stepped region is provided with a top selection region and a subarea stepped structure region which is positioned on one side of the top selection region far away from the core region; the stepped region extends in a first direction;

forming a first step group extending step by step along the first direction and a second step group extending step by step along the second direction in the top selection area, and forming a third step group extending step by step along the second direction in the partition step structure area; the second direction is perpendicular to the first direction, the first step group, the second step group and the third step group have the same step number, and the thickness of the steps at the same step is the same; the steps in the first step group are correspondingly connected with the steps in the second step group one by one to form L-shaped steps; the steps in the second step group and the steps in the third step group are aligned in the first direction.

Optionally, the step of forming a first step group extending step by step along the first direction and a second step group extending step by step along the second direction in the top selection area, and forming a third step group extending step by step along the second direction in the partition step structure area includes the following steps:

forming initial step groups extending step by step along the second direction in the partition step structure area and the top selection area, and forming first step groups extending step by step along the first direction in the top selection area; the initial step group and the first step group have the same step number, and the steps of the same step have the same thickness; the steps in the initial steps are correspondingly connected with the steps in the first step group one by one to form L-shaped steps;

carrying out integral thinning treatment on the subarea stepped structure area so as to convert the initial step group into a second step group positioned in the top selection area and a third step group positioned in the subarea stepped structure area; the height of the third step group is smaller than that of the second step group, and the height difference of each step in the third step group and the corresponding step in the second step group is the same.

Optionally, each step in the first step group, the second step group and the third step group has the same thickness.

forming a first initial step group extending step by step along the second direction in the partitioned stepped structure region and the top selection region, and forming a second initial step group extending step by step along the first direction in the top selection region; the first initial step group and the second initial step group have the same step number, the thickness of the step at the same step is the same, the thickness of the step at the highest step of the first initial step group and the second initial step group is greater than that of the step at each other step, and the thickness of the step at each other step is the same; the steps in the first initial steps are correspondingly connected with the steps in the second initial step group one by one to form L-shaped steps;

removing at least the steps at the highest level of the first initial step set and the second initial step set to form a first step set located in the top selection region and extending stepwise along the first direction, and a transition step set located in the partitioned step structure region and the top selection region and extending stepwise along the second direction; wherein the thickness of each step in the first step group and the transition step group is the same;

carrying out integral thinning treatment on the subarea stepped structure region so as to enable the transition step group to be changed into a second step group positioned in the top selection region and a third step group positioned in the subarea stepped structure region; the height of the third step group is smaller than that of the second step group, and the height difference of each step in the third step group and the corresponding step in the second step group is the same.

Optionally, in the step of removing at least the step located at the highest step of the first initial step group and the second initial step group, a top step located on the first step group and close to the core region is further formed; one side of the top ladder far away from the core area is positioned on one side of the first ladder group far away from the third ladder group;

Optionally, the same step in the first step group, the second step group and the third step group includes at least one pair of first material layer and second material layer stacked.

According to the semiconductor device and the manufacturing method thereof, the same photomask can be adopted to manufacture the ladder of the top selection area and the subarea of the subarea ladder structure area, one photoetching step and one photomask can be saved, the frequency of the trimming/etching process can be saved, the manufacturing process of the semiconductor device can be simplified, and the production cost can be saved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

FIG. 1 is a top block diagram of a storage array region of an exemplary three-dimensional memory.

Fig. 2 is a schematic partial perspective view of the step region of fig. 1.

Fig. 3A to 3F are mask patterns for forming the stepped region shown in fig. 2.

Fig. 4A to 4R are schematic cross-sectional views a-a and B-B forming the stepped region shown in fig. 2.

Fig. 5A to 5B are schematic partial perspective views illustrating the step region shown in fig. 2.

Fig. 6 is a schematic block flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 7A to 7E illustrate mask patterns for forming a step region according to a first embodiment of the present disclosure.

Fig. 8A to 8J are schematic cross-sectional views at a-a of a step region formed in the first embodiment of the present application.

Fig. 9A to 9J are schematic cross-sectional views at B-B of a step region formed in the first embodiment of the present application.

Fig. 10A to 10C are schematic partial perspective views illustrating a step region formed in the first embodiment of the present application.

Fig. 11 is a schematic partial perspective view of a semiconductor device according to a first embodiment and a third embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

FIG. 1 is a top view block diagram of a storage array region of an exemplary three-dimensional memory. As shown in fig. 1, a memory array region 100 is formed on a substrate and has stacked layers corresponding to memory cells. The memory array region 100 includes a Core (Core) region 110 and a staircase region 120. The stepped region 120 further comprises a top selection region 121 adjacent the core region and a plurality of separate zoned stepped structure (SDS) regions 122 located on a side of the top selection region 121 remote from the core region. Each SDS region 122 is, for example, a bar shape. These separate SDS regions 122 may be distributed on both sides of the core region 110 as in fig. 1, or may be distributed on only one side of the core region 110. The top selection region 121 located at the edge of the core region 110 has N steps, and each SDS region 122 is formed with N divisions in the Y direction (i.e., N steps are formed from both sides in the Y direction toward the center of the strip), where N is a natural number greater than or equal to 2, preferably 3, 4, 6, or 8. Fig. 2 is an exemplary partial perspective view of the step region of fig. 1. An example where N is equal to 6 is shown in fig. 2. Each SDS region is a 6-partition structure, i.e., 6 steps are formed in the Y direction. Each partition extends in the X direction and descends away from the core 110.

Fig. 3A-3C are mask patterns for forming the top select regions shown in fig. 2. Fig. 3D-3F are mask patterns for forming the partitioned ladder structure region shown in fig. 2. Fig. 4A-4R are exemplary partial cross-sectional views illustrating the formation of the step region shown in fig. 2, and in particular, partial cross-sectional views of the step region corresponding to the mask patterns a-a and B-B of fig. 3A-3F. Fig. 5A-5B are schematic partial perspective views illustrating the formation of the stepped region shown in fig. 2.

As shown in fig. 4A, the initial semiconductor structure 400a has a stack of layers 410. The stacked layer 410 includes first material layers and second material layers that are alternately stacked. The first material layer can be a gate layer or a sacrificial layer; the second material layer may be a dielectric layer. If each pair of stacked first and second material layers is considered to be one film layer, the stacked layer 410 may include a plurality of film layers stacked, for example, a first film layer 411, a second film layer 412, a third film layer 413, a fourth film layer 414, a fifth film layer 415, a sixth film layer 416, and the like from top to bottom. The thicknesses of the other film layers except the first film layer 411 are equal, and the thickness of the first film layer 411 is greater than the thicknesses of the other film layers.

As shown in fig. 3A and 4A, a first MASK pattern 30a is formed on the semiconductor structure 400a by photolithography and etching using a first photomask (MASK 1). The first mask pattern 30a covers only a portion of the stack layer 410, which is a left area in fig. 4A, for example, covers the core area and the top selection area. Next, as shown in fig. 4B, the exposed first film layer 411 is removed in the semiconductor structure 400B using the first mask pattern 30a to shrink it to 411a, forming a first initial step. Then, as shown in fig. 3B and 4C, the first mask pattern 30a is modified in the semiconductor structure 400C to be narrowed toward the core region (leftward in fig. 4C) to become a second mask pattern 30B. Then, as shown in fig. 4D, a second mask pattern 30b is used to remove a portion of the thickness of the stack of layers in the semiconductor structure 400D, including continuing to remove the exposed first film layer 411a, reducing it to 411b, thereby forming a first transition step at the location of the first initial step, and removing the exposed second film layer 412, reducing it to 412a, forming a second initial step. Then, as shown in fig. 3C and 4E, the second mask pattern 30b is modified in the semiconductor structure 400E to be narrowed toward the core region to become a third mask pattern 30C. Then, as shown in fig. 4F, a third mask pattern 30c is used to remove a portion of the thickness of the stack of layers in the semiconductor structure 400F, including continuing to remove the exposed first film layer 411b to reduce it to 411c, thereby forming a first step at the location of the first transition step, and removing the exposed second film layer 412a to reduce it to 412b, thereby forming a second step at the location of the second initial step, and removing the exposed third film layer 413 to reduce it to 413a, thereby forming a third step. A perspective view of the semiconductor structure 400f up to this step may be as shown in fig. 5A, resulting in a 3-level stair step structure of the top selection region 121 in the stair step region.

In accordance with the above, the third MASK pattern 30c on the semiconductor structure 400f is removed, and then, as shown in fig. 3D, 4G and 4M, the fourth MASK pattern 30D is formed on the semiconductor structure 400G by photolithography and etching using the second photomask (MASK 2). Wherein the fourth mask pattern 30d covers the entire top selection region of the semiconductor structure 400g in the stepped structure and a portion of the SDS region (at B-B). Next, as shown in fig. 4H and 4N, the exposed fourth film 414 is removed in the semiconductor structure 400H using the fourth mask pattern 30d and reduced to 414a, forming a third initial step, wherein the third initial step includes a third initial step located in the top selection region and a third initial step located in the SDS region. Then, as shown in fig. 3E, 4I and 4O, the fourth mask pattern 30d is trimmed to shrink toward the core region in the semiconductor structure 400I, thereby forming a fifth mask pattern 30E. Then, as shown in fig. 4J and 4P, a fifth mask pattern 30e is used to remove a portion of the thickness of the stack layer in the semiconductor structure 400J, including continuously removing the exposed fourth film layer 414a to reduce it to 414b, thereby forming a second transition step at the position of the third initial step, and removing the exposed fifth film layer 415 to reduce it to 415a, thereby forming a fourth initial step, wherein the second transition step includes a second transition step located in the top selection region and a second transition step located in the SDS region, and the fourth initial step includes a fourth initial step located in the top selection region and a fourth initial step located in the SDS region. Then, as shown in fig. 3F, 4K and 4Q, the fifth mask pattern 30e is trimmed to be narrowed toward the core region in the semiconductor structure 400K to be a sixth mask pattern 30F. Then, as shown in fig. 4L and 4R, a sixth mask pattern 30f is used to remove a portion of the thickness of the stack layer in the semiconductor structure 400L, including continuously removing the exposed fourth film layer 414b to reduce it to 414c, thereby forming a fourth step at the top selection region and a first step at the SDS region at the location of the second transition step, and removing the exposed fifth film layer 415a to reduce it to 415b, thereby forming a fifth step at the top selection region and a second step at the SDS region at the location of the fourth initial step, and removing the exposed sixth film layer 416 to reduce it to 416a, thereby forming a sixth step at the top selection region and a third step at the SDS region. A perspective view of the semiconductor structure 400l up to this step may be as shown in fig. 5B, resulting in a stepped structure of the partitioned stepped structure regions 122.

After the semiconductor structure shown in fig. 5B is formed, trimming/etching is continued according to a conventional process, so that the step structure shown in fig. 2 can be obtained.

In the above exemplary step region forming process, 2 times of photolithography and 2 photomasks (MASKs) are required to form the MASK patterns shown in fig. 3A and 3D, respectively, and the step structures of the top selection region and the partitioned step structure region are manufactured by the same number of trimming/etching processes, respectively, so that the step region forming process is complicated and the cost is high. Therefore, the present application is expected to further reduce the number of photolithography and the number of photomasks, simplify the process and save the cost, and particularly refer to the following embodiments.

Example one

As shown in fig. 6, an embodiment of the present application provides a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a three-dimensional memory device. The specific manufacturing method refers to step 601 and step 602.

Step 601: providing a semiconductor structure; the semiconductor structure comprises a core area and a step area, wherein the step area is provided with a top selection area and a subarea step structure area which is positioned on one side of the top selection area far away from the core area; the stepped region extends in a first direction.

The semiconductor structure in this embodiment is at least a portion of a structure that will be used in subsequent processing to ultimately form a three-dimensional memory device. The semiconductor structure may include an array region (array), which may include a core region (core) and a step region (SS). The core region is a region including memory cells, and the staircase region is a region including word line connection circuits. The array region may have a substrate and stacked layers, as viewed in a vertical direction. The stack layer may include gate layers (or sacrificial layers) and dielectric layers that are alternately stacked.

Specifically, the first direction in the present embodiment refers to the X direction in the drawing.

In the cross-sectional view of the initial semiconductor structure shown in fig. 8A, the semiconductor structure 800a may include a step region, only the step region is shown for simplicity, and other regions of the semiconductor structure in the horizontal direction, such as the core region on the right side of the figure, are not shown. Also, other layers in the vertical direction of the stepped region, such as the substrate, are not shown. The stacked layers 810 in the stepped region may include first material layers and second material layers (not shown) that are alternately stacked. The number of stacked pairs depends on the number of layers (e.g., 32 or 64 layers) of the three-dimensional memory device being fabricated. The first material layer may be a gate layer or a sacrificial layer, and the second material layer may be a dielectric layer. If each pair of stacked first and second material layers is considered to be one film layer, the stacked layers may include a plurality of film layers arranged in a stack, for example, a first film layer 811, a second film layer 812, a third film layer 813, and the like from top to bottom. Each film layer includes a stacked gate layer and a dielectric layer, or a stacked sacrificial layer and a dielectric layer.

In the embodiments of the present application, the substrate includes a silicon-containing substrate, such as Si, SOI (silicon on insulator), SiGe, Si: C, etc., without limitation.

Although exemplary configurations of the initial semiconductor structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure. In addition, the materials of the various layers illustrated are merely exemplary.

Step 602: a first step group extending step by step along the first direction and a second step group extending step by step along the second direction are formed in the top selection area, and a third step group extending step by step along the second direction is formed in the subarea step structure area; the second direction is perpendicular to the first direction, the first step group, the second step group and the third step group have the same step number, and the thickness of the steps at the same step is the same; the steps in the first step group are correspondingly connected with the steps in the second step group one by one to form L-shaped steps; the steps in the second step set and the steps in the third step set are aligned in the first direction.

Specifically, the second direction is the Y direction in the drawing. It should be noted that, the step-by-step extension described in this application refers to the extension direction of the step from high to low. In this embodiment, a manufacturing process of the first step group, the second step group, and the third step group is described by taking a 3-step structure as an example, and it can be understood that the first step group, the second step group, and the third step group formed by the manufacturing method in this embodiment all include 3 steps. In addition, it should be noted that, in the embodiment of the present application, the steps in the second step group and the steps in the third step group are aligned in the first direction, specifically, the orthographic projection of the 3-step in the second step group on the substrate and the orthographic projection of the 3-step in the third step group on the substrate are both aligned in the first direction (or are disposed correspondingly), and in a specific embodiment, the orthographic projection of the 3-step in the second step group on the substrate and the orthographic projection of the 3-step in the third step group on the substrate are connected (or continuous) in the first direction.

In a specific embodiment, step 602 specifically includes step 6021 and step 6023.

Step 6021: forming a first initial step group extending step by step along a second direction in the partition step structure area and the top selection area, and forming a second initial step group extending step by step along the first direction in the top selection area; the first initial step group and the second initial step group have the same step number, the thickness of the step of the same step is the same, the thickness of the step of the highest step of the first initial step group and the second initial step group is larger than that of the step of other steps, and the thickness of the step of other steps is the same; the steps in the first initial steps are correspondingly connected with the steps in the second initial step group one by one to form L-shaped steps.

In this embodiment, the thickness of the top film layer in the stack layer 810 is greater than the thickness of the other film layers for forming the step, and the thickness of the other film layers for forming the step is the same, for example, the thickness of the first film layer 811 is greater than the thickness of the second film layer 812 and the third film layer 813, and the thickness of the second film layer 812 and the third film layer 813 are the same.

Fig. 7A-7E illustrate mask patterns for forming the step regions in the first embodiment of the present application. FIGS. 8A-8J are schematic cross-sectional views taken along line A-A of the step region formed in the first embodiment of the present application. FIGS. 9A-9J are schematic cross-sectional views at B-B illustrating the step region formed in the first embodiment of the present application. Fig. 10A-10C are schematic partial perspective views illustrating the step region formed in the first embodiment of the present application.

Referring to fig. 7A to 7C, 8A to 8F, and 9A to 9F, the first initial step set and the second initial step set are manufactured as follows.

First, as shown in fig. 7A, 8A and 9A, a first mask pattern 70a is formed on the semiconductor structure 800 a. The first mask pattern 70a includes a first mask layer 71a and a second mask layer 72a connected to the first mask layer 71 a. In particular, a photomask (MASK) having a first region corresponding to a first MASK layer and a second region corresponding to a second MASK layer may be used to form a MASK pattern on a semiconductor structure. In the embodiment of the present application, the first photomask and the second photomask forming the exemplary step region shown in fig. 2 may be combined into one photomask, the combined photomask has a first region corresponding to the first mask layer and a second region corresponding to the second mask layer, and the combined photomask may be used to form the first mask pattern 70a on the semiconductor structure.

The first mask layer 71a covers the top select region and the core region of the stack layer 810, and the second mask layer 72a covers the partitioned ladder structure region of the stack layer 810. In the embodiment of the present application, the number of the second mask layers 72a may be varied. The first mask pattern 70a may include a plurality of second mask layers 72a spaced apart from each other and connected to a side of the first mask layer 71a away from the core region. The drawings in the embodiments of the present application show only two second mask layers 72a that are spaced apart from each other, and only one second mask layer is illustrated for describing the step region formation process. The first mask pattern may be a photoresist material, and the first mask pattern 70a shown in fig. 7A can be obtained by covering the entire photoresist layer on the stack 810, and then performing photolithography using a photomask and etching.

Then, as shown in fig. 8B and 9B, the exposed first film layer 811 is removed using the first mask pattern 70a in the semiconductor structure 800B to be reduced to 811a, forming a first initial step of an "L" shape. The first initial step includes a first sub-initial step S01a located at the top selection region and a first sub-initial step S01b located at the top selection region and the divisional step structure region, and the first sub-initial step S01a and the first sub-initial step S01b have the same thickness and constitute an "L" -shaped step.

Then, as shown in fig. 7B, 8C and 9C, the first mask pattern 70a is trimmed in the semiconductor structure 800C to be reduced toward the core region (leftward in fig. 8C) to be a second mask pattern 70B, wherein the first mask layer 71a and the second mask layer 72a are trimmed to be a first mask layer 71B and a second mask layer 72B, respectively. Then, as shown in fig. 8D and 9D, a portion of the thickness of the stack layer is removed in the semiconductor structure 800D using the first mask layer 71b and the second mask layer 72b of the second mask pattern 70b, including continuing to remove the exposed first film layer 811a to reduce it to 811b, thereby forming an "L" -shaped first transition step at the location of the first initial step, and removing the exposed second film layer 812 to reduce it to 812a, thereby forming an "L" -shaped second initial step. The first transition step comprises a first sub-transition step S11a located at the top selection region and a first sub-transition step S11b located at the top selection region and the partitioned ladder structure region, the first sub-transition step S11a and the first sub-transition step S11b have the same thickness and form an "L" -shaped step; the second initial step includes a second sub-initial step S02a located at the top selection region and a second sub-initial step S02b located at the top selection region and the divisional step structure region, and the second sub-initial step S02a and the second sub-initial step S02b have the same thickness and constitute an "L" -shaped step.

Then, as shown in fig. 7C, 8E and 9E, the second mask pattern 70b is trimmed to shrink toward the core region in the semiconductor structure 800E to become a third mask pattern 70C, wherein the second mask layer 71b and the second mask layer 72b are trimmed to become a first mask layer 71C and a second mask layer 72C, respectively. Then, as shown in fig. 8F and 9F, a partial thickness of the stack layer is removed in the semiconductor structure 800F using the first mask layer 71c and the second mask layer 72c of the third mask pattern 70c, including continuing to remove the exposed first film layer 811b, so as to be reduced to 811c, thereby forming an "L" -shaped first step S1 at the position of the first transition step, and removing the exposed second film layer 812a, so as to be reduced to 812b, thereby forming an "L" -shaped second step S2 at the position of the second initial step, and removing the exposed third film layer 813, so as to be reduced to 813a, thereby forming an "L" -shaped third step S3. Among them, the first step S1, the second step S2 and the third step S3 can be referred to fig. 10A.

Specifically, the first step S1 includes a first sub-step S1a located in the top selection region and a first sub-step S1b located in the top selection region and the partitioned step structure region, and the first sub-step S1a and the first sub-step S1b have the same thickness and form an "L" -shaped step; the second step S2 includes a second sub-step S2a located at the top selection region and a second sub-step S2b located at the top selection region and the divisional ladder structure region, the second sub-step S2a and the second sub-step S2b have the same thickness and form an "L" shaped step; the third step S3 includes a third sub-step S3a located in the top select area and a third sub-step S3b located in the top select area and the partitioned ladder structure area, the third sub-step S3a and the third sub-step S3b are the same thickness and form an "L" shaped step.

A perspective view of the semiconductor structure 800f up to this step may be seen in fig. 10A, resulting in a staircase region 1000A, wherein a first initial staircase set 1011 located in the top select region 1010 and the partitioned staircase region 1020 and a second initial staircase set 1012 located in the top select region 1010 are formed. Specifically, the first sub-step S1a, the second sub-step S2a, and the third sub-step S3a constitute a second initial step group 1012 extending stepwise in the first direction; the first sub step S1b, the second sub step S2b, and the third sub step S3b constitute a first initial step group 1011 extending stepwise in the second direction.

It can be understood that the steps of the same step in the first initial step set 1011 and the second initial step set 1012 are formed with the same thickness, and the thickness of each step is equal to the thickness of a corresponding film layer, while the thicknesses of the steps S1a and S1b of the highest step are greater than those of the other steps, so that the thicknesses of the steps of different steps of the step structure are different, which is not beneficial to improving the device function. Therefore, the next steps will be used to form the partitioned ladder structure with each step having the same thickness.

Step 6022: removing at least the highest step of the first initial step group and the second initial step group to form a first step group which is positioned in the top selection area and extends step by step along the first direction, and a transition step group which is positioned in the partitioned step structure area and the top selection area and extends step by step along the second direction; and the thicknesses of each step in the first step group and the transition step group are the same.

In this embodiment, in order to realize that the thicknesses of the steps at different levels of the partitioned stepped structure are the same, the step with the highest thickness needs to be removed, so that each step of the partitioned stepped structure region is formed by the film layers with the same thickness. The process may be implemented by an etching process, and according to different etching conditions, the number of top film layers to be removed may be one layer or multiple layers, which is not limited herein, and in the embodiment of the present application, only the step (i.e., the first film layer 811c) at the highest level is removed as an example for explanation.

Referring to fig. 7D, 8G to 8H, and 9G to 9H, the first step set and the transition step set are manufactured as follows.

In the semiconductor structure 800f, as shown in fig. 7D, 8G and 9G, the third mask pattern 70c is trimmed to shrink toward the core region to form the fourth mask pattern 70D in the semiconductor structure 800G, and the fourth mask pattern 70D only covers the core region, so that the second mask layer 72c is completely removed and the first mask layer 71c shrinks toward the core region. Then, as shown in fig. 8H and 9H, a portion of the thickness of the stack layer is removed in the semiconductor structure 800H using the fourth mask pattern 70d, including continuing to remove the exposed first film layer 811c to 811d, thereby forming a top step S0 at the position of the first step S1, and removing the exposed second film layer 812b to 812c, thereby forming a new first step S1 ' at the position of the second step S2, and removing the exposed third film layer 813a to 813b, thereby forming a new second step S2 ' at the position of the third step S3, and removing the exposed fourth film layer 814 to 814a, thereby forming a new first step S1 '. Therein, a new first step S1 ', a new second step S2 ' and a new third step S3 ' can be seen with reference to fig. 10B.

Specifically, top step S0 is located near the core region and on the first step set; the side of top step S0 remote from the core region is located on the side of the first step set remote from the third step set; the thickness of the top step is larger than that of any step in the first step group.

Specifically, the new first step S1 ' includes a first sub-step S1a ' located in the top selection region and a first sub-step S1b ' located in the top selection region and the partitioned step structure region, and the first sub-step S1a ' and the first sub-step S1b ' have the same thickness and form an "L" -shaped step; the new second step S2 ' includes a second sub-step S2a ' located at the top selection region and a second sub-step S2b ' located at the top selection region and the divisional ladder structure region, the second sub-step S2a ' and the second sub-step S2b ' have the same thickness and constitute an "L" -shaped step; the new third step S3 ' includes a third sub-step S3a ' located in the top select area and a third sub-step S3b ' located in the top select area and the partitioned ladder structure area, the third sub-step S3a ' and the third sub-step S3b ' are the same thickness and constitute an "L" shaped step.

A perspective view of the semiconductor structure 800h up to this step may be seen in fig. 10B, resulting in a staircase region 1000B, in which a transition staircase set 1013 at the top selection region 1010 and the partitioned staircase structure region 1020 and a first staircase set 1014 at the top selection region 1010 are formed. Specifically, the first sub-step S1a ', the second sub-step S2a ', and the third sub-step S3a ' constitute a first step group 1014 extending stepwise in a first direction; the first sub-step S1b ', the second sub-step S2b ', and the third sub-step S3b ' constitute a transitional step group 1013 extending stepwise in the second direction. Since the steps in the set 1013 are made of layers having the same thickness, the steps of different steps have the same thickness.

However, at this time, the height difference between the step group of the partitioned step structure area 1020 and the step group of the top selection area 1010 has not reached the preset height, and the next step 6023 will realize that the height difference between the step group of the partitioned step structure area 1020 and the step group of the top selection area 1010 is the preset height.

Step 6023: carrying out integral thinning treatment on the subarea stepped structure area so as to convert the transition stepped group into a second stepped group positioned in the top selection area and a third stepped group positioned in the subarea stepped structure area; the height of the third ladder group is smaller than that of the second ladder group, and the height difference of each step in the third ladder group and the corresponding step in the second ladder group is the same.

In this embodiment, the height difference between the third step group and the second step group is preset to be 3 steps (three layers with the same thickness) of thickness, but not limited thereto, in other embodiments, the height difference between the third step group and the second step group may be greater than 3 steps of thickness, or may be smaller than 3 steps of thickness.

Referring to fig. 7E, 8I to 8J, and 9I to 9J, the second step set and the third step set are fabricated as follows.

Following the semiconductor structure 800h, the fourth mask pattern 70d in the semiconductor structure 800h is removed. Then, as shown in fig. 7E, 8I and 9I, a fifth mask pattern 70E is formed on the semiconductor structure 800I. The fifth mask pattern 70e covers the entire core region and the top selection region. Specifically, a mask pattern may be formed on the semiconductor structure using a photomask (which is not required to be additionally fabricated) that is commonly used in a subsequent process. The fifth mask pattern may be a photoresist material. The fifth mask pattern 70E shown in fig. 7E can be obtained by covering the stack 810 of the semiconductor structure 800i with a complete photoresist layer, and then performing photolithography using a conventional photomask, followed by etching. It will be appreciated that the orthographic projection of the fifth mask pattern on the substrate completely covers the orthographic projection of the first mask pattern on the substrate.

Then, as shown in fig. 8J and 9J, the thickness of the three-layer film in the partitioned ladder structure region of the stack layer is removed using the fifth mask pattern 70e in the semiconductor structure 800J, including completely removing the exposed second, third, and fourth film layers 812c, 813b, and 814a in the partitioned ladder structure region, and removing the gradually exposed fifth film layer 815 in the partitioned ladder structure region, reducing it to 815a, and forming a new first ladder S1 ″, and removing the gradually exposed sixth film layer 816, reducing it to 816a, and forming a new second ladder S2 ″, and removing the gradually exposed seventh film layer 817, reducing it to 817a, and forming a new third ladder S3 ″.

It should be noted that the fifth membrane layer 815, the sixth membrane layer 816, and the seventh membrane layer 817 are sequentially located below the fourth membrane layer 814, and the thickness of the fifth membrane layer 815, the sixth membrane layer 816, and the seventh membrane layer 817 is the same as that of the fourth membrane layer 814.

It can be understood that, in the above process, the heights of the first step set and the transition step set in the top selection region are kept unchanged, while the height of the transition step set in the partitioned step structure region is reduced by the thickness of the three-layer film as a whole, i.e. by the thickness of the 3-step, so that the transition step set is broken into two parts, one part is the second step set in the top selection region, and the other part is the third step set in the partitioned step structure region.

The perspective view of the semiconductor structure 800j up to this step can be seen in fig. 10C, resulting in a step region 1000C, wherein a second step group 1015 at the top selection region 1010d and a third step group 1016 at the partitioned step structure region 1020 are formed. Specifically, the second step group 1015 is formed of transition step groups remaining at the top selection area 1010d, and the third step group 1016 is formed of a new first step S1 ", a new second step S2", and a new third step S3 ", and extends stepwise toward the second direction. Since the thicknesses of the film layers constituting the second step group 1015 and the third step group 1016 are the same, the thickness of each step is equal to the thickness of one film layer, and the third step group 1016 is obtained by integrally thinning, each step of the third step group 1016 corresponds to a step in the second step group 1015, and the height difference of the corresponding steps is the same.

After forming the semiconductor structure shown in fig. 10C, trimming/etching is continued according to a conventional process, so that the semiconductor structure 1100 shown in fig. 11 can be obtained.

It should be noted that the mask pattern in the embodiments of the present application always covers the core region, and when the mask pattern is trimmed, the whole periphery of the mask pattern is reduced toward the core region, and the mask pattern in the drawings of the embodiments of the present application only shows a part of the mask pattern located on one side of the core region.

Different from the manufacturing process of the exemplary step region, in the embodiment of the present application, the first photomask and the second photomask which form the exemplary step region are combined into one photomask, the first mask pattern 70a in the embodiment of the present application may be formed by using the combined photomask, the step of the top selection region and the step partition of the step partition structure region are simultaneously manufactured by using the first mask pattern 70a and combining the trimming/etching process, the mask patterns shown in fig. 3A and 3D are prevented from being formed by using 2 times of photolithography and 2 photomasks, and the step of the top selection region and the step partition of the step partition structure region are prevented from being manufactured by using the same number of trimming/etching processes; therefore, the method can save one photoetching step and one photomask, can save the times of finishing/etching processes, and is beneficial to simplifying the manufacturing process of the semiconductor device and saving the production cost.

Example two

The embodiment of the present application further provides a method for manufacturing a semiconductor device, which is different from the above embodiments in that all thicknesses of film layers used for forming steps in the stacked layers in the embodiment of the present application are equal, and step 602 includes only the following steps:

forming initial step groups extending step by step along the second direction in the partition step structure area and the top selection area, and forming first step groups extending step by step along the first direction in the top selection area; the initial step group and the first step group have the same step number, and the steps of the same step have the same thickness; the steps in the initial steps are correspondingly connected with the steps in the first step group one by one to form L-shaped steps.

Carrying out integral thinning treatment on the partitioned stepped structure area so as to convert the initial step group into a second step group positioned in the top selection area and a third step group positioned in the partitioned stepped structure area; the height of the third ladder group is smaller than that of the second ladder group, and the height difference of each step in the third ladder group and the corresponding step in the second ladder group is the same.

Specifically, each step in the first step group, the second step group and the third step group has the same thickness.

It will be appreciated that in the present embodiment, there is no top step with a large thickness, so that the mask pattern shown in fig. 7D need not be formed, nor need step 6022 be performed. Therefore, in the present embodiment, the second initial ladder set in the first embodiment can be replaced by the first ladder set in the present embodiment, and the first initial ladder set in the first embodiment can be replaced by the initial ladder set in the present embodiment. Since the method of forming the step is the same, the detailed manufacturing process is not described in detail in this embodiment.

EXAMPLE III

As shown in fig. 11, an embodiment of the present application further provides a semiconductor device 1100 formed by the manufacturing method described in the first embodiment, where the semiconductor device 1100 includes a core region and a step region, and the positional relationship between the core region and the step region may refer to a top view block diagram of a memory array region of the exemplary three-dimensional memory shown in fig. 1. The staircase region has a top selection region 1110 and a partitioned staircase region 1120 located on a side of the top selection region 1110 remote from the core region; the stepped region extends in a first direction (X direction); the top selection area 1110 has a first step group 1014 extending stepwise in a first direction and a second step group 1015 extending stepwise in a second direction (Y direction) arranged perpendicular to the first direction; the partitioned ladder structure region 1120 has a third ladder group 1016 extending stepwise in the second direction; the first step group 1014, the second step group 1015 and the third step group 1016 have the same step number, and the thickness of the steps at the same step is the same; the steps in the first step group 1014 are correspondingly connected with the steps in the second step group 1015 one by one to form L-shaped steps; the steps in the second step group 1015 and the steps in the third step group 1016 are arranged in a one-to-one correspondence in the first direction.

Specifically, the semiconductor device 1100 is a three-dimensional memory device, and the structures such as the substrate and the stacked layers of the semiconductor device 1100 can be referred to in the first embodiment, which is not described herein again.

Specifically, the number of steps of the first step set 1014, the second step set 1015 and the third step set 1016 is greater than or equal to 2, and the thickness of each step is the same. In this embodiment, each step group includes 3 steps, but is not limited thereto, and each step corresponds to one film layer, and each film layer is composed of a gate layer and a dielectric layer stacked in a stacked manner. Of course, in other embodiments, portions of the steps may be formed from multiple layers of film.

Specifically, the first step set 1014 is composed of the first sub-step S1a ', the second sub-step S2a ' and the third sub-step S3a ' in the first embodiment; the second step group 1015 is composed of the first sub-step S1b ', the second sub-step S2b ' and the third sub-step S3b ' located at the top selection area in the first embodiment; the third step group 1016 is comprised of a first step S1 ", a second step S2", and a third step S3 ". The first sub-step S1a ', the second sub-step S2 a' and the third sub-step S3a 'extend in the first direction step by step, and the first sub-step S1 b', the second sub-step S2b 'and the third sub-step S3 b' extend in the second direction step by step. The first sub-step S1a ' and the first sub-step S1b ' form an "L" -shaped first step S1 ', the second sub-step S2a ' and the second sub-step S2b ' form an "L" -shaped second step S2 ', and the third sub-step S3a ' and the third sub-step S3b ' form an "L" -shaped third step S3 '. The first step S1 "corresponds to the first step S1b ', the second step S2" corresponds to the second step S2b ', and the third step S3 "corresponds to the third step S3b '.

Specifically, top selection region 1110 further includes a top ladder S0 located one level adjacent to the core region and on first ladder group 1014; the side of top step S0 away from the core is located on the side of first step set 1014 away from third step set 1016; the thickness of the top step S0 is greater than the thickness of any one step in the first step set 1014.

Specifically, the height of the first step set 1014 is equal to the height of the second step set 1015, the height of the third step set 1016 is smaller than the height of the second step set 1015, and the height difference between each step in the third step set 1016 and the corresponding step in the second step set 1015 is the same. In this embodiment, the height difference between the third step group 1016 and the second step group 1015 is equal to the sum of the thicknesses of the 3 steps, that is, equal to the sum of the thicknesses of the three layers of films with the same thickness, and in other embodiments, the height difference between the third step group 1016 and the second step group 1015 may be another preset value.

Specifically, the stepped region includes a plurality of partitioned stepped structure regions spaced apart in the second direction, and only two stepped structure regions are shown in the present embodiment, but not limited thereto.

In this embodiment, the same photomask can be used to manufacture the step of the top selection region and the partition of the partitioned step structure region, so that one photolithography step and one photomask can be saved, the frequency of trimming/etching process can be saved, the manufacturing process of the semiconductor device can be simplified, and the production cost can be saved.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The foregoing detailed description is directed to a semiconductor device and a method for manufacturing the same provided in the embodiments of the present application, and specific examples are applied in the detailed description to explain the principles and implementations of the present application, and the description of the foregoing embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device comprising a core region and a stepped region, the stepped region having a top selection region and a segmented stair-step structure region on a side of the top selection region remote from the core region; the stepped region extends in a first direction;

2. The semiconductor device according to claim 1, wherein the number of steps of the first step group is 2 or more, and the thickness of each step is the same.

3. The semiconductor device of claim 2, wherein the top select region further comprises a top step one level adjacent to the core region and on the first set of steps; one side of the top ladder far away from the core area is positioned on one side of the first ladder group far away from the third ladder group;

4. The semiconductor device of claim 1, wherein the height of the third step set is less than the height of the second step set, and each step in the third step set has the same height difference as the corresponding step in the second step set.

5. The semiconductor device according to claim 1, wherein the stepped region includes a plurality of the divisional stepped structure regions arranged at intervals in the second direction.

6. The semiconductor device of claim 1, wherein each identical level ladder of the first, second, and third ladder sets comprises at least one pair of gate layers and dielectric layers arranged in a stack.

7. The semiconductor device according to claim 1, wherein the semiconductor device comprises a three-dimensional memory device.

8. A method for manufacturing a semiconductor device is characterized by comprising the following steps:

9. The method for manufacturing the semiconductor device according to claim 8, wherein the step of forming a first step group extending stepwise along the first direction and a second step group extending stepwise along the second direction in the top selection region, and forming a third step group extending stepwise along the second direction in the partitioned step structure region comprises the steps of:

10. The method of manufacturing a semiconductor device according to claim 9, wherein each step in the first step group, the second step group, and the third step group has the same thickness.

11. The method for manufacturing the semiconductor device according to claim 8, wherein the step of forming a first step group extending stepwise along the first direction and a second step group extending stepwise along the second direction in the top selection region, and forming a third step group extending stepwise along the second direction in the partitioned step structure region comprises the steps of:

12. The method of claim 11, wherein the step of removing at least the top step of the first initial step group and the second initial step group further forms a top step of the first step group adjacent to the core region; one side of the top ladder far away from the core area is positioned on one side of the first ladder group far away from the third ladder group;

13. The method of manufacturing a semiconductor device according to claim 10 or 11, wherein the same step in the first step group, the second step group, and the third step group includes at least one pair of first material layer and second material layer disposed in a stacked manner.