CN208753319U - Three-dimensional storage - Google Patents

Abstract

The utility model relates to a kind of three-dimensional storages, including core space and stepped region, the stepped region has top selection area and subregion hierarchic structure area, and top selection area and subregion hierarchic structure area have identical first ladder of height, and have identical second ladder of height；Wherein in top selection area, first ladder is higher than second ladder and than second ladder closer to the core space；In subregion hierarchic structure area, first ladder is higher than second ladder and than second ladder further from top selection area.The utility model can reduce the number of photoetching and the quantity of photomask when forming subregion.

Description

Three-dimensional storage

Technical field

The utility model relates generally to semiconductor devices more particularly to a kind of three-dimensional storage.

Background technique

In order to overcome the limitation of two-dimensional storage device, industry has been developed that the memory device with three-dimensional (3D) structure, Integration density is improved by the way that memory cell is three-dimensionally disposed in substrate.

In such as three-dimensional storage of 3D nand flash memory, storage array may include the core area (core) and stepped region.Rank Terraced area is used to draw contact portion for the control gate in each floor of storage array.Wordline of these control gates as storage array executes The operation such as programming, erasable, reading.

Stepped region typically uses unidirectional hierarchic structure.With the increase of the three-dimensional storage number of plies, the knot of unidirectional ladder Structure causes the area increase of stepped region and cost of manufacture to steeply rise.A kind of subregion hierarchic structure is proposed thus It the area (staircase divide Scheme, SDS) can be by stepped region by the zoning design perpendicular to ladder direction Area halves, the reduction of cost of implementation.

Currently in order to realizing subregion, need using 2 photoetching and 2 photomasks.

Utility model content

The utility model provides a kind of three-dimensional storage, and the number and photomask of photoetching can be reduced when forming subregion Quantity.

The utility model to solve above-mentioned technical problem and the technical solution adopted is that provide a kind of three-dimensional storage, including Core space and stepped region, the stepped region have top selection area and subregion hierarchic structure area, top selection area and described Subregion hierarchic structure area has identical first ladder of height, and has identical second ladder of height；Wherein at the top Area is selected, first ladder is higher than second ladder and than second ladder closer to the core space；At described point Hierarchic structure area, area, first ladder are higher than second ladder and select than second ladder further from the top Area.

In an embodiment of the utility model, the stepped region includes the subregion hierarchic structure area of multiple separation.

In an embodiment of the utility model, first ladder and/or the second ladder include at least a pair of stack Grid layer and dielectric layer.

In an embodiment of the utility model, the top select between area and subregion hierarchic structure area for lower than The plane of second ladder.

In an embodiment of the utility model, subregion hierarchic structure area include be distributed in a first direction it is multiple Subregion, each subregion include in a second direction to far from top selection area direction decline multiple ladders, described first Perpendicular to the second direction, the second direction is the extending direction of the stepped region in direction.

In an embodiment of the utility model, each ladder of the multiple ladder includes at least a pair of grid stacked Layer and dielectric layer.

In an embodiment of the utility model, the grid layer is electrically connected with the contact portion perpendicular to the grid layer.

In an embodiment of the utility model, the difference in height of adjacent sectors is the height of a ladder in the multiple subregion Degree.

In an embodiment of the utility model, stepped region is arranged in side or the opposite sides of the core space.

In an embodiment of the utility model, the three-dimensional storage is 3D nand flash memory.

The utility model due to using the technology described above, need to only use a photomask, carrying out a photoetching can shape At the subregion hierarchic structure area of the stepped region of three-dimensional storage, therefore a lithography step and a photomask can be saved, letter The manufacture craft of three-dimensional storage is changed.

Detailed description of the invention

It is practical to this below in conjunction with attached drawing for the above objects, features, and advantages of the utility model can be clearer and more comprehensible Novel specific embodiment elaborates, in which:

Fig. 1 is the vertical view block diagram in the storage array region of three-dimensional storage.

Fig. 2 is the sectional perspective schematic diagram in Fig. 1 in relation to stepped region.

Fig. 3 A-3D is the mask pattern in the example process for be formed the stepped region with subregion as shown in Figure 2.

Fig. 4 A-4H is the diagrammatic cross-section to form the example process of the stepped region with subregion as shown in Figure 2.

Fig. 5 A-5C is the example process to form the stepped region shown in Fig. 2 with subregion.

Fig. 6 is that the stepped region with subregion is formed in the three-dimensional storage manufacturing method according to an embodiment of the present invention Flow chart.

Fig. 7 A, 7B are that had in the example process of stepped region of subregion according to the formation of an embodiment of the present invention Mask pattern.

Fig. 8 A-8E is shown according to the section of the example process of the stepped region with subregion of an embodiment of the present invention It is intended to.

Fig. 9 A-9D is the stepped region in the three-dimensional storage manufacturing method according to an embodiment of the present invention with subregion Example process.

Figure 10 is the top view for the stepped region for having subregion according to the three-dimensional storage of an embodiment of the present invention.

Specific embodiment

It is practical to this below in conjunction with attached drawing for the above objects, features, and advantages of the utility model can be clearer and more comprehensible Novel specific embodiment elaborates.

Many details are explained in the following description in order to fully understand the utility model, but this is practical new Type can also be implemented using other different from other way described herein, therefore the utility model is not by following public tool The limitation of body embodiment.

As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising" Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus The step of may also including other or element.

When the utility model embodiment is described in detail, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general ratio Example makees partial enlargement, and the schematic diagram is example, should not limit the range of the utility model protection herein.In addition, The three-dimensional space of length, width and depth should be included in actual fabrication.

For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper" Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers " between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.

In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features Embodiment, such first and second feature may not be direct contact.

Fig. 1 is the vertical view block diagram in the storage array region of three-dimensional storage.Refering to what is shown in Fig. 1,100 shape of storage array region At on substrate, and there is the stack layer of corresponding storage unit.Storage array region includes area core (Core) 110 and stepped region 120.Stepped region 120 further comprises multiple isolated areas subregion hierarchic structure (SDS) 122.The edge of core space 110 and each The edge in the area SDS 122 separates preset distance.The shape in each area SDS 122 is, for example, long strip type.The area SDS of these separation 122 can be distributed in the two sides of core space 110 as Fig. 1, can also be distributed only over the wherein side of core space 110.Core space 110 edge has N grades of ladders, and the isolated area SDS is formed with N number of subregion (i.e. from two side directions of Y-direction in the Y direction Strip center direction forms N grades of ladders), wherein N is the natural number more than or equal to 2, preferably 3,4,6 or 8 etc..Fig. 2 is figure In relation to the sectional perspective schematic diagram of stepped region in 1.It is illustrated in figure 2 the example that N is equal to 6.The area SDS of left side long strip type in Fig. 2 122a, 122b are spaced apart preset distance with right side core space (not showing in Fig. 2).Each area SDS is 6 partitioned organizations, i.e., in the side Y It is upwardly formed 6 ladders.Each subregion then extends in the X direction, and declines towards the direction far from core space.The edge of core space N grade ladder and N number of subregion of Y-direction the same photomask can be used, it is synchronous to pass through amendment (Trim)/etching (Etch) technique It is formed, therefore the isolated area SDS of strip is respectively formed the hierarchic structure towards center in surrounding.

Fig. 3 A-3D is the mask pattern in the example process for be formed the stepped region shown in Fig. 2 with subregion.Fig. 4 A-4H It is the diagrammatic cross-section to form the example process of the stepped region shown in Fig. 2 with subregion.The solid of initial semiconductor structure Figure can refer to shown in Fig. 5 A.With reference to shown in Fig. 3 A and 4A, lithography and etching first is carried out using the first photomask, in semiconductor structure Mask pattern 30a is formed on 400a.Semiconductor structure 400a has stack layer 410.Stack layer 410 includes first be alternately stacked Material layer 401 and second material layer 402.First material layer 401 can be grid layer or dummy gate layer.Second material layer 402 can be Dielectric layer.If the first material layer 401 of each pair of stacking and second material layer 402 are considered as a film layer, stack layer 410 It may include multiple film layers, such as the first film layer 411, the second film layer 412 and third membrane layer 413 etc..First wraps to third membrane layer The grid layer and dielectric layer of stacking are included, or the dummy gate layer and dielectric layer that stack.Mask pattern 30a only covers stack layer 410 A part, in figure be left area.Then it as shown in Fig. 4 B, is gone in semiconductor structure 400b using mask pattern 30a Except the first film layer 411 being exposed, it is allowed to be reduced into 411a, forms initial step S0.Then as shown in Fig. 3 B and Fig. 4 C, half Mask pattern 30a is modified in conductor structure 400c, is reduced it to the direction (left in Fig. 4 C) close to core space, is become and cover Mould pattern 30b.Then as shown in Figure 4 D, stack layer is removed using the mask pattern 30b after finishing in semiconductor structure 400d Segment thickness, a part of 411a of the first film layer being exposed including continuing removal is allowed to be reduced into 411b, thus first The position of beginning ladder S0 forms the first ladder S1, and the second film layer 412 that removal is exposed, and is allowed to be reduced into 412a, forms the Two ladder S2.Perspective view to the semiconductor structure 400d of this step can refer to shown in Fig. 5 B.

Hold it is above-mentioned, then as shown in Fig. 3 C and Fig. 4 E, using the second photomask carry out lithography and etching, in semiconductor structure Mask pattern 30c is formed on 400e.Mask pattern 30c only covers a part of stack layer 410, includes the in figure for left side The part of one ladder S1 and the second ladder S2.Then as illustrated in figure 4f, gone in semiconductor structure 400f using mask pattern 30c It except the third membrane layer 413 being exposed, is allowed to be reduced into 413a, forms another initial step S0 '.Then such as Fig. 3 D and Fig. 4 G institute Show, mask pattern 30c modified in semiconductor structure 400g, reduces it to the direction (left in Fig. 4 G) close to core space, As mask pattern 30d.Then as shown at figure 4h, removed in semiconductor structure 400h using the mask pattern 30d after finishing The segment thickness of stack layer, a part of 411a including continuing the first film layer that removal is exposed, is allowed to be reduced into 411b, from And third ladder S3, and the 4th film layer 414 that removal is exposed are formed in the position of another initial step S0 ', it is allowed to be reduced into 414a forms fourth order ladder S4.In this course, multiple and different ladders are also formed in the region SDS of semiconductor structure Subregion.Perspective view to the semiconductor structure 400h of this step can refer to shown in Fig. 5 C.

After forming structure shown in Fig. 5 C, continuation modify/etch according to common process, available as shown in Figure 2 Hierarchic structure.

In above process, 2 photoetching and 2 photomasks is needed to be respectively formed mask pattern shown in Fig. 3 A and Fig. 3 C. It is expected that being further reduced photoetching number and photomask quantity.

Fig. 6 is that the stepped region with subregion is formed in the three-dimensional storage manufacturing method according to an embodiment of the present invention Flow chart.Fig. 7 A, 7B are that had in the example process of stepped region of subregion according to the formation of an embodiment of the present invention Mask pattern.Fig. 8 A-8E is cuing open according to the example process of the stepped region with subregion of an embodiment of the present invention Face schematic diagram.There is the process of the stepped region of subregion below with reference to the formation for describing the present embodiment shown in Fig. 6-8E.

In step 602, semiconductor structure is provided.

This semiconductor structure is at least one for being used for structure of the follow-up process to ultimately form three-dimensional storage part Point.Semiconductor structure may include array area (array), array area may include core space (core) and stepped region (stair step, SS).Core space is the region for including storage unit, and stepped region is the region for including wordline connection circuit.In terms of vertical direction, battle array Column area can have substrate and stack layer.Stack layer may include the grid layer (or dummy gate layer) and dielectric layer being alternately stacked.

In the sectional view of the semiconductor structure exemplified by Fig. 8 A, semiconductor structure 800a may include stepped region, for simplification For the sake of, other regions of semiconductor structure in the horizontal direction, such as core space are not shown.And stepped region is also not shown to hang down Other upward layers of histogram, such as substrate.Stack layer 810 in stepped region may include 801 He of first material layer being alternately stacked Second material layer 802.The logarithm of stacking depends on the number of plies (such as 32 layers or 64 layers) of made three-dimensional storage part.First material The bed of material 801 can be grid layer or dummy gate layer.Second material layer 802 can be dielectric layer.If by the first material of each pair of stacking Layer 801 and second material layer 802 are considered as a film layer, then stack layer 410 may include multiple film layers, such as the first film layer 811, the Two film layers 812 and third membrane layer 813 etc..First to third membrane layer 811-813 includes the grid layer and dielectric layer stacked, or The dummy gate layer and dielectric layer of stacking.The perspective view of semiconductor structure 800a can refer to shown in Fig. 9 A.

In the embodiments of the present invention, substrate is typically siliceous substrate, such as Si, SOI (silicon-on-insulator), SiGe, Si:C etc., although this and it is non-limiting.First material layer 801 and second material layer 802 are the groups of silicon nitride and silica Conjunction, silica and (undoped) polysilicon or combination, silicon oxide or silicon nitride and the combination of amorphous carbon of amorphous silicon etc..With nitrogen It, can be using chemical vapor deposition (CVD), atomic layer deposition (ALD) or other are suitable for the combination of SiClx and silica Deposition method, successively on substrate alternating deposit silicon nitride (for example, first material layer 801) and silica (for example, the second material 802) layer, forms the stack layer 810.

Although there is described herein the exemplary composition of initial semiconductor structure, it is to be understood that, one or more features It can be omitted, substitute or increase to from this semiconductor structure in this semiconductor structure.In addition, each layer illustrated Material be only exemplary.

In step 604, mask pattern is formed on stepped region.

Here, mask pattern includes the first mask layer and the second mask layer of separation.A photomask can be used partly leading Mask pattern is formed in body structure, photomask has the second of the first area of corresponding first mask layer and corresponding second mask layer Region.

With reference to shown in Fig. 7 A and 8B, mask pattern 70a includes the first mask layer 71a and the second mask layer 72a.First covers Mold layer 71a and the second mask layer 72a are separated from each other in their extension direction.In the semiconductor structure 800b of Fig. 8 B, first is covered Mold layer 71a covers a part of stack layer 810, is left area in figure.Second mask layer 72a covers the another of stack layer 810 A part is right side central region in figure.In the embodiments of the present invention, the quantity of the second mask layer 72a is can be with Variation.Mask pattern 70a may include multiple second mask layer 72a, these the second mask layer 72a are being parallel to the first mask The direction of the first edge E1 of layer 71a is separated from each other.First edge E1 is the edge far from core space.Mask pattern can be light Hinder material.Can by covering complete photoresist layer on stack layer 810, after then photomask can be used to carry out photoetching, into Row etching, obtains mask pattern 70a as shown in figs. 7 a-b.Here, photomask has the firstth area of corresponding first mask layer The second area in domain and corresponding second mask layer, pattern are substantially similar to shown in Fig. 7 A.

In step 606, using the predetermined thickness of mask pattern removal stack layer, and in the first edge of the first mask layer and The surrounding of second mask layer forms initial step.

Here, the first film layer of part exposed on stack layer can be removed, thus in the first mask under mask pattern protection The first edge of layer forms initial step, and forms initial step in the surrounding of the second mask layer.

In the sectional view of semiconductor structure 800c exemplified by Fig. 8 C, the first mask layer 71a of mask pattern 70a is used With the predetermined thickness of the second mask layer 72a removal stack layer 810, the thickness of for example, one film layer, to remove stack layer 810 Upper exposed the first film layer of part 811, is allowed to be reduced into 811a.At this point, being formed just in the first edge E1 of the first mask layer 71a Beginning ladder S0, and initial step S0 is formed in the surrounding of the second mask layer 72a.Remove the first film layer of part of stack layer 810 811 mode can be etching.Semiconductor structure 800c to this step can be with reference to shown in Fig. 9 B, and which show diminutions First film layer 811a and initial step S0.In the example of Fig. 9 B, two the second mask layers have been used, have formd 2 subregion ranks Terraced structural area SDS.

In step 606, mask pattern is modified, reduces the first edge of the first mask layer to the direction close to core space, And reduce the second mask layer from four circumferential centers.

Since this step, typical finishing/etching technics can be used to form hierarchic structure step by step.In this step, Mask pattern can be modified, is allowed to reduce the width of a ladder, so as to the new hierarchic structure of the region etch in exposing.

As shown in Fig. 7 B and Fig. 8 D, mask pattern 70a is modified in semiconductor structure 800d, makes it to close to core space Direction (left in Fig. 8 D) reduces, and becomes mask pattern 70b.First mask layer 71b has retreated one to the direction close to core space The width of a ladder, the second mask layer 72b has retreated the width of a ladder from the four circumferential directions close to its center, to reveal A part of the first film layer 811a reduced out.

In step 608, using the predetermined thickness of stack layer described in the mask pattern after finishing, and in first mask layer First edge and the second mask layer surrounding formed the first ladder, and the position of initial step formed the second ladder.

In this step, exposed the first film layer of part on stack layer can be removed under mask pattern protection after conditioning With the second film layer, so that the first ladder is formed in the first edge of the first mask layer and the surrounding of the second mask layer, and initial The second ladder that the position of ladder is formed.

As illustrated in fig. 8e, the part of the mask pattern 70b removal stack layer after finishing is used in semiconductor structure 800e Thickness, a part including continuing the first film layer 811a after the diminution that is exposed of removal are allowed to further reduce as 811b, thus The first ladder S1 is formed in the first edge E1 of the first mask layer 71b and the surrounding of the second mask layer.Remove second to be exposed Film layer 812 is allowed to be reduced into 812a, thus the second ladder S2 formed in the position of initial step S0.To partly leading for this step The perspective view of body structure 800e can refer to shown in Fig. 9 C, which show the first film layer 811b further reduced, reduce the Two film layer 811a, the first ladder S1 and the second ladder S2.One of the first film layer 811a after reducing can be removed by photoetching herein Part and the second film layer 812 being exposed.

In the methods described above, only a photomask need to be used in step 604, carries out a photoetching, therefore can save Lithography step and a photomask, simplify the manufacture craft of three-dimensional storage.

Flow chart has been used to be used to illustrate operation performed by method according to an embodiment of the present application herein.It should be understood that , the operation of front not necessarily accurately carries out in sequence.On the contrary, various steps can be handled according to inverted order or simultaneously Suddenly.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.

Above-described embodiment is formed by semiconductor structure, and using subsequent conventional steps, three-dimensional storage can be obtained Part.Such as after forming structure shown in Fig. 8 E and 9C, by the alternately predetermined thickness of removal stack layer and mask pattern is modified, The side of the first edge of first mask layer is upwardly formed multistage ladder.Here, modify/etch according to common process, Obtain hierarchic structure as shown in fig. 9d.It is practical according to this that semiconductor structure 800F description is formed by with reference to the present embodiment herein The three-dimensional storage of a novel embodiment.Three-dimensional storage may include core space (not shown) and stepped region.Stepped region Ke Bao Include the subregion hierarchic structure area SDS of top selection area TSG and 2 separation.Top selection area TSG has the first ladder S1 and the Two ladder S2, the first ladder S1 are higher than the second ladder S2 and compare the second ladder S2 closer to core space.Subregion hierarchic structure area SDS Also there is the first ladder S1 and the second ladder S2, the first ladder S1 to be higher than the second ladder S2 and compare the second ladder S1 further from top Select area TSG.Here, the first ladder S1 and the second ladder S2 in subregion hierarchic structure area SDS only refer to the rank of extreme higher position Ladder.Here, the first identical, the second ladder S2 height of ladder S1 height of top selection area TSG and subregion hierarchic structure area SDS Also identical.Top selects between area TSG and subregion hierarchic structure area SDS as the plane lower than the second ladder S2.Therefore, stepped region From the direction far from core space, height first gradually declines, then gradually rises.

In conjunction with shown in reference Fig. 9 D and Figure 10, in the area SDS, the extending direction of the first edge E1 of TSG in top selection area In (Y-direction in figure), each subregion hierarchic structure area SDS forms 3 different subregions of height, the difference in height between adjacent sectors For the height of 1 ladder.It returns to shown in Fig. 9 D, subregion hierarchic structure area SDS may also include to be selected to far from top along the X direction Multiple ladder S of the direction decline of area TSG.X-direction and Y-direction are mutually perpendicular to.The series of these ladders S and three-dimensional storage The number of plies is related.

In the embodiments of the present invention, the first ladder S1 and/or the second ladder S2 may include a pair of or multipair heap Folded grid layer and dielectric layer.In some embodiments, the quantity of the first ladder S1 and/or the grid layer in the second ladder S2 It is also possible to odd number, dielectric layer is also such.The grid layer of top selection area TSG constitutes top selection grid.

As it was noted above, the quantity of subregion hierarchic structure area SDS can change, such as subregion hierarchic structure area SDS It can be one, it can also be with more than two.

Other details of three-dimensional storage part, such as structure, the periphery interconnection of storage array etc., not the utility model Emphasis, herein not reinflated description.

In the context of the utility model, three-dimensional storage part can be 3D flash memory, such as 3D NAND flash memory.

The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ", And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or " alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application Feature, structure or feature can carry out combination appropriate.

Although the utility model is disclosed as above with preferred embodiment, so it is not intended to limit the utility model, any Those skilled in the art, without departing from the spirit and scope of the utility model, when can make a little modification and it is perfect, therefore this The protection scope of utility model, which is worked as, to be subjected to the definition of the claims.

Claims (10)

1. a kind of three-dimensional storage, it is characterised in that including core space and stepped region, the stepped region have top selection area and Subregion hierarchic structure area, top selection area and subregion hierarchic structure area have identical first ladder of height, and have There is identical second ladder of height；Wherein in top selection area, first ladder is higher than second ladder and compares institute The second ladder is stated closer to the core space；In subregion hierarchic structure area, first ladder is higher than second ladder And than second ladder further from top selection area.

2. three-dimensional storage as described in claim 1, which is characterized in that the stepped region includes the subregion of multiple separation Hierarchic structure area.

3. three-dimensional storage as described in claim 1, which is characterized in that first ladder and/or the second ladder are including extremely Few a pair of grid layer and dielectric layer stacked.

4. three-dimensional storage as described in claim 1, which is characterized in that top selection area and the subregion hierarchic structure It is the plane lower than second ladder between area.

5. three-dimensional storage as described in claim 1, which is characterized in that subregion hierarchic structure area includes in a first direction Multiple subregions of upper distribution, each subregion include the multiple ranks declined in a second direction to the direction far from top selection area Ladder, for the first direction perpendicular to the second direction, the second direction is the extending direction of the stepped region.

6. three-dimensional storage as claimed in claim 5, which is characterized in that each ladder of the multiple ladder includes at least one To the grid layer and dielectric layer of stacking.

7. the three-dimensional storage as described in claim 3 or 6, which is characterized in that the grid layer with perpendicular to the grid layer Contact portion electrical connection.

8. three-dimensional storage as claimed in claim 5, which is characterized in that the difference in height of adjacent sectors is in the multiple subregion The height of one ladder.

9. three-dimensional storage as described in claim 1, which is characterized in that the stepped region is arranged in the side of the core space Or opposite sides.

10. three-dimensional storage as claimed in claim 2, which is characterized in that the three-dimensional storage is 3DNAND flash memory.