CN112259516A - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
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- CN112259516A CN112259516A CN201910659765.9A CN201910659765A CN112259516A CN 112259516 A CN112259516 A CN 112259516A CN 201910659765 A CN201910659765 A CN 201910659765A CN 112259516 A CN112259516 A CN 112259516A
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- chip
- boss
- metal sheet
- conductive metal
- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004806 packaging method and process Methods 0.000 title claims description 11
- 239000000853 adhesive Substances 0.000 claims abstract description 10
- 230000001070 adhesive effect Effects 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 77
- 239000002184 metal Substances 0.000 claims description 77
- 239000012790 adhesive layer Substances 0.000 claims description 45
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000002265 prevention Effects 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 9
- 238000012360 testing method Methods 0.000 description 14
- 239000010410 layer Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 230000009194 climbing Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003685 thermal hair damage Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
Abstract
The application provides a semiconductor package structure, semiconductor package structure includes chip, first electrically conductive sheetmetal and connection the chip with the first electrically conductive adhesive linkage of first electrically conductive sheetmetal, a surface of chip is equipped with source electrode region, first electrically conductive sheetmetal includes first boss and first convex closure, first boss is located face to in the first electrically conductive sheetmetal the regional one side of source electrode of chip, just first boss corresponds to the regional setting of source electrode of chip, first convex closure is located face to in the first boss the regional one side of source electrode of chip, just first convex closure is to being close to the direction of chip extends. This application is through setting up first boss and first convex closure to guarantee the uniformity of the thickness of the first electrically conductive adhesive linkage between chip and the first electrically conductive sheetmetal, reached the beneficial effect that improves the reliability of product.
Description
Technical Field
The present application relates to the field of semiconductors, and more particularly, to a semiconductor package structure.
Background
With the continuous development of the semiconductor industry, the demand of people on semiconductors is higher and higher, the electrical performance of the semiconductors is expected to be better, and the manufacturing cost can be smaller and smaller. In order to better meet the market demand, the chip design development end continuously improves the chip design, and meanwhile, higher requirements are also put forward on the package design development end. The packaging resistance of the development end of the packaging design is required to be smaller and smaller, the current is higher, and the heat conducting performance is better.
The existing copper sheet structure faces the problems of large packaging resistance, poor heat-conducting property and difficulty in meeting the requirement of high reliability.
In the existing semiconductor packaging structure, the problem that the thickness of solder paste between a chip and a copper sheet is difficult to control and is completely consistent in the heating and climbing process exists, so that certain risks exist in the reliability of products.
Disclosure of Invention
The invention provides a semiconductor packaging structure for improving the reliability of products.
To achieve the above objective, embodiments of the present invention provide a semiconductor package structure. This semiconductor package structure includes chip, first electrically conductive sheetmetal and connection the chip with the first electrically conductive adhesive linkage of first electrically conductive sheetmetal, a surface of chip is equipped with the source electrode region, first electrically conductive sheetmetal includes first boss and first convex closure, first boss is located face in the first electrically conductive sheetmetal towards the regional one side of source electrode of chip, just first boss corresponds to the regional setting of source electrode of chip, first convex closure is located face in the first boss towards the regional one side of source electrode of chip, just first convex closure is to being close to the direction extension of chip.
Optionally, the first convex hull is located in a central region of the first boss.
Optionally, a first through hole is formed in the first convex hull, the first through hole penetrates through the first conductive metal sheet along the thickness direction of the first conductive metal sheet, and the first conductive adhesive layer is partially penetrated in the first through hole.
Optionally, the number of the first convex hulls is multiple, and the first convex hulls are arranged in the central area of the first boss at intervals.
Optionally, the center of the first boss coincides with the center of the source region of the chip.
Optionally, the first conductive metal sheet further includes:
the first main body is arranged on the chip in a covering mode, the orthographic projection of the first main body is located inside the outer periphery of the chip, and the first boss is arranged on the first main body;
one end of the first connecting part is connected with the first main body, and the other end of the first connecting part extends in the direction far away from the first main body;
and one end of the first lead part is connected with the first connecting part, and the other end of the first lead part extends towards the direction far away from the first connecting part.
Optionally, the first main body comprises a spill-proof portion, the spill-proof portion is arranged around the outer periphery of the first boss, the width of the spill-proof portion is greater than 0.2mm, and the distance from the outer periphery of the spill-proof portion to the outer periphery of the chip is greater than 0.1 mm; and/or the presence of a gas in the gas,
the first connecting part is provided with a pair of through holes; and/or the presence of a gas in the gas,
one end of the first lead part, which is far away from the first connecting part, is provided with a groove.
Optionally, a gate region is disposed on one surface of the chip, the semiconductor package structure further includes a second conductive metal sheet and a second conductive adhesive layer connecting the chip and the second conductive metal sheet, and the second conductive metal sheet is disposed corresponding to the gate region of the chip and insulated from the first conductive metal sheet; the second conductive metal sheet comprises a second boss, the second boss is arranged on one surface, facing the grid region of the chip, of the second conductive metal sheet, and the second boss corresponds to the grid region of the chip.
Optionally, the second conductive metal sheet further includes a second convex hull, the second convex hull is disposed on a surface of the second boss facing the gate region of the chip, and the second convex hull extends in a direction close to the chip.
Optionally, the second convex hull is located in a central region of the second boss; and/or the presence of a gas in the gas,
and a second through hole is formed in the second convex hull, the second through hole penetrates through the second conductive metal sheet along the thickness direction of the second conductive metal sheet, and the second conductive adhesive layer is partially arranged in the second through hole in a penetrating manner.
In the semiconductor package structure of the embodiment, the first boss is arranged to ensure that the first conductive adhesive layer between the chip and the first conductive metal sheet can reach a consistent thickness in a heating and climbing process; the first convex hull is arranged on the surface, facing the source electrode area of the chip, of the first boss, so that the first conductive bonding layer between the chip and the first boss is extruded through the first convex hull, the consistency of the thickness of the first conductive bonding layer between the chip and the first conductive metal sheet is ensured, and the beneficial effect of improving the reliability of a product is achieved; simultaneously, through setting up first convex closure and increased the area of contact between first electrically conductive sheetmetal and the chip to reach and reduce the encapsulation resistance, improved the beneficial effect of thermal conductivity.
Drawings
Fig. 1 is a schematic perspective view of a semiconductor package structure according to an exemplary embodiment of the present invention, when a chip, a first metal sheet, and a second metal sheet are assembled together.
Fig. 2 is a schematic top view of a semiconductor package structure according to an exemplary embodiment of the invention.
Fig. 3 is a schematic perspective view of another angle of the first metal sheet and the second metal sheet of the semiconductor package structure according to an exemplary embodiment of the invention.
Fig. 4 is a schematic bottom view of a first metal sheet and a second metal sheet of a semiconductor package structure according to an exemplary embodiment of the invention.
Fig. 5 is a schematic sectional view in the direction of a-a in fig. 4.
Fig. 6 is a schematic sectional view in the direction B-B in fig. 4.
Description of the reference numerals
First conductive metal sheet 20
First convex hull 22
First through hole 23
To the through hole 251
Second conductive metal sheet 30
Second through hole 33
Second connecting portion 35
Height H1 of first boss
Height h1 of first convex hull
Height H2 of second boss
Height h2 of second convex hull
Thickness direction T of first conductive metal sheet
Thickness direction t of the second conductive metal sheet
Width d of the spill-proof part
Distance D from outer periphery of overflow preventing part to outer periphery of chip
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "plurality" includes two, and is equivalent to at least two. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
As shown in fig. 1 to 6, an embodiment of the invention provides a semiconductor package structure. The semiconductor package structure includes a chip 10, a first conductive metal sheet 20, a first conductive adhesive layer (not shown), a second conductive metal sheet 30, and a second conductive adhesive layer (not shown).
The first conductive adhesive layer is connected between the chip 10 and the first conductive metal sheet 20. The second conductive adhesive layer (not labeled) is connected between the chip 10 and the second conductive metal sheet 30. In this embodiment, the first conductive adhesive layer and the second conductive adhesive layer are made of tin metal, but not limited to tin metal, and may be other metals. The first conductive metal sheet 20 and the second conductive metal sheet 30 are made of copper metal, but not limited to copper metal, and may be other metals.
A surface of the chip 10 is provided with a source region (not shown) and a gate region (not shown), respectively. The first conductive metal sheet 20 is disposed corresponding to the source region, the second conductive metal sheet 30 is disposed corresponding to the gate region of the chip 10, and the second conductive metal sheet 30 and the first conductive metal sheet 20 are insulated and isolated from each other.
The first conductive metal sheet 20 includes a first boss 21 and a first convex hull 22.
The first bump 21 is disposed on a surface of the first conductive metal sheet 20 facing the source region of the chip 10, and the first bump 21 is disposed corresponding to the source region of the chip 10. When the area of the first conductive metal sheet 20 corresponding to the source region of the chip 10 is a planar structure, during the heat climbing process of the first conductive adhesive layer connecting the chip 10 and the first conductive metal sheet 20, the thickness is easily inconsistent, and thus, the inventor of the present application proposes that a first bump 21 is disposed on the side of the first conductive metal sheet 20 facing the gate region of the chip 10, where the first bump 21 is disposed corresponding to the source region of the chip 10. Thus, by arranging the first boss 21, the distance between the plane where the chip 10 is located and the first conductive metal sheet 20 is shortened, so that the first conductive adhesive layer within the coverage range of the first boss 21 can be ensured to reach a consistent thickness in the heating and climbing process. The center of the first boss 21 coincides with the center of the source region of the chip 10, so as to achieve the beneficial effect of making the stress on the chip 10 more uniform. The shape of the first bump 21 is not limited in this embodiment, and the shape of the first bump 21 is set with respect to the source region of the chip 10.
In the present embodiment, the height H1 of the first boss 21 is 65um-85 um.
The first convex hulls 22 are disposed on a surface of the first boss 21 facing the source region of the chip 10, and the first convex hulls 22 extend in a direction close to the chip 10. In this way, the first convex hull 22 is arranged on the surface of the first boss 21 facing the source region of the chip 10, so that the first conductive adhesive layer between the chip 10 and the first boss 21 is extruded by the first convex hull 22, the consistency of the thickness of the first conductive adhesive layer between the chip 10 and the first conductive metal sheet 20 is ensured, and the beneficial effect of improving the reliability of the product is achieved; meanwhile, the contact area between the first conductive metal sheet 20 and the chip 10 is increased by providing the first convex hulls 22, so that the beneficial effects of reducing the packaging resistance and improving the heat conductivity are achieved.
Preferably, the first convex hull 22 is located in a central region of the first boss 21. Thus, by arranging the first convex hull 22 in the central area of the first boss 21, the problems that the thickness of the first conductive adhesive layer is not equal and the product is not flat due to the included angle between the first conductive metal sheet 20 and the plane where the chip 10 is located caused by the arrangement of the first convex hull 22 can be avoided. The number of first convex hulls 22 may be one, or two, or other values, depending on design requirements. When the number of the first convex hulls 22 is plural, the plural first convex hulls 22 are arranged at the central area of the first boss 21 at intervals to ensure that the first conductive metal sheet 20 is parallel to the plane where the chip 10 is located.
The height h1 of the first convex hull 22 is greater than 20um, so that the problem of short circuit caused by deformation of the aluminum layer of the chip 10 in high and low temperature cycle test examination of the semiconductor packaging structure can be solved. Preferably, the height h1 of the first convex hull 22 is greater than 30um, so that the problem of drain and source leakage current caused by stress release in the high-temperature gate bias test of the semiconductor package structure can be solved. This is because: the inventor(s) have found through a large number of experiments that, in the high-low temperature cycle test examination, when the height h1 of the first convex hull 22 is less than 20um, the aluminum layer of the chip 10 is deformed; when the height h1 of the first convex hull 22 is greater than 20um and less than 30um, the phenomenon of deformation of the aluminum layer of the chip disappears when the product is tested and examined in a high-low temperature cycle test, but the phenomenon of drain current and source current leakage easily occurs when the product is tested and examined in a high-temperature gate bias test; when the height h1 of the first convex hull 22 is larger than 30um, the phenomenon of deformation of the aluminum layer of the chip disappears when the product is examined in a high-low temperature cycle test, and the phenomenon of leakage current of the drain electrode and the source electrode disappears when the product is examined in a high-temperature grid deflection test.
More preferably, the height h1 of the first convex hull 22 is 30um-55 um. In this way, by setting the height h1 of the first convex hull 22 to 30um-55um, the thickness of the first conductive adhesive layer can be ensured. This is because the first convex hull 22 has only a very thin layer of the first conductive adhesive layer (thickness is between 1um-2 um) on the side close to the chip 10, and the height h1 of the first convex hull 22 is slightly smaller than the thickness of the first conductive adhesive layer between the chip 10 and the first boss 21, so that the thickness of the first conductive adhesive layer can be ensured by setting the height h1 of the first convex hull 22. When the height h1 of first convex closure 22 is 30um-55um, the thickness of first electrically conductive adhesive linkage can reach 31um-57um, this thickness first electrically conductive adhesive linkage can cushion the thermal stress on the chip 10 well, avoids chip 10 to produce the inner structure under the effect of thermal stress and damages.
In this embodiment, the first convex hull 22 is provided with a first through hole 23, the first through hole 23 penetrates the first conductive metal sheet 20 along the thickness direction T of the first conductive metal sheet 20, and the first conductive adhesive layer is partially disposed in the first through hole 23. Like this, through setting up first through-hole 23, be convenient for in time detect the condition of the first electrically conductive adhesive linkage on chip 10 surface before the backward flow, make first electrically conductive adhesive linkage partially wear to locate in first through-hole 23 simultaneously, form bigger contact surface and increase whole cohesion. Furthermore, the first through hole 23 increases the contact area between the first conductive metal sheet 20 and the chip 10, so that the beneficial effects of reducing the package resistance and improving the thermal conductivity are also achieved. Preferably, the diameter of the first through hole 23 is greater than 0.2mm and smaller than the diameter of the first convex hull 22.
Specifically, the first conductive metal sheet 20 includes: a first body 24, a first connection portion 25, and a first lead portion 26. In order to distinguish the first body 24 and the first connection portion 25 more clearly, both are divided by a dotted line in fig. 2 and 4, but the dotted line does not exist in an actual structure.
The first body 24 is disposed on the chip 10, and an orthogonal projection of the first body 24 is located inside an outer periphery of the chip 10, and the first bump 21 is disposed on the first body 24. The first body 24 includes a non-spill portion 241, the non-spill portion 241 being disposed around an outer peripheral edge of the first boss 21, a width D of the non-spill portion 241 being greater than 0.2mm, and a spacing D of the outer peripheral edge of the non-spill portion 241 to an outer peripheral edge of the chip 10 being greater than 0.1 mm. Therefore, on one hand, the width d of the anti-overflow part 241 is set to be larger than 0.2mm, so that the control on the usage amount of the first conductive adhesive layer can be achieved, the sufficient first conductive adhesive layer cannot overflow to other areas in the welding process, and only the first conductive adhesive layer can overflow to the area covered by the anti-overflow part 241, so that the overall binding force of the product is increased; on the other hand, by setting the distance D between the outer periphery of the overflow preventing portion 241 and the outer periphery of the chip 10 to be greater than 0.1mm, and by leaving a distance between the outer periphery of the overflow preventing portion 241 and the outer periphery of the chip 10, the first conductive adhesive layer is prevented from contacting other areas during climbing to cause a short circuit of the product.
The first connecting portion 25 has one end connected to the first body 24 and the other end extending in a direction away from the first body 24. The first connecting portion 25 has a through hole 251. Through the arrangement of the pair of through holes 251, the overall fluidity of the plastic package material is increased during filling in the subsequent plastic package process; after the molding compound is filled, the molding compound forms two supporting posts at the positions corresponding to the through holes 251, so that the stress release of the molding compound to the chip 10 is reduced. Preferably, the opposite through holes 251 are disposed in the middle of the first connecting portion 25, so as to better achieve the beneficial effect of increasing the overall fluidity.
One end of the first lead portion 26 is connected to the first connection portion 25, and the other end extends in a direction away from the first connection portion 25. The end of the first lead portion 26 away from the first connection portion 25 is formed with a groove 261 to facilitate the discharge of bubbles generated during the reflow process of the first conductive adhesive layer.
The second conductive metal sheet 30 includes: a second body 34, a second connecting portion 35, and a second lead portion 36. The second body 34 is disposed on the chip 10, and the orthographic projection of the second body 34 is located within the outer periphery of the chip 10. The second connecting portion 35 has one end connected to the second body 34 and the other end extending in a direction away from the second body 34. One end of the second lead portion 36 is connected to the second connection portion 35, and the other end extends in a direction away from the second connection portion 35. In order to distinguish the second body 34 and the second connection portion 35 more clearly, both are divided by a dotted line in fig. 2 and 4, and the dotted line does not exist in an actual structure.
In the prior art, the second conductive metal sheet 30 disposed relative to the gate region of the chip 10 has a limited area, and the second body 34 generally has a planar structure, so that during the heat climbing process of the second conductive adhesive layer connecting the chip 10 and the second conductive metal sheet 30, the thickness is easily inconsistent, and therefore, the inventor of the present application proposes that the second bump 31 is disposed on the surface of the second body 34 of the second conductive metal sheet 30 facing the gate region of the chip 10, and the second bump 31 is disposed corresponding to the gate region of the chip 10. In this way, by providing the second bump 31 on the surface of the second body 34 facing the source region of the chip 10, the distance between the plane of the chip 10 and the second conductive metal sheet 30 is shortened, so that the thickness uniformity of the second conductive adhesive layer within the coverage of the second bump 31 can be ensured. In the present embodiment, due to the size limitation of the second conductive metal sheet 30 itself, the second bump 31 has a circular shape to better cover the gate region of the corresponding chip 10.
In the present embodiment, the height H2 of the second boss 31 is 65um-85 um.
Preferably, the second conductive metal sheet 30 further includes a second convex hull 32, the second convex hull 32 is disposed on a surface of the second bump 31 facing the gate region of the chip 10, and the second convex hull 32 extends toward the chip 10. In this way, the second conductive adhesive layer between the chip 10 and the second boss 21 can be extruded by the second convex hull 32, so that the consistency of the thickness of the second conductive adhesive layer between the chip 10 and the second conductive metal sheet 30 is ensured, and the beneficial effect of only improving the reliability of the product in one step is achieved.
Preferably, the second convex hull 32 is located in a central region of the second boss 31. Therefore, by arranging the second convex hull 32 in the central area of the second boss 31, the problems that the thickness of the second conductive adhesive layer is not equal, the product is not flat and the like due to the fact that the second convex hull 32 is arranged, an included angle is formed between the second conductive metal sheet 30 and the plane where the chip 10 is located can be avoided.
The height h2 of the second convex hull 32 is greater than 20um, so that the problem of short circuit caused by deformation of the aluminum layer of the chip 10 in high-low temperature cycle test examination of the semiconductor packaging structure can be solved. Preferably, the height h2 of the second convex hull 32 is greater than 30um, so that the problem of drain and source leakage current caused by stress release in the high-temperature gate bias test of the semiconductor package structure can be solved. This is because: the inventor(s) have found through a large number of experiments that, in the high-low temperature cycle test examination, when the height h2 of the second convex hull 32 is less than 20um, the aluminum layer of the chip 10 is deformed; when the height h2 of the second convex hull 32 is greater than 20um and less than 30um, the phenomenon of deformation of the aluminum layer of the chip disappears when the product is tested and examined in a high-low temperature cycle test, but the phenomenon of drain current and source current leakage easily occurs when the product is tested and examined in a high-temperature gate bias test; when the height h2 of the second convex hull 32 is larger than 30um, the phenomenon of deformation of the aluminum layer of the chip disappears when the product is examined in a high-low temperature cycle test, and the phenomenon of leakage current of the drain electrode and the source electrode disappears when the product is examined in a high-temperature grid deflection test.
More preferably, the height h2 of the second convex hull 32 is 30um-55 um. In this way, by setting the height h2 of the second convex hull 32 to 30um-55um, the thickness of the second conductive adhesive layer can be ensured. This is because the second convex hull 32 has only a very thin layer of the second conductive adhesive layer (thickness between 1um and 2 um) on the side close to the chip 10, and the height h2 of the second convex hull 32 is slightly smaller than the thickness of the second conductive adhesive layer between the chip 10 and the first bump 21, so that the thickness of the first conductive adhesive layer can be ensured by setting the height h2 of the second convex hull 32. When the height h2 of second convex hull 32 is 30um-55um, the thickness of the second conductive adhesive layer can reach 31um-57um, this thickness the second conductive adhesive layer can buffer the thermal stress on chip 10 well, avoids chip 10 to produce the inner structure under the effect of thermal stress and damages.
Optionally, the second convex hull 32 is provided with a second through hole 33, the second through hole 33 penetrates through the second conductive metal sheet 30 along the thickness direction t of the second conductive metal sheet 30, and the second conductive adhesive layer partially penetrates through the second through hole 33. Like this, through setting up second through-hole 33, be convenient for before the backward flow in time detect the chip 10 surface the condition of the electrically conductive adhesive linkage of second makes simultaneously during the electrically conductive adhesive linkage part of second wears to locate second through-hole 33, forms bigger contact surface and increases whole cohesion. Preferably, the diameter of the second through hole 33 is greater than 0.2mm and smaller than the diameter of the second convex hull 32.
In addition, it should be noted that, in the prior art, since the area of the gate region of the chip 10 is limited, it is difficult to control the amount of the second conductive adhesive layer, and usually the second conductive adhesive layer is easily excessive, so that the second conductive adhesive layer overflows to other regions during the soldering process, which causes the second conductive adhesive layer to splash or the second conductive adhesive layer is connected to the outside of the gate region of the chip 10, which causes a product short circuit.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (10)
1. The utility model provides a semiconductor packaging structure, includes chip, first electrically conductive sheetmetal and connection the chip with the first electrically conductive adhesive linkage of first electrically conductive sheetmetal, a surface of chip is equipped with the source region, its characterized in that, first electrically conductive sheetmetal includes first boss and first convex closure, first boss is located face in the first electrically conductive sheetmetal to the regional one side of source electrode of chip, just first boss correspond to the regional setting of source electrode of chip, first convex closure is located face in the first boss to the regional one side of source electrode of chip, just first convex closure is to being close to the direction extension of chip.
2. The semiconductor package structure of claim 1, wherein the first convex hull is located in a central region of the first boss.
3. The semiconductor package structure of claim 1, wherein the first convex hull has a first through hole formed therein, the first through hole penetrating the first conductive metal sheet along a thickness direction of the first conductive metal sheet, and the first conductive adhesive layer partially penetrating the first through hole.
4. The semiconductor package structure of claim 1, wherein the first bump is plural in number, and the plural first bumps are disposed at intervals in a central region of the first boss.
5. The semiconductor package structure of claim 1, wherein a center of the first boss coincides with a center of a source region of the chip.
6. The semiconductor package structure of claim 1, wherein the first conductive metal sheet further comprises:
the first main body is arranged on the chip in a covering mode, the orthographic projection of the first main body is located inside the outer periphery of the chip, and the first boss is arranged on the first main body;
one end of the first connecting part is connected with the first main body, and the other end of the first connecting part extends in the direction far away from the first main body;
and one end of the first lead part is connected with the first connecting part, and the other end of the first lead part extends towards the direction far away from the first connecting part.
7. The semiconductor package structure of claim 6, wherein the first body comprises a no-flow prevention portion disposed around an outer periphery of the first boss, the no-flow prevention portion having a width greater than 0.2mm, and a spacing from the outer periphery of the no-flow prevention portion to an outer periphery of the chip greater than 0.1 mm; and/or the presence of a gas in the gas,
the first connecting part is provided with a pair of through holes; and/or the presence of a gas in the gas,
one end of the first lead part, which is far away from the first connecting part, is provided with a groove.
8. The semiconductor package structure according to claim 1, wherein a gate region is formed on a surface of the chip, the semiconductor package structure further comprises a second conductive metal sheet and a second conductive adhesive layer connecting the chip and the second conductive metal sheet, the second conductive metal sheet is disposed corresponding to the gate region of the chip and is insulated and isolated from the first conductive metal sheet; the second conductive metal sheet comprises a second boss, the second boss is arranged on one surface, facing the grid region of the chip, of the second conductive metal sheet, and the second boss corresponds to the grid region of the chip.
9. The semiconductor package structure of claim 8, wherein the second conductive metal sheet further comprises a second convex hull, the second convex hull is disposed on a side of the second boss facing the gate region of the chip, and the second convex hull extends in a direction closer to the chip.
10. The semiconductor package structure of claim 9, wherein the second convex hull is located in a central region of the second boss; and/or the presence of a gas in the gas,
and a second through hole is formed in the second convex hull, the second through hole penetrates through the second conductive metal sheet along the thickness direction of the second conductive metal sheet, and the second conductive adhesive layer is partially arranged in the second through hole in a penetrating manner.
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| CN201910659765.9A CN112259516A (en) | 2019-07-22 | 2019-07-22 | Semiconductor packaging structure |
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| US20010044167A1 (en) * | 2000-05-18 | 2001-11-22 | Frank Kuo | Power semiconductor package and method for making the same |
| CN101720504A (en) * | 2007-04-30 | 2010-06-02 | 万国半导体股份有限公司 | Semiconductor package having dimpled plate interconnections |
| CN102437138A (en) * | 2010-09-29 | 2012-05-02 | 三菱电机株式会社 | Semiconductor device |
| CN206116387U (en) * | 2016-09-26 | 2017-04-19 | 无锡新洁能股份有限公司 | Big current power semiconductor device's packaging structure |
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| US20010044167A1 (en) * | 2000-05-18 | 2001-11-22 | Frank Kuo | Power semiconductor package and method for making the same |
| CN101720504A (en) * | 2007-04-30 | 2010-06-02 | 万国半导体股份有限公司 | Semiconductor package having dimpled plate interconnections |
| CN102437138A (en) * | 2010-09-29 | 2012-05-02 | 三菱电机株式会社 | Semiconductor device |
| CN206116387U (en) * | 2016-09-26 | 2017-04-19 | 无锡新洁能股份有限公司 | Big current power semiconductor device's packaging structure |
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