CN217280756U - Lead frame and chip packaging product - Google Patents

Lead frame and chip packaging product Download PDF

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Publication number
CN217280756U
CN217280756U CN202220297766.0U CN202220297766U CN217280756U CN 217280756 U CN217280756 U CN 217280756U CN 202220297766 U CN202220297766 U CN 202220297766U CN 217280756 U CN217280756 U CN 217280756U
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China
Prior art keywords
edge
base
conductive layer
lead
chip
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CN202220297766.0U
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Chinese (zh)
Inventor
华璋
陈达志
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Advanced Semiconductor Materials Anhui Co ltd
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Advanced Semiconductor Materials Anhui Co ltd
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Priority to CN202220297766.0U priority Critical patent/CN217280756U/en
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Priority to TW112201234U priority patent/TWM644421U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The embodiment of the present disclosure provides a lead frame and a chip package product, wherein the lead frame is suitable for bearing and fixing a chip, and comprises: a base adapted to carry a chip; the pin is suitable for leading out an electrode of the chip; the first surface of the base is formed with a first conductive layer, the first surface of the base includes an edge, and a first distance is provided between the edge of the first conductive layer and a corresponding edge of the first surface of the base. The lead frame and the chip packaging product provided by the embodiment of the disclosure can reduce the risk of delamination between the packaging body material and the lead frame, improve the delamination problem between the packaging body material and the lead frame, and improve the packaging reliability of the packaging device.

Description

Lead frame and chip packaging product
Technical Field
The present disclosure relates to the field of integrated circuit packaging, and more particularly, to a lead frame and a chip package product.
Background
In the packaging process of the integrated circuit, the lead frame provides mechanical and electrical connection between the integrated circuit and the circuit board. Generally, in order to meet the functional requirements of chip connection and wire bonding, a metal layer is plated on a specific area of the lead frame, such as a metal layer on the base and the leads. After the chip connection and the wire bonding are completed, the chip and the metal bonding wire need to be packaged by using a packaging material to protect the internal structure.
Because the thermal expansion coefficients of the packaging material, the chip and the lead frame are not matched, internal stress can be generated among the plastic packaging material, the chip and the lead frame under the influence of injection molding, external environment temperature change or chip operation heating. These internal stresses can cause delamination of the internal structure, reduce the useful life of the packaged device, and even cause failure of the packaged device.
Therefore, there is a need to improve the delamination between the packaging material and the lead frame to prevent the chip package product from delamination and other problems such as failure of the packaged device.
SUMMERY OF THE UTILITY MODEL
In order to improve the layering problem between the packaging material and the lead frame and improve the packaging reliability of the packaged device, the embodiment of the disclosure provides the lead frame and a chip packaging product.
Embodiments of the present disclosure provide a lead frame adapted to carry and fix a chip, the lead frame including: a base adapted to carry a chip; the pin is suitable for leading out an electrode of the chip; the first surface of the base is formed with a first conductive layer, the first surface of the base comprises an edge, and a first distance is reserved between the edge of the first conductive layer and the edge corresponding to the first surface of the base.
In some embodiments, the first distance ranges from 0.025mm to 0.1 mm.
In some embodiments, the lead has a spacing from the base, the first surface of the lead includes a first edge, the first edge is the edge of the lead closest to the base, the first surface of the lead is formed with a second conductive layer, and the second conductive layer has a second distance from the first edge of the lead.
In some embodiments, the first surface of the pin includes a second edge adjacent to the first edge of the pin, and the second conductive layer of the first surface of the pin has a third distance from the second edge of the pin.
In some embodiments, the second and third distances range from 0.025mm to 0.1 mm.
In some embodiments, the adhesion between the base material and the encapsulating leadframe material is greater than the adhesion between the first conductive layer and the encapsulating leadframe material; the adhesion between the pin material and the package lead frame material is greater than the adhesion between the second conductive layer and the package lead frame material.
In some embodiments, the first and second conductive layers are comprised of silver or nickel palladium gold, and the base and leads of the leadframe are comprised of a copper alloy.
Embodiments of the present disclosure also provide a chip package product, which includes: a chip; a base adapted to carry the chip; the pins are suitable for leading out electrodes of the chip and are arranged on the periphery of the base; a package adapted to encapsulate the chip, the base, the bonding wires, and a portion of the leads; the first surface of the base is formed with a first conductive layer, the first surface of the base includes an edge, and a first distance is provided between the edge of the first conductive layer and a corresponding edge of the first surface of the base.
In some embodiments, the first distance ranges from 0.025mm to 0.1 mm.
In some embodiments, the lead and the base have a space therebetween, the first surface of the lead includes a first edge, the first edge is an edge of the lead closest to the base, the first surface of the lead is formed with a second conductive layer, and the second conductive layer has a second distance from the first edge of the lead.
In some embodiments, the first surface of the pin includes a second edge adjacent to the first edge of the pin, and the second conductive layer of the first surface of the pin has a third distance from the second edge of the pin.
In some embodiments, the second and third distances range from 0.025mm to 0.1 mm.
In some embodiments, the adhesion between the base material and the package material is greater than the adhesion between the first conductive layer and the package material; the adhesion between the pin material and the package material is greater than the adhesion between the second conductive layer and the package material.
In some embodiments, the chip is fixed on the first surface of the base by an adhesive, and one end of the bonding wire is soldered on the chip and the other end is soldered on the second conductive layer of the pin.
In some embodiments, the first and second conductive layers are composed of silver or nickel palladium gold, the base and the leads of the lead frame are composed of a copper alloy, and the package is composed of epoxy resin.
Compared with the prior art, the technical scheme of the embodiment of the disclosure has the following beneficial effects:
according to the lead frame and the chip packaging product provided by the embodiment of the disclosure, the first distance is formed between the edge of the first conductive layer formed on the first surface of the base and the corresponding edge of the first surface of the base, so that the contact area between the base and the packaging body material is increased, the first distance is controlled within a certain range, the risk of layering of the lead frame and the packaging body material after packaging is reduced, and the packaging reliability of a packaged device is improved.
According to the lead frame and the chip packaging product provided by the embodiment of the disclosure, the second distance is formed between the second conductive layer formed on the first surface of the pin and the first edge of the pin, so that the contact area between the pin and the packaging body material is increased, the second distance is controlled within a certain range, the pin and the chip are ensured to be connected through welding of the bonding wire, the risk of layering of the lead frame and the packaging body material after packaging is further reduced, and the packaging reliability of a packaging device is improved.
Drawings
Other features and advantages of the present disclosure will be better understood by the following detailed description of alternative embodiments, taken in conjunction with the accompanying drawings, in which like characters represent the same or similar parts, and in which:
FIG. 1 shows a cross-sectional schematic view of a side of a lead frame according to an embodiment of the present disclosure;
2-3 show top schematic views of a base of a leadframe according to an embodiment of the disclosure;
4-7 show top schematic views of lead frames according to embodiments of the present disclosure;
FIG. 8 shows a schematic side cross-sectional view of a chip package product according to an embodiment of the disclosure;
FIG. 9 is a partially enlarged cross-sectional schematic view of a chip-packaged product at a pedestal edge according to a prior art embodiment;
FIG. 10 shows a partially enlarged cross-sectional schematic view at the edge of a base of a chip package product according to an embodiment of the disclosure;
fig. 11 shows a partially enlarged cross-sectional schematic view of a chip package product at a pin edge according to a prior art embodiment;
fig. 12 shows a partially enlarged cross-sectional schematic view of a chip package product at a lead edge according to an embodiment of the disclosure.
Detailed Description
Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present disclosure, and are not to be construed as limiting the present disclosure.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. In the description of the present disclosure, it is to be understood that the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the present disclosure and simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be considered as limiting the present disclosure.
To improve the problem of delamination of the package material from the leadframe, embodiments of the present disclosure provide a leadframe.
Fig. 1 shows a schematic cross-sectional view of a side of a lead frame according to an embodiment of the present disclosure. With reference to fig. 1, the lead frame is adapted to carry and hold a chip 3, the lead frame comprising: the pin 2 is suitable for leading out an electrode of the chip 3; a base 1 adapted to carry a chip 3; the first surface of the base 1 is formed with a first conductive layer 11, the first conductive layer 11 includes an edge 111, the first surface of the base 1 includes an edge 12 corresponding to the edge 111, the edge 12 is the edge closest to the edge 111 of the first conductive layer on the first surface of the base 1, a gap is provided between the edge 111 of the first conductive layer 11 and the edge 12 of the first surface of the base 1, and the width of the gap constitutes a first distance W 1 。
In some embodiments, the first conductive layer formed on the first surface of the base does not completely cover the first surface of the base. The first surface of the base comprises a plurality of edges, the first conducting layer comprises a plurality of edges, each edge is provided with an edge of the first surface closest to the edge, a gap is arranged between at least one edge of the first conducting layer and the corresponding edge of the first surface closest to the edge, and the gap is not covered by the first conducting layer.
In some embodiments, the first conductive layer formed on the first surface of the base has a polygonal shape, the first conductive layer includes a plurality of edges, and at least one edge of the first conductive layer does not reach an edge of the first surface closest to the first conductive layer.
According to the requirement of practical application, the shape of the first conductive layer formed on the first surface of the base can be any shape, and the area of the first conductive layer is smaller than that of the first surface of the base. In some embodiments, the first conductive layer formed on the first surface of the base has a circular or elliptical shape, and at least a part of the arc-shaped edge of the first conductive layer has a gap with the edge of the first surface closest to the first conductive layer.
Referring to fig. 1, the chip 3 and the lead 2 are connected by a bonding wire 4, so that an electrode of the chip 3 is led out.
Fig. 2-3 show top schematic views of a base of a leadframe according to embodiments of the disclosure. The first surface of the base 1 is seen from the top view angle of the upper surface of the base 1.
Referring to fig. 2, a base 1 is spaced apart from a lead 2, a first conductive layer 11 is formed on a first surface of the base 1, the first surface of the base 1 includes an edge 12 adjacent to the lead 2, and a first distance W is formed between the edge 111 of the first conductive layer 11 and the edge 12 of the first surface of the base 1 1 。
Referring to fig. 3, the base 1 is spaced from the lead 2, a first conductive layer 11 is formed on a first surface of the base 1, the first surface of the base includes an edge 12 and a side edge 13 near the lead 2, the edge 12 is adjacent to the side edge 13, and a first distance W is formed between an edge 111 of the first conductive layer 11 and the edge 12 of the base 1 1 . The first conductive layer 11 further comprises a side edge 112, the side edge 112 is an edge of the side edge 13 of the first conductive layer 11 closest to the first surface of the base 1, the side edge 112 is adjacent to the edge 111 of the first conductive layer 11, and the side edge 112 of the first conductive layer 11 and the side edge 13 of the first surface of the base 1 have a first distance W therebetween 1 。
In some embodiments, the adhesion between the base and the encapsulating lead frame material is greater than the adhesion between the first conductive layer and the encapsulating lead frame material. In some embodiments, the first distance W 1 The range of (A) is selected to be 0.025 mm-0.1 mm. Therefore, the area of the first conducting layer can be reduced while the bonding process is not influenced, and the risk of layering of the base and the packaging lead frame material is reduced.
In some embodiments, the base has a side surface perpendicular to the first surface, and a surface of the side surface is formed with the conductive layer.
In some embodiments, the base has a side surface perpendicular to the first surface, and a surface of the side surface of the base is a copper alloy.
Fig. 4-7 show schematic top views of lead frames according to embodiments of the present disclosure, and in fig. 4-7, the first surface of the base 1 and the first surface of the lead 2 are both seen from a top view angle of the upper surfaces of the base 1 and the lead 2.
The structure of the base 1 and the first conductive layer 11 formed on the first surface thereof shown in fig. 4 is the same as that shown in fig. 2. Referring to fig. 4, a first conductive layer 11 is formed on the first surface of the base 1, the first surface of the base 1 includes an edge 12 near the lead 2, and a first distance W is formed between an edge 111 of the first conductive layer 11 and the edge 12 of the first surface of the base 1 1 。
In some embodiments, the first distance W 1 The range is 0.025 mm-0.1 mm.
Referring to fig. 1 and 4, the lead 2 and the base 1 have a gap therebetween, the first surface of the lead 2 includes a first edge 22, the first edge 22 is an edge of the lead 2 closest to the base 1, the first surface of the lead 2 is formed with a second conductive layer 21, the second conductive layer 21 includes an edge 211, the edge 211 is an edge of the second conductive layer 21 closest to the first edge 22 of the lead 2, a gap is provided between the edge 211 and the first edge 22 of the lead 2, and a width of the gap forms a second distance W 2 。
In some embodiments, the adhesion between the pin and the package lead frame material is greater than the adhesion between the second conductive layer and the package lead frame material. In some embodiments, the second distance W 2 The range of (A) is selected to be 0.025 mm-0.1 mm. Therefore, the area of the second conducting layer can be reduced while the bonding process is not influenced, and the risk of layering between the lead and the packaging lead frame material is reduced.
The structure of the base and the first conductive layer formed on the first surface thereof shown in fig. 5 is the same as that shown in fig. 3. Referring to fig. 5, a first distance W is formed between an edge 111 of the first conductive layer 11 formed on the first surface of the base 1 and an edge 12 of the first surface of the base 1 1 The first guideThe side edge 112 of the electrical layer 11 has a first distance W from the side edge 13 of the first surface of the substrate 1 1 (ii) a The first surface of the pin 2 includes a first edge 22, the first surface of the pin 2 is formed with a second conductive layer 21, the second conductive layer 21 includes an edge 211, the edge 211 is the edge of the second conductive layer 21 closest to the first edge 22 of the pin 2, a gap is provided between the edge 211 and the first edge 22 of the pin 2, and the width of the gap forms a second distance W 2 。
In some embodiments, the first distance W 1 In the range of 0.025mm to 0.1mm, said second distance W 2 The range is 0.025 mm-0.1 mm.
The structure of the base and the first conductive layer formed on the first surface thereof shown in fig. 6 is the same as that of fig. 2. Referring to fig. 6, a first distance W is formed between an edge of the first conductive layer 11 formed on the first surface of the base 1 and an edge 12 of the base 1 near the leads 2 1 (ii) a A second conductive layer 21 is formed on the first surface of the pin 2, the first surface of the pin 2 includes a first edge 22 closest to the base 1, the first surface of the pin 2 further includes a second edge 23, and the second edge 23 is adjacent to the first edge 22; a second distance W is formed between the edge 211 of the second conductive layer 21 and the first edge 22 of the lead 2 2 。
Referring to fig. 6, the second conductive layer 21 includes a side edge 212, the side edge 212 is an edge of the second conductive layer 21 closest to the second edge 23 of the lead 2, the edge 211 of the second conductive layer 21 is adjacent to the side edge 212 of the second conductive layer, a gap is formed between the side edge 212 of the second conductive layer 21 and the second edge 23 of the lead 2, and the width of the gap forms a third distance W 3 。
In some embodiments, the first distance W 1 In the range of 0.025mm to 0.1mm, said second distance W 2 The range is 0.025 mm-0.1 mm.
In some embodiments, the adhesion between the pin and the package lead frame material is greater than the adhesion between the second conductive layer and the package lead frame material. In some embodiments, the third distance W 3 Range selection of0.025 mm-0.1 mm. Therefore, the area of the second conducting layer can be reduced while the bonding process is not influenced, and the risk of layering between the lead and the packaging lead frame material is reduced.
The structure of the base and the first conductive layer formed on the first surface thereof shown in fig. 7 is the same as that of fig. 3. Referring to fig. 7, a first distance W is formed between an edge 111 of the first conductive layer 11 formed on the first surface of the base 1 and an edge 12 of the first surface of the base 1 1 The side edge 112 of the first conductive layer 11 and the side edge 13 of the first surface of the base 1 have a first distance W therebetween 1 (ii) a A second conductive layer 21 is formed on the first surface of the pin 2, the first surface of the pin 2 includes a first edge 22, the first edge 22 is the edge closest to the base 1, the first surface of the pin 2 further includes a second edge 23, and the second edge 23 is adjacent to the first edge 22; the second conducting layer 21 has a second distance W between the edge 211 and the first edge 22 2 A third distance W is formed between the side edge 212 of the second conductive layer 21 and the second edge 23 of the lead 2 3 。
In some embodiments, the first distance W 1 In the range of 0.025mm to 0.1mm, said second distance W 2 In the range of 0.025mm to 0.1mm, said third distance W 3 The range is 0.025 mm-0.1 mm.
In some embodiments, the first conductive layer 11 is formed on the first surface of the base 1 by electroplating.
In some embodiments, the second conductive layer 21 is formed on the first surface of the lead 2 by electroplating.
In some embodiments, the base 1 and the leads 2 of the lead frame are made of copper alloy, and the first conductive layer 11 and the second conductive layer 21 are made of silver or nickel-palladium-gold.
The embodiment of the disclosure also provides a chip packaging product. Fig. 8 shows a side cross-sectional schematic view of a chip package product according to an embodiment of the disclosure. Referring to fig. 8, the chip package product includes: a chip 3; a base 1 adapted to carry a chip 3; the pin 2 is suitable for leading out an electrode of a chip 3, and the pin 2 is arranged on the periphery of the base 1 and connected with the chip 3 through a bonding wire 4; and the packaging body 5 is suitable for packaging the chip 3, the base 1, the bonding wire 4 and a part of the pin 2.
Referring to fig. 8, the first surface of the base 1 is formed with a first conductive layer 11, the first conductive layer 11 includes an edge 111, the first surface of the base 1 includes an edge 12 corresponding to the edge 111, the edge 12 is an edge of the first surface of the base 1 closest to the edge 111 of the first conductive layer, a gap is formed between the edge 111 of the first conductive layer 11 and the edge 12 of the first surface of the base 1, and the gap constitutes a first distance W 1 。
Referring to fig. 8, the lead 2 is spaced from the base 1, the first surface of the lead 2 includes a first edge 22, the first edge 22 is the edge of the lead 2 closest to the base 1, the first surface of the lead 2 is formed with a second conductive layer 21, and a second distance W is formed between an edge 211 of the second conductive layer 21 and the first edge 22 of the lead 2 2 。
In the chip package product according to the embodiment of the present disclosure, after the chip is fixed by the lead frame and electrically connected to the chip and the pins through the bonding wires, the chip is packaged into a finished product by using the plastic package body. Therefore, the first conductive layer structure formed on the base and the first surface of the base, the second conductive layer structure formed on the pins and the first surface of the pins, the first distance corresponding to the base structure, and the second distance and the third distance corresponding to the pin structure of the chip package product according to the embodiments of the present disclosure are the same as those described above, and are not described herein again.
Referring to fig. 8, a chip 3 is fixed on the first conductive layer 11 on the first surface of the base 1 by an adhesive 6, and one end of a bonding wire 4 is soldered on the chip 3 and the other end is soldered on the second conductive layer 21 of the pin 2.
In some embodiments, the adhesive glue is a silver-doped epoxy glue.
FIG. 9 is a partially enlarged cross-sectional schematic view of a chip-packaged product at a pedestal edge according to a prior art embodiment; fig. 10 shows a partially enlarged cross-sectional schematic view of a chip package product at a pedestal edge according to an embodiment of the disclosure. The chip package products according to the embodiments of the present disclosure and the prior art embodiments are described in detail below with reference to fig. 9 and 10.
Referring to fig. 9, in the prior art embodiment, in the chip package product, the first conductive layer 11 completely covers the first surface of the base 1, and the first conductive layer 11 also covers the second surface 14 of the base 1. A first internal stress σ is generated in the first direction a between the first conductive layer 11 on the first surface of the base 1 and the plastic-sealed body 1 A second internal stress σ is generated in the second direction B between the first conductive layer 11 and the plastic package at the intersection of the first surface and the second surface 14 of the base 1 2 A third internal stress σ is generated between the first conductive layer 11 on the second surface 14 of the base 1 and the plastic package body in the third direction C 3 The first direction a, the second direction B, and the third direction C are different from each other.
Referring to fig. 10, in an embodiment of the present disclosure, in a chip package product, a first conductive layer 11 is formed on a first surface of a base 1, and an edge of the first conductive layer 11 is a first distance W from an edge 12 of the base 1 1 . A first internal stress σ is generated between the first conductive layer 11 and the plastic package body in the first direction a 1 ’。
In the chip package product according to the prior art and in combination with the embodiments shown in fig. 9 and 10, the first conductive layer 11 and the plastic package body respectively generate the first internal stress σ in three different directions, namely, the first direction a, the second direction B, and the third direction C 1 Second internal stress σ 2 Third internal stress σ 3 Due to the existence of the internal stress, the bonding force between the first conductive layer 11 and the plastic package body is reduced, and the phenomenon that the base 1 and the plastic package body are layered easily occurs in the process of expansion with heat and contraction with cold; in the chip package product according to the embodiment of the disclosure, a first internal stress σ is generated between the first conductive layer 11 and the plastic package body in the first direction a 1 ' compared with the prior art, the internal stress σ is generated only in the first direction between the first conductive layer 11 on the base 1 and the plastic package in the embodiment of the disclosure 1 ' to eliminate the internal stress generated in the second and third directions, thereby forming a susceptor1 is less at risk of delamination from the package.
On the other hand, the adhesion between the base 1 and the package is greater than the adhesion between the first conductive layer 11 and the package, so the larger the contact area between the base 1 and the package, the better the adhesion between the base 1 and the package. Compared with the chip package product of the embodiment in the prior art, the chip package product of the embodiment of the disclosure has the advantages that the area of the first conductive layer 11 in contact with the package body is smaller, and the area of the base 1 is larger, so that the base 1 and the package body have stronger adhesion force, and delamination is less prone to happen.
FIG. 11 is a partially enlarged cross-sectional schematic view of a chip package product at a pin edge according to a prior art embodiment; fig. 12 shows a partially enlarged cross-sectional schematic view of a chip package product at a pin edge according to an embodiment of the disclosure. The chip package products according to the embodiments of the present disclosure and the prior art embodiments are described in detail below with reference to fig. 11 and 12.
Referring to fig. 11, in the prior art embodiment, in the chip package product, the second conductive layer 21 completely covers the first surface of the lead 2, and the second conductive layer 21 also covers the second surface 24 of the lead 2. A fourth internal stress σ is generated in the fourth direction D between the second conductive layer 21 on the first surface of the lead 2 and the plastic package body 4 A fifth internal stress σ is generated in a fifth direction E between the second conductive layer 21 and the plastic package at the intersection of the first surface and the second surface 24 of the lead 2 5 A sixth internal stress σ is generated in the sixth direction F between the second conductive layer 21 of the second surface 24 of the lead 2 and the plastic package body 6 The fourth direction D, the fifth direction E, and the sixth direction F are different from each other.
Referring to fig. 12, in the embodiment of the present disclosure, in the chip package product, a second conductive layer 21 is formed on the first surface of the lead 2, and an edge of the second conductive layer 21 is spaced from an edge 22 of the lead 2 by a second distance W 2 . The second conductive layer 21 generates a fourth internal stress σ in a fourth direction D with the plastic package body 4 ’。
Core according to the prior art, combining the embodiments shown in fig. 11 and 12In the sheet package product, a fourth internal stress σ is generated between the second conductive layer 21 and the plastic package body in three different directions, namely a fourth direction D, a fifth direction E and a sixth direction F 4 Fifth internal stress σ 5 Sixth internal stress σ 6 Due to the existence of the internal stress, the bonding force between the second conductive layer 21 and the plastic package body is reduced, and the phenomenon that the pin 2 and the plastic package body are layered easily occurs in the process of expansion with heat and contraction with cold; a fourth internal stress σ is generated between the second conductive layer 21 of the chip package product and the plastic package body in a fourth direction D according to the embodiment of the disclosure 4 In contrast to the prior art embodiment, the internal stress σ is generated only in the fourth direction between the second conductive layer 21 on the lead 2 and the plastic package in the embodiment of the present disclosure 4 ' the internal stress generated in the fifth direction and the sixth direction is eliminated, so that the risk of delamination of the leads 2 from the plastic package is smaller.
On the other hand, the adhesion between the lead 2 and the package is greater than the adhesion between the second conductive layer 21 and the package, so the larger the contact area between the lead 2 and the package, the better the adhesion between the lead 2 and the package. Compared with the chip package product of the embodiment in the prior art, the chip package product of the embodiment of the disclosure has the advantages that the area of the second conductive layer 21 in contact with the package body is smaller, and the area of the pin 2 is larger, so that the pin 2 and the package body have stronger adhesion force, and delamination is less prone to happening.
In some embodiments, the first conductive layer 11 is made of ag or pd-ni, the second conductive layer 21 is made of ag or pd-ni, the base 1 and the leads 2 of the lead frame are made of cu alloy, and the package 5 is made of epoxy resin.
According to the embodiment of the disclosure, under the condition that the bonding force between the edge of the base and the plastic package body and the bonding force between the edge of the pin and the plastic package body are considered, the bonding force between the base and the plastic package body is increased by arranging the first distance between the first conductive layer and the edge of the base on the first surface of the base; the second distance between the second conductive layer and the edge of the pin is set by setting the second distance on the first surface of the pin, so that the binding force between the pin and the plastic package body is increased; and then reduce the risk of layering between lead frame and the plastic-sealed body, improve the reliability of encapsulation.
The above description is made for the purpose of illustrating the principles of the present disclosure and is not intended to limit the scope of the present disclosure. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these changes and modifications are also within the scope of the disclosure.

Claims (15)

1. A lead frame adapted to carry and hold a chip, comprising:
a base adapted to carry a chip;
the pin is suitable for leading out an electrode of the chip;
it is characterized in that the preparation method is characterized in that,
the first surface of the base is formed with a first conductive layer, the first surface of the base includes an edge, and a first distance is provided between the edge of the first conductive layer and a corresponding edge of the first surface of the base.
2. The lead frame of claim 1, wherein the first distance ranges from 0.025mm to 0.1 mm.
3. The lead frame of claim 1, wherein the lead is spaced from the base, the first surface of the lead includes a first edge, the first edge being the edge of the lead closest to the base, the first surface of the lead being formed with a second conductive layer having a second distance from the first edge of the lead.
4. The lead frame of claim 3, wherein the first surface of the pin includes a second edge, the second edge being adjacent to the first edge of the pin, the second conductive layer of the first surface of the pin having a third distance from the second edge of the pin.
5. The lead frame of claim 4, wherein the second and third distances range from 0.025mm to 0.1 mm.
6. The lead frame of any of claims 3-5, wherein the adhesion between the base material and an encapsulating lead frame material is greater than the adhesion between the first conductive layer and the encapsulating lead frame material;
the adhesion between the pin material and the package lead frame material is greater than the adhesion between the second conductive layer and the package lead frame material.
7. The lead frame of claim 6, wherein the first and second conductive layers are comprised of silver or nickel palladium gold, and the base and leads of the lead frame are comprised of a copper alloy.
8. A chip package product, comprising:
a chip;
a base adapted to carry the chip;
the pins are suitable for leading out electrodes of the chip and are arranged on the periphery of the base;
a package adapted to encapsulate the chip, the base, the bonding wires, and a portion of the leads;
the first surface of the base is formed with a first conductive layer, the first surface of the base includes an edge, and a first distance is provided between the edge of the first conductive layer and a corresponding edge of the first surface of the base.
9. The chip package product according to claim 8, wherein the first distance is in a range of 0.025mm to 0.1 mm.
10. The chip package product according to claim 8, wherein the lead and the base have a space therebetween, the first surface of the lead includes a first edge, the first edge is an edge of the lead closest to the base, the first surface of the lead is formed with a second conductive layer, and the second conductive layer has a second distance from the first edge of the lead.
11. The chip package product according to claim 10, wherein the first surface of the lead includes a second edge, the second edge being adjacent to the first edge of the lead, the second conductive layer of the first surface of the lead having a third distance from the second edge of the lead.
12. The chip package product according to claim 11, wherein the second and third distances range from 0.025mm to 0.1 mm.
13. The chip package product according to any one of claims 10-12, wherein an adhesion between the base material and the package material is greater than an adhesion between the first conductive layer and the package material;
the adhesion between the pin material and the package material is greater than the adhesion between the second conductive layer and the package material.
14. The chip package product according to any one of claims 10 to 12, wherein the chip is fixed on the first surface of the base by an adhesive, and one end of the bonding wire is soldered on the chip and the other end is soldered on the second conductive layer of the pin.
15. The chip package product according to claim 13, wherein the first and second conductive layers are made of silver or nickel palladium gold, the base and the leads are made of a copper alloy, and the package body is made of epoxy resin.
CN202220297766.0U 2022-02-14 2022-02-14 Lead frame and chip packaging product Active CN217280756U (en)

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TW112201234U TWM644421U (en) 2022-02-14 2023-02-13 Lead frame and chip packaging product

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