CN112242488A - Gate tube with novel two-dimensional material structure and preparation method thereof - Google Patents
Gate tube with novel two-dimensional material structure and preparation method thereof Download PDFInfo
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- 239000000463 material Substances 0.000 title claims abstract description 120
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 229910052976 metal sulfide Inorganic materials 0.000 claims abstract description 71
- 229910052751 metal Inorganic materials 0.000 claims abstract description 66
- 239000002184 metal Substances 0.000 claims abstract description 66
- 230000007547 defect Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 28
- 238000005485 electric heating Methods 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 229910052697 platinum Inorganic materials 0.000 claims description 12
- 229910004166 TaN Inorganic materials 0.000 claims description 10
- 229910008599 TiW Inorganic materials 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims description 10
- 229910052718 tin Inorganic materials 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 9
- 229910005866 GeSe Inorganic materials 0.000 claims description 8
- 238000010884 ion-beam technique Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 241000252067 Megalops atlanticus Species 0.000 claims description 6
- 229910003185 MoSx Inorganic materials 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910008834 WSx Inorganic materials 0.000 claims description 6
- 229910021389 graphene Inorganic materials 0.000 claims description 6
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 5
- -1 chalcogenide compound Chemical class 0.000 claims description 4
- 229910021645 metal ion Inorganic materials 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 274
- 238000009413 insulation Methods 0.000 description 13
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 12
- 230000015654 memory Effects 0.000 description 11
- 150000004770 chalcogenides Chemical group 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 230000002457 bidirectional effect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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Abstract
The invention discloses a gate tube with a novel two-dimensional material structure and a preparation method thereof, and belongs to the technical field of micro-nano electronics. The gate tube comprises a first metal electrode layer, a gate layer and a second metal electrode layer which are sequentially stacked; the gating layer includes: the two-dimensional material layer A, the switch layer B and the active metal sulfide layer, the two-dimensional material layer A with the switch layer B is piled up alternately and is formed any structure in AB asymmetric structure, BA asymmetric structure or ABA symmetric structure, the quantity of active metal sulfide layer is the same with the quantity of two-dimensional material layer A, the active metal sulfide layer contacts with the one side of two-dimensional material layer A far away from switch layer B, the active metal sulfide layer can provide metal ions, and the metal ions pass through the defect space of two-dimensional material layer, form the electrically conductive silk in the switch layer. The first metal electrode layer and the second metal electrode layer are inert electrode layers, failure of the gate tube due to electrode failure is avoided, and stability of the gate tube is improved.
Description
Technical Field
The invention relates to the technical field of micro-nano electronics, in particular to a gate tube with a novel two-dimensional material structure and a preparation method thereof.
Background
To achieve high density storage, new high performance memories (e.g., resistive memories, phase change memories, etc.) typically take the form of a crossbar array arrangement and thus present a serious cross-talk problem, i.e., a high resistance state read in a 2 × 2 crossbar array will cause current leakage due to the low resistance state of adjacent cells providing a sneak path, resulting in misreading. When the memory array becomes larger or the multi-layer arrays are stacked, the leakage phenomenon becomes more serious. In order to avoid the leakage phenomenon, each memory cell must be connected with a gate tube.
At present, the gate tube mainly includes a bidirectional threshold switch type gate tube, a metal-insulator transition gate tube, a mixed ion electron conduction gate tube, a barrier type gate tube, and a conduction bridge threshold switch type gate tube. The conductive bridge threshold switch type gate tube has extremely low leakage current (high on-off ratio) and has a low power consumption application prospect.
In general, an active metal electrode layer is used as an electrode layer of a conductive bridge threshold switching type gate tube, and a multilayer stack structure in which a conductive wire easy-growth layer a and a conductive wire difficult-growth layer B are alternately stacked is used as a switching layer. By adopting the mode, the gate tube device can form the conduction of the conductive wire under the lower starting voltage, provide larger driving current, and the conductive wire is easy to be disconnected when being closed, so that the gate tube device has extremely low leakage current.
However, in the process of implementing the technical solution of the embodiments of the present application, the inventors of the present application find that the above-mentioned technology has at least a technical problem that the gate transistor device fails due to the easy diffusion or oxidation of the active metal electrode layer, thereby affecting the overall lifetime of the memory.
Disclosure of Invention
The embodiment of the application solves the problem that a gating tube device in the prior art is easy to lose efficacy by providing the gating tube with the novel two-dimensional material structure and the preparation method thereof, and improves the whole service life of a memory.
The embodiment of the application provides a gate tube with a novel two-dimensional material structure, which comprises a first metal electrode layer, a gate layer and a second metal electrode layer which are sequentially stacked;
the gating layer includes: the two-dimensional electrode structure comprises a two-dimensional material layer A, a switch layer B and an active metal sulfide layer, wherein the two-dimensional material layer A and the switch layer B are alternately stacked to form any one structure of an AB asymmetric structure, a BA asymmetric structure or an ABA symmetric structure, the number of the active metal sulfide layers is the same as that of the two-dimensional material layer A, the active metal sulfide layer is in contact with one surface, far away from the switch layer B, of the two-dimensional material layer A, and the first metal electrode layer and the second metal electrode layer are inert electrode layers.
Optionally, the material of the two-dimensional material layer a is any one of graphene, MoSx, WSx, BN, MoSex, MoTex, WSex, WTex, TiSex, and black phosphorus.
Optionally, the material of the active metal sulfide layer is any one of AgS, CuS, NiS and CoS.
Optionally, the material of the switch layer B is a chalcogenide compound, and the chalcogenide compound includes GeSe, ZnSe, AlSe, SbSe2、SnSe、SiSe、GeS、ZnS、AlS、SbS、SbS2And SnS and SiS.
Optionally, the material of the inert electrode layer comprises Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2At least one of ITO and IZO, or Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2An alloy material composed of any two or more of ITO and IZO.
Optionally, the thickness of the two-dimensional material layer A is 5-10 nm.
Optionally, the thickness of the active metal sulfide layer is 15-30 nm.
The embodiment of the application provides a preparation method of a gate tube made of a two-dimensional material, which comprises the following steps:
providing a substrate;
depositing a first metal electrode layer on the substrate, wherein the first metal electrode layer is an inert electrode layer;
manufacturing a gate selection layer on the first metal electrode layer, wherein the gate selection layer comprises a two-dimensional material layer A, a switch layer B and active metal sulfide layers, the two-dimensional material layer A and the switch layer B are alternately stacked to form any one of an AB asymmetric structure, a BA asymmetric structure or an ABA symmetric structure, the number of the active metal sulfide layers is the same as that of the two-dimensional material layer A, and the active metal sulfide layers are in contact with one surface, far away from the switch layer B, of the two-dimensional material layer A;
and preparing the second metal electrode layer on the gating layer, wherein the second metal electrode layer is an inert electrode layer.
Optionally, preparing a gate layer on the first metal electrode layer comprises:
depositing an electric heating insulating layer on the substrate, and patterning the electric heating insulating layer to obtain a nanopore and expose the first metal electrode layer;
and patterning the electric heating insulating layer again, and alternately depositing a switch layer B and a two-dimensional material layer A in sequence to alternately stack to form a BA asymmetric structure.
Optionally, after depositing the two-dimensional material layer a, further comprising:
and carrying out ion beam bombardment on the two-dimensional material layer A so as to adjust the size of the surface defect of the two-dimensional material layer A.
The technical scheme provided by the embodiment of the invention has the beneficial effects that at least:
the gate tube comprises a first metal electrode layer, a gate layer and a second metal electrode layer which are sequentially stacked; the gating layer includes: the two-dimensional material layer A and the switch layer B are alternately stacked to form any one of an AB asymmetric structure, a BA asymmetric structure or an ABA symmetric structure, the number of the active metal sulfide layers is the same as that of the two-dimensional material layer A, the active metal sulfide layers are in contact with one surfaces, far away from the switch layer B, of the two-dimensional material layer A, the active metal sulfide layers can provide metal ions, and the metal ions penetrate through defect gaps of the two-dimensional material layers to form conductive wires in the switch layers. The first metal electrode layer and the second metal electrode layer are inert electrode layers, failure caused by oxidation or diffusion of electrode metal is avoided, stability of the gate tube is improved, and service life of the memory is prolonged. The active metal sulfide layer is limited by the inert electrode layer, so that the active metal sulfide layer is only used as an active metal ion provider, and compared with the active metal ion provider which is used as an electrode, the thickness of the active metal sulfide layer is reduced, the threshold voltage of the gate tube can be reduced, and the power consumption is saved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a gate tube with a novel two-dimensional material structure according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of a gate tube with a novel two-dimensional material structure according to an embodiment of the present invention;
fig. 3 is a cross-sectional view of another gate tube with a novel two-dimensional material structure according to an embodiment of the present invention;
fig. 4 is a cross-sectional view of another gate tube with a novel two-dimensional material structure according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for manufacturing a gate tube with a two-dimensional material new structure according to an embodiment of the present invention;
fig. 6 to 9 are schematic process diagrams of a method for manufacturing a gate tube with a novel two-dimensional material structure according to an embodiment of the present invention;
fig. 10 to 12 are schematic process diagrams of another method for manufacturing a gate tube with a novel two-dimensional material structure according to an embodiment of the present invention;
fig. 13 to fig. 16 are schematic process diagrams of another method for manufacturing a gate tube with a novel two-dimensional material structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a gate tube with a novel two-dimensional material structure according to an embodiment of the present invention. As shown in fig. 1, the gate tube includes a first metal electrode layer 100, a gate layer 200, and a second metal electrode layer 300, which are sequentially stacked. The gating layer 200 comprises a two-dimensional material layer A, a switch layer B and active metal sulfide layers 202, the two-dimensional material layer A and the switch layer B are stacked alternately to form any one of an AB asymmetric structure, a BA asymmetric structure or an ABA symmetric structure, the number of the active metal sulfide layers 202 is the same as that of the two-dimensional material layer A, the active metal sulfide layers 202 are in contact with one surface, away from the switch layer B, of the two-dimensional material layer A, the active metal sulfide layers 202 can provide metal ions, and the metal ions penetrate through defect gaps of the two-dimensional material layer to form conductive wires in the switch layer.
The first metal electrode layer 100 and the second metal electrode layer 300 are both inert electrode layers, so that failure caused by oxidation or diffusion of electrode metal is avoided, the stability of the gate tube is improved, and the service life of the memory is further prolonged. Meanwhile, the active metal sulfide layer 202 is limited by the inert electrode layer, so that the active metal sulfide layer is only used as an active metal ion provider, and compared with the active metal ion provider which is used as an electrode, the thickness of the active metal sulfide layer is reduced, the threshold voltage of the gate tube can be reduced, and the power consumption is saved.
In use, an excitation is applied between the first metal electrode layer 100 and the second metal electrode layer 300 of the gate tube. Under the action of the electric field, when the applied voltage exceeds the threshold voltage, the metal ions of the active metal sulfide layer 202 migrate into the switch layer along the defect gaps in the two-dimensional material layer a to form a conductive wire, so that the first metal electrode layer 100 and the second metal electrode layer 300 are conducted, and the gate tube is conducted. When the applied voltage is lower than the threshold voltage, the conductive filaments disappear, and the gate tube is closed.
Specifically, the thickness of the two-dimensional material layer A is 5-10 nm, and the material of the two-dimensional material layer A is any one of graphene, MoSx, WSx, BN, MoSex, MoTex, WSex, WTex, TiSex and black phosphorus.
In some embodiments, the thickness of the active metal sulfide layer 202 is 15-30 nm, and the material of the active metal sulfide layer 202 is any one of AgS, CuS, NiS and CoS.
In some embodiments, the switching layer B is a chalcogenide thin film, and the chalcogenide includes GeSe, ZnSe, AlSe, SbSe2、SnSe、SiSe、GeS、ZnS、AlS、SbS、SbS2And SnS and SiS.
In some embodiments, the material of the inert electrode layer includes Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2At least one of ITO and IZO, or Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2An alloy material composed of any two or more of ITO and IZO.
Fig. 2 is a cross-sectional view of a gate tube having a novel two-dimensional structure according to an embodiment of the present invention, and in some embodiments, as shown in fig. 2, the gate tube includes a substrate 400, and a first metal electrode layer 100 and an electrothermal insulation layer 201 sequentially deposited on the substrate 400, wherein a nanopore is formed in the electrothermal insulation layer 201, an axis of the nanopore is perpendicular to the substrate 400, and a bottom surface of the nanopore is an upper surface of the first metal electrode layer 100. A switch layer B and a two-dimensional material layer A are alternately stacked in the nanometer hole to form a BA asymmetric structure, the upper surface of the two-dimensional material layer A is flush with the upper surface of the electric heating insulating layer 201, and an active metal sulfide layer 202 and a second metal electrode layer 300 are deposited on the electric heating insulating layer 201. A defect gap serving as a conductive wire channel can be formed in the two-dimensional material layer A, and the thickness of the conductive wire formed in the switch layer when the gate tube is opened can be controlled by controlling the size of the defect area in the two-dimensional material layer A, so that the switching performance of the gate tube can be adjusted.
Fig. 3 is a cross-sectional view of another gate tube with a novel two-dimensional structure according to an embodiment of the present invention, and in some embodiments, as shown in fig. 3, the gate tube includes a substrate 400, and a first metal electrode layer 100, an active metal sulfide layer 202, and an electrothermal insulation layer 201 sequentially deposited on the substrate 400, wherein the electrothermal insulation layer 201 has a nanopore, an axis of the nanopore is perpendicular to the substrate 400, and a bottom surface of the nanopore is an upper surface of the active metal sulfide layer 202. Two-dimensional material layers A and switch layers B are alternately stacked in the nanometer holes to form an AB asymmetric structure, the upper surfaces of the switch layers B are flush with the upper surface of the electric heating insulating layer 201, and a second metal electrode layer 300 is deposited on the electric heating insulating layer 201. A defect gap serving as a conductive wire channel can be formed in the two-dimensional material layer A, and the thickness of the conductive wire formed in the switch layer when the gate tube is opened can be controlled by controlling the size of the defect area in the two-dimensional material layer A, so that the switching performance of the gate tube can be adjusted.
Fig. 4 is a cross-sectional view of another gate tube with a novel two-dimensional structure according to an embodiment of the present invention, and in some embodiments, as shown in fig. 4, the gate tube includes a substrate 400, and a first metal electrode layer 100, an active metal sulfide layer 202, and an electrothermal insulation layer 201 sequentially deposited on the substrate 400, wherein the electrothermal insulation layer 201 has a nanopore, an axis of the nanopore is perpendicular to the substrate 400, and a bottom surface of the nanopore is an upper surface of the active metal sulfide layer 202. Two-dimensional material layers A and switch layers B are alternately stacked in the nano holes to form an ABA asymmetric structure, the upper surfaces of the two-dimensional material layers A are flush with the upper surface of the electric heating insulating layer 201, and an active metal sulfide layer 202 and a second metal electrode layer 300 are deposited on the electric heating insulating layer 201. The gate tube can realize the characteristic of bidirectional gate and is suitable for bipolar devices and unipolar devices. The bidirectional gate tube is applied to the three-dimensional memory, the number of transistors connected on one layer of word line can be reduced, the integration density can be improved, and the performance of the three-dimensional memory is further improved.
Fig. 5 is a flowchart of a method for manufacturing a gate tube with a two-dimensional material new structure according to an embodiment of the present invention. As shown in fig. 5, an embodiment of the present application provides a preparation method of a gate tube with a two-dimensional material novel structure, where the preparation method includes:
s11: a substrate 400 is provided.
In some embodiments, the substrate 400 may be a semiconductor substrate 400, such as a silicon substrate.
S12: a first metal electrode layer 100 is deposited on the substrate 400, the first metal electrode layer 100 being an inert electrode layer.
As shown in fig. 6, a first metal electrode layer 100 is deposited on a substrate 400, the first metal electrode layer 100 being an inert electrode layer.
Optionally, the first metal electrode layer 100 is an inert electrode layer, and the inert electrode layer material includes Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2At least one of ITO and IZO, or Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2An alloy material composed of any two or more of ITO and IZO.
S13: the gate layer 200 is manufactured on the first metal electrode layer 100, the gate layer 200 comprises a two-dimensional material layer A, a switch layer B and an active metal sulfide layer 202, the two-dimensional material layer A and the switch layer B are alternately stacked to form any one of an AB asymmetric structure, a BA asymmetric structure or an ABA symmetric structure, the number of the active metal sulfide layers 202 is the same as that of the two-dimensional material layers A, and the active metal sulfide layer 202 is in contact with one surface of the two-dimensional material layer A, which is far away from the switch layer B.
When the gate tube device shown in fig. 2 is manufactured, S13: fabricating a gate layer 200 on the first metal electrode layer 100, comprising:
s101: preparing an electric heating insulating layer on the substrate 400, and patterning the electric heating insulating layer to obtain a nanopore and expose the first metal electrode layer 100;
in some embodiments, as shown in fig. 7, an electrothermal insulation layer is prepared on a substrate 400, and the electrothermal insulation layer is patterned to obtain a nanopore and expose the first metal electrode layer 100. The material of the electrothermal insulating layer can be SiO2The thickness of the electric heating insulating layer is 100 nm.
S102: and patterning the insulating layer again, and alternately depositing a switch layer B and a two-dimensional material layer A in sequence to alternately stack to form a BA asymmetric structure.
As shown in fig. 8, the insulating layer is patterned again, and the switch layer B and the two-dimensional material layer a are alternately deposited and stacked in sequence to form a BA asymmetric structure. The material of the two-dimensional material layer A can be any one of graphene, MoSx, WSx, BN, MoSex, MoTex, WSex, WTex, TiSex and black phosphorus.
The switch layer B is a chalcogenide film, and the chalcogenide can include GeSe, ZnSe, AlSe, SbSe2、SnSe、SiSe、GeS、ZnS、AlS、SbS、SbS2And SnS and SiS.
S103: an active metal sulfide layer 202 is prepared on the electrically heated insulating layer.
In some embodiments, as shown in FIG. 9, an active metal sulfide layer 202 is prepared on the electrocaloric insulation layer. The thickness of the active metal sulfide layer 202 is 15-30 nm, and the material of the active metal sulfide layer 202 is any one of AgS, CuS, NiS and CoS.
In fabricating the strobe device shown in fig. 3, S13: fabricating a gate layer 200 on the first metal electrode layer 100, comprising:
s201: an active metal sulfide layer 202 is prepared on a substrate 400.
In some embodiments, as shown in fig. 10, an active metal sulfide layer 202 is prepared on a substrate 400. The thickness of the active metal sulfide layer 202 is 15-30 nm, and the material of the active metal sulfide layer 202 is any one of AgS, CuS, NiS and CoS.
S202: an electrothermal insulating layer is prepared on the active metal sulfide layer 202, and the electrothermal insulating layer is patterned to obtain a nanopore and expose the active metal sulfide layer 202.
In some embodiments, as shown in fig. 11, an electrocaloric insulation layer is prepared on the active metal sulfide layer 202 and patterned to obtain nanopores and expose the active metal sulfide layer 202. The material of the electrothermal insulating layer can be SiO2The thickness of the insulating layer was 100 nm.
S203: and patterning the insulating layer again, and alternately depositing a two-dimensional material layer A and a switch layer B in sequence to alternately stack to form an AB asymmetric structure.
As shown in fig. 12, the insulating layer is patterned again, and two-dimensional material layers a and switching layers B are alternately deposited and stacked in sequence to form an AB asymmetric structure. The material of the two-dimensional material layer A can be any one of graphene, MoSx, WSx, BN, MoSex, MoTex, WSex, WTex, TiSex and black phosphorus.
The switch layer B is a chalcogenide film, and the chalcogenide comprises GeSe, ZnSe, AlSe, SbSe and SbSe2、SnSe、SiSe、GeS、ZnS、AlS、SbS、SbS2And SnS and SiS.
In fabricating the strobe device shown in fig. 4, S13: fabricating a gate layer 200 on the first metal electrode layer 100, comprising:
s301: an active metal sulfide layer 202 is prepared on a substrate 400.
In some embodiments, as shown in fig. 13, an active metal sulfide layer 202 is prepared on a substrate 400. The thickness of the active metal sulfide layer 202 is 15-30 nm, and the material of the active metal sulfide layer 202 is any one of AgS, CuS, NiS and CoS.
S302: an electrothermal insulating layer is prepared on the active metal sulfide layer 202, and the electrothermal insulating layer is patterned to obtain a nanopore and expose the active metal sulfide layer 202.
In some embodiments, as shown in fig. 14, an electrocaloric insulation layer is prepared on the active metal sulfide layer 202 and patterned to obtain nanopores and expose the active metal sulfide layer 202. The material of the electrothermal insulating layer can be SiO2The thickness of the electric heating insulating layer is 100 nm.
S303: and patterning the electric heating insulating layer again, and sequentially and alternately depositing a two-dimensional material layer A and a switch layer B to alternately stack to form an ABA symmetrical structure.
As shown in fig. 12, the electrothermal insulating layer is patterned again, and two-dimensional material layers a and switching layers B are alternately deposited in sequence and alternately stacked to form an ABA asymmetric structure. The material of the two-dimensional material layer A can be any one of graphene, MoSx, WSx, BN, MoSex, MoTex, WSex, WTex, TiSex and black phosphorus.
The switch layer B is a chalcogenide film, and the chalcogenide comprises GeSe, ZnSe, AlSe, SbSe and SbSe2、SnSe、SiSe、GeS、ZnS、AlS、SbS、SbS2And SnS and SiS.
S304: an active metal sulfide layer 202 is prepared on the electrothermal insulation layer 201.
In some embodiments, as shown in FIG. 13, an active metal sulfide layer 202 is prepared on an electrocaloric insulation layer 201. The thickness of the active metal sulfide layer 202 is 15-30 nm, and the material of the active metal sulfide layer 202 is any one of AgS, CuS, NiS and CoS.
Optionally, after depositing the two-dimensional material layer a, further comprising:
and carrying out ion beam bombardment on the two-dimensional material layer A to adjust the size of the surface defect of the two-dimensional material layer A. The ion beam bombardment device can generate defects with different sizes when bombarded by different ion beams, can generate smaller defects when the density of the ion beams is smaller and the bombardment time is shorter, and further generate thinner conductive wires, so that the gate tube has larger on-off ratio, and can generate larger defects when the density of the ion beams is larger and the bombardment time is longer, and further generate thicker conductive wires, so that the gate tube has the advantages of low resistance, high threshold value, good cycle characteristic and the like.
S14, preparing a second metal electrode layer 300 on the gate layer 200, the second metal electrode layer 300 being an inert electrode.
Optionally, the second metal electrode layer 300 is an inert electrode, and the inert electrode layer material includes Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2At least one of ITO and IZO, or Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2An alloy material composed of any two or more of ITO and IZO.
The following description is given by way of specific example, illustrating a specific method for fabricating a gate device as shown in fig. 2:
s21: a layer of first metal electrode is prepared on a silicon substrate with a crystalline phase of <100> and a layer of silicon dioxide on the surface through magnetron sputtering, the thickness of the first metal electrode is 100nm, and the first metal electrode is made of platinum.
S22: and preparing an electric heating insulating layer on the bottom electrode, wherein the thickness of the electric heating insulating layer is 100nm, and the material is SiO 2.
S23: a nanopore with a pore diameter of 50nm and a depth of 100nm is prepared on the electric heating insulating layer by a patterning process.
S24: sequentially filling single-layer GeSe and MoS into the nano-pores2The thickness of the material, GeSe, is 40 nm.
S25: photoetching is carried out on the surface of an electric heating insulating layer, then preparing a layer of active metal sulfide CuS material with the thickness of 20nm and top electrode platinum with the thickness of 100nm on the electric heating insulating layer, and then stripping to obtain the gate tube with the novel two-dimensional material structure.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. The gate tube with the novel two-dimensional material structure is characterized by comprising a first metal electrode layer, a gate layer and a second metal electrode layer which are sequentially stacked;
the gating layer includes: the two-dimensional electrode structure comprises a two-dimensional material layer A, a switch layer B and an active metal sulfide layer, wherein the two-dimensional material layer A and the switch layer B are alternately stacked to form any one structure of an AB asymmetric structure, a BA asymmetric structure or an ABA symmetric structure, the number of the active metal sulfide layers is the same as that of the two-dimensional material layer A, the active metal sulfide layer is in contact with one surface, far away from the switch layer B, of the two-dimensional material layer A, and the first metal electrode layer and the second metal electrode layer are inert electrode layers.
2. The gate tube with the novel two-dimensional structure according to claim 1, wherein the material of the two-dimensional material layer a is any one of graphene, MoSx, WSx, BN, MoSex, MoTex, WSex, WTex, TiSex, and black phosphorus.
3. The gate tube with the novel structure of two-dimensional material as claimed in claim 1 or 2, wherein the material of the active metal sulfide layer is any one of AgS, CuS, NiS and CoS.
4. The gate tube with the novel two-dimensional structure as claimed in claim 3, wherein the switch layer B is made of chalcogenide compound including GeSe, ZnSe, AlSe, SbSe2、SnSe、SiSe、GeS、ZnS、AlS、SbS、SbS2And SnS and SiS.
5. The gate tube with the novel structure of two-dimensional material as claimed in claim 4, wherein the material of the inert electrode layer comprises Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2At least one of ITO and IZO, or Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2An alloy material composed of any two or more of ITO and IZO.
6. The gate tube with the novel two-dimensional material structure as claimed in claim 4 or 5, wherein the thickness of the two-dimensional material layer A is 5-10 nm.
7. The gate tube with the novel structure of the two-dimensional material as claimed in claim 4 or 5, wherein the thickness of the active metal sulfide layer is 15-30 nm.
8. A preparation method of a gate tube with a novel two-dimensional material structure is characterized by comprising the following steps:
providing a substrate;
depositing a first metal electrode layer on the substrate, wherein the first metal electrode layer is an inert electrode layer;
manufacturing a gate selection layer on the first metal electrode layer, wherein the gate selection layer comprises a two-dimensional material layer A, a switch layer B and active metal sulfide layers, the two-dimensional material layer A and the switch layer B are alternately stacked to form any one of an AB asymmetric structure, a BA asymmetric structure or an ABA symmetric structure, the number of the active metal sulfide layers is the same as that of the two-dimensional material layer A, and the active metal sulfide layers are in contact with one surface, far away from the switch layer B, of the two-dimensional material layer A;
and preparing a second metal electrode layer on the gating layer, wherein the second metal electrode layer is an inert electrode layer.
9. The method of claim 8, wherein forming a gate layer on the first metal electrode layer comprises:
depositing an electric heating insulating layer on the substrate, and patterning the electric heating insulating layer to obtain a nanopore and expose the first metal electrode layer;
patterning the electric heating insulating layer again, and alternately depositing a switch layer B and a two-dimensional material layer A in sequence to alternately stack to form a BA asymmetric structure;
and preparing an active metal sulfide layer on the electric heating insulating layer.
10. The method according to claim 9, further comprising, after depositing the two-dimensional material layer a:
and carrying out ion beam bombardment on the two-dimensional material layer A so as to adjust the size of the surface defect of the two-dimensional material layer A.
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