JP2013125903A - Resistance change element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance change element having rectifying properties without requiring a metal layer as an ion source layer.SOLUTION: The resistance change element comprises: a first electrode 11; a second electrode 15; a first variable resistance layer 12 which is disposed between the first electrode 11 and the second electrode 15, and is doped with a metal element; a second variable resistance layer 14 which is disposed between the first variable resistance layer 12 and the second electrode 15; and an isolating layer 13 which is disposed between the first variable resistance layer 12 and the second variable resistance layer 14.

Description

  Embodiments described herein relate generally to a nonvolatile variable resistance element whose resistance is electrically variable.

  ReRAM (Resistive Random Access Memory) is a memory in which a variable resistance element unit is configured from a two-terminal structure in which a variable resistance layer is sandwiched between two electrodes. Since the memory cell structure is simple, it is considered that scaling is easier compared to other memories. Therefore, the resistance change memory is one of the promising candidates for the next generation mass storage device that replaces existing products such as NAND flash memories that are widely applied to products.

  Various materials such as transition metal oxides, sulfides, and perovskite oxides have been studied as variable resistance materials for resistance change memories. Among them, a resistance change element using amorphous silicon as a variable resistance material has a high affinity with a silicon CMOS process, and has demonstrated a nonvolatile memory operation at a low current.

  The conventional element structure of the variable resistance element using amorphous silicon as a variable resistance material is composed of Ag in which one electrode is a highly doped Si layer and the counter electrode is a metal. In this element structure, when a voltage is applied between two electrodes, Ag of the electrode material is ionized, and a conductive filament is formed by moving in amorphous silicon (resistance change mechanism). In this resistance change mechanism, Ag as one electrode plays a role as an ion supply layer (ion source layer) for forming a conductive filament.

  However, since the conventional element structure requires a metal layer as an ion source layer, it has problems such as adhesion of the metal layer and metal contamination. Furthermore, in order to realize a mass storage device, having a rectifying property is one of the necessary conditions.

Sung Hyun Jo and Wei Lu, Nano Letters 8, no.2, pp. 392-397 (2008)

  Provided is a resistance change element having a rectifying property without requiring a metal layer as an ion source layer.

  In one embodiment, the variable resistance element includes first and second electrodes, a first variable resistance layer disposed between the first electrode and the second electrode, doped with a metal element, and the first variable resistance element. And a second variable resistance layer disposed between the resistance layer and the second electrode, and an insulating layer disposed between the first variable resistance layer and the second variable resistance layer. And

It is sectional drawing of the resistance change element of 1st Embodiment. It is sectional drawing which shows the transition to the low resistance state of the variable resistance element of 1st Embodiment. It is sectional drawing which shows the transition to the high resistance state of the variable resistance element of 1st Embodiment. It is a figure which shows the typical current-voltage characteristic of the resistance change element of 1st Embodiment. It is a perspective view of the resistance change memory of 2nd Embodiment. It is sectional drawing of the resistance change memory of 2nd Embodiment. It is sectional drawing of the resistance change memory of the modification of 2nd Embodiment. It is sectional drawing of the resistance change memory of 3rd Embodiment. It is sectional drawing of the resistance change memory of the modification of 3rd Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[First Embodiment]
The variable resistance element according to the first embodiment will be described.

  FIG. 1 is a cross-sectional view illustrating the structure of the variable resistance element according to the first embodiment.

  The variable resistance element 10 is based on a laminated structure as shown in FIG. Between the 1st electrode 11 and the 2nd electrode 15, the 1st variable resistance layer 12, the insulating layer 13, and the 2nd variable resistance layer 14 are arrange | positioned in order from the 1st electrode 11 side. That is, the first variable resistance layer 12 is disposed between the first electrode 11 and the second electrode 15, and the second variable resistance layer 14 is disposed between the first variable resistance layer 12 and the second electrode 15. Has been. Furthermore, an insulating layer 13 is disposed between the first variable resistance layer 12 and the second variable resistance layer 14.

  The variable resistance layer 12 is doped with a metal element. The metal element doped in the variable resistance layer 12 acts as an ion source for forming a conductive filament.

  The resistance change element 10 transitions to a low resistance state or a high resistance state depending on the voltage application direction. Below, the transition to the low resistance state or the high resistance state in the variable resistance element 10 will be described.

  2A and 2B are cross-sectional views showing the transition of the variable resistance element 10 to the low resistance state.

  In the resistance change element 10, a voltage is applied between the electrode 11 and the electrode 15. When a positive voltage is applied to the electrode 11 with respect to the voltage applied to the electrode 15, an electric field is generated in the direction from the electrode 11 to the electrode 15. At this time, the metal element doped in the variable resistance layer 12 is ionized. The ionized metal ions 12a are pulled by the action of an electric field and move in the direction of the electrode 15 as shown in FIG.

  As a result, as shown in FIG. 2B, the metal filament 16 is formed in the variable resistance layer 12, the metal filament 17 is formed in the insulating layer 13, and the metal filament 18 is formed in the variable resistance layer 14. These metal filaments 16, 17, and 18 are electrically connected between the electrode 11 and the electrode 15, and the resistance change element 10 transitions to a low resistance state. This is called a set operation.

  Next, the transition to the high resistance state in the variable resistance element 10 will be described. 3A and 3B are cross-sectional views showing the transition of the variable resistance element 10 to the high resistance state.

  For the variable resistance element 10 that has transitioned to the low resistance state, the direction of voltage application is reversed from that at the transition to the low resistance state. That is, a negative voltage is applied to the electrode 11 with respect to the voltage applied to the electrode 15. Then, an electric field is generated in the direction from the electrode 15 to the electrode 11. At this time, the metal atoms constituting the metal filaments 16, 17, and 18 are ionized, and the metal ions 12a move toward the electrode 11 as shown in FIG.

  Then, as shown in FIG. 3B, the metal filaments 16, 17, 18 disappear. Thereby, electrical insulation arises between the electrode 11 and the electrode 15, and the resistance change element 10 changes to a high resistance state. This is called a reset operation. A series of operations including a set operation and a reset operation is called a switch operation.

  On the other hand, in the resistance change element 10 in the high resistance state, when a negative voltage is applied to the electrode 11 with respect to the voltage applied to the electrode 15, the metal element doped in the variable resistance layer 12 is ionized. And move in the direction of the electrode 11. In this case, a metal filament is formed in the variable resistance layer 12, but no metal filament is formed in the insulating layer 13 and the variable resistance layer 14, so that the variable resistance element 10 is maintained in a high resistance state. As described above, asymmetric current-voltage characteristics can be realized for the variable resistance element 10 in the high resistance state. In particular, a variable resistance material exhibiting rectification is used for one or both of the variable resistance layers 12 and 14, or a material system having a small voltage required for the reset operation is used to make the rectification variable. It can be built in the element 10.

  Next, experimental results regarding the variable resistance element according to the first embodiment will be described.

  The variable resistance element 10 shown in FIG. 1 was made of the following materials. TiN is used for the electrode 11, amorphous silicon (film thickness 20 nm) is used for the variable resistance layer 12, SiN (film thickness 10 nm) is used for the insulating layer 13, amorphous silicon (film thickness 20 nm) is used for the variable resistance layer 14, and the electrode 15 is used. Was used for W and Ag for the metal element doped in the variable resistance layer 12. The shape of the element 10 is a circle with a diameter of 100 nm.

  FIG. 4 shows typical current-voltage characteristics of the produced variable resistance element 10.

  As shown in FIG. 4, it can be seen that by applying a positive voltage to TiN that is the electrode 11, the set operation is performed and the resistance change element 10 is transitioned to the low resistance state. Furthermore, it can be seen that a reset operation is performed by applying a negative voltage to the electrode 11, and the resistance change element 10 is transitioning to a high resistance state. When a negative voltage is applied in the high resistance state, no transition to the low resistance state is observed, and a current-voltage characteristic asymmetric with respect to the polarity of the applied voltage is obtained. From the above experimental results, it was confirmed that the variable resistance element 10 having the element structure proposed by the first embodiment can be switched and has an asymmetric current-voltage characteristic.

In the first embodiment, as described above, amorphous silicon is used as the material of the variable resistance layer 12 and the variable resistance layer 14. However, amorphous semiconductors such as amorphous germanium, amorphous silicon germanium, amorphous silicon carbide, and amorphous carbon doped silicon may be used instead of amorphous silicon. Alternatively, a semiconductor such as silicon, germanium, silicon germanium, silicon carbide, or carbon-doped silicon may be used. Furthermore, oxides such as SiOx, HfOx, AlOx, TiOx, or solid ion conduction such as silver sulfide (Ag ₂ S), silver iodide (AgI), copper sulfide (Cu ₂ S), copper selenide (CuSe), etc. The body may be used.

  The materials of the variable resistance layer 12 and the variable resistance layer 14 may be the same or different. The film thicknesses of the variable resistance layer 12 and the variable resistance layer 14 are typically 1 to 300 nm. Considering the operating voltage of the resistance change element when applied to a memory, the thinner the film thickness is, the more preferable is 1 to 20 nm.

  In the first embodiment, TiN and W were used as materials for the electrode 11 and the electrode 15, respectively. However, an inert metal that is difficult to ionize, such as Pt, Ta, or Mo, may be used instead of these materials. Moreover, as a material of the electrode 11 and the electrode 15, a highly doped semiconductor layer, that is, a semiconductor layer doped with an impurity at a high concentration, specifically, silicon, germanium, silicon germanium, silicon carbide, carbon-doped silicon, etc. May be used. Moreover, the material of the electrode 11 and the electrode 15 may be the same, and may differ.

  In the first embodiment, Ag is used as the metal element doped in the variable resistance layer 12. However, instead of Ag, a metal that is easily ionized, such as Co, Ni, Cu, Ti, Al, or Au, can be used. Further, Cr, Mn, Fe, Zn, Sn, In, Pd, Pb, Bi, or the like may be used.

  As a method for doping the variable resistance layer 12 with a metal element, a method in which a metal element is ion-implanted after the variable resistance layer 12 is deposited can be used. In addition, a method of thermally diffusing the metal element into the variable resistance layer 12 by depositing a film containing the metal element after the variable resistance layer 12 and performing a heat treatment can be used. In the resistance change element created in the first embodiment, a method of doping Ag into the amorphous silicon as the variable resistance layer 12 by heat treatment is used.

  The metal element doped in the variable resistance layer 12 may diffuse into the variable resistance element 10, particularly into the variable resistance layer 14, due to the deposition process of the laminated structure of the variable resistance element 10 and the thermal history in the subsequent process steps. is there. By inserting the insulating layer 13 between the variable resistance layer 12 and the variable resistance layer 14, it is possible to prevent the initial diffusion of the metal element. That is, the insulating layer 13 prevents the initial diffusion of the metal element into the variable resistance layer 14 due to the thermal history of the manufacturing process, so that the variable resistance layer 12 doped with the metal element and the variable resistance layer 14 without the metal element exist. It acts as a spacer that separates the two.

  As the insulating layer 13 having such an action, a silicon nitride film (SiN), a silicon oxide film (SiOx), a silicon oxynitride film (SiON), or the like can be used. In the first embodiment, it was confirmed that an asymmetric current-voltage characteristic resulting from an asymmetric laminated structure can be obtained by using a silicon nitride film and suppressing initial diffusion of Ag. The film thickness of the insulating layer 13 is typically 1 to 100 nm. Considering the operating voltage of the resistance change element when applied to a memory, the insulating layer 13 is preferably thin, so 1 to 20 nm is more preferable.

  In the structure of the variable resistance element according to the first embodiment, the ion source is doped in the variable resistance layer and does not have a metal layer as the ion source layer. For example, in the manufacturing process of a conventional element structure, it is difficult to process a metal layer, for example, adhesion between a metal layer used as an ion source layer (hereinafter referred to as an ion source metal layer) and a variable resistance layer, or metal contamination. I have to worry about such things. On the other hand, in the variable resistance element of the first embodiment, since the ion source is embedded in the variable resistance layer, the ion source metal layer is unnecessary, and there is a problem of adhesion between the ion source metal layer and the variable resistance layer and metal contamination. Can be resolved.

  In addition, it is expected that the single layer of the variable resistance layer in which the ion source is embedded has current-voltage characteristics that are symmetric with respect to the polarity of the voltage due to the structural symmetry. For this reason, in the first embodiment, a variable resistance layer having an asymmetric structure further realizes a variable resistance element that exhibits rectification.

  As described above, in the first embodiment, a metal layer as an ion source layer is not required, and a variable resistance element having a rectifying property can be formed.

[Second Embodiment]
In the second embodiment, a cross-point type resistance change memory in which the resistance change element of the first embodiment is arranged at the intersection of the lower wiring and the upper wiring will be described.

  FIG. 5 is a perspective view showing a resistance change memory according to the second embodiment. 6A is a cross-sectional view taken along line A-A ′ shown in FIG. 5, and FIG. 6B is a cross-sectional view taken along line B-B ′ shown in FIG. 5.

  The second embodiment has a structure in which the electrode 11 and the electrode 15 are the lower wiring 20 and the upper wiring 23, respectively, in the first embodiment, and corresponds to the structure of the cross-point type resistance change memory.

Lower wiring _{20 1, 20 2, ···,} 20 n are arranged in parallel, the interlayer insulating film ₂₁ 1 is between the lower wiring, ₂₁ 2, · · ·, _{21 n-1} are disposed. Lower wiring ₂₀ 1, ₂₀ 2, ..., 20 _n, an interlayer insulating film ₂₁ 1, ₂₁ 2, ..., it is electrically insulated from each other by _{21 n-1.}

  A variable resistance structure 22 is disposed on the lower wiring 20 and the interlayer insulating film 21. The variable resistance structure 22 includes a variable resistance layer 12, an insulating layer 13, and a variable resistance layer 14. Further, an upper wiring 23 is disposed on the variable resistance structure 22.

Upper wiring _{23 1,} 23 2, ..., 23 _m are arranged in parallel, the interlayer insulating film ₂₄ 1, ₂₄ 2 between the upper wiring, ..., are disposed _{24 m-1.} Upper wiring _{23 1,} 23 2, ..., 23 _m, an interlayer insulating film _{24 1,} 24 2, ..., are electrically insulated from each other by _{24 m-1.}

The lower wirings 20 ₁ , 20 ₂ ,..., 20 _n and the upper wirings 23 ₁ , 23 ₂ ,..., 23 _m are arranged in a direction crossing each other as shown in FIG. The variable resistance structure 22 existing at the intersection of the lower wiring and the upper wiring becomes a memory cell, and a memory cell array is configured. The memory cell includes a variable resistance layer 12 doped with a metal element, an insulating layer 13, and a variable resistance layer 14, and performs a switching operation. The configuration and operation principle of each layer of the memory cell are as described in the first embodiment.

In the second embodiment, it is possible to control the conductance between adjacent memory cells and adjacent wires by controlling the concentration of the metal element doped in the variable resistance layer 12 in the variable resistance structure 22. That is, it is possible to suppress leakage between wirings arranged in the same wiring layer by keeping the metal element concentration low. For example, in FIG. 6 (b), when the conductance of the variable resistance layer 12 in which the metal element is doped high, ₁ and the wiring 20 ₂ adjacent wires 20 leaks. The same problem occurs in the conventional variable resistance element structure having the ion source electrode layer, and leakage between adjacent wirings becomes a problem.

  On the other hand, in the case of the proposed structure of this embodiment, the conductance of the variable resistance layer 12 can be reduced by keeping the metal element concentration of the variable resistance layer 12 low. As a result, leakage between wirings can be suppressed.

As a typical value of the concentration of the metal element doped in the variable resistance layer 12, 1 × 10 ¹⁸ atom / cm ⁻³ or less can be used. Furthermore, in consideration of the possibility of the switch operation and the suppression of the leakage current in the miniaturized device, it is possible to control in the range of 1 × 10 ¹⁵ atom / cm ⁻³ to 1 × 10 ¹⁷ atom / cm ^−3. preferable.

  In the embodiment shown in FIG. 6, it has been described that the element structure of the variable resistance structure 22 includes the variable resistance layer 12 doped with a metal element, the insulating layer 13, and the variable resistance layer 14 in this order. However, the structure of the variable resistance structure 22 is the stacking order opposite to the structure shown in FIG. 6, that is, the order of the variable resistance layer 14, the insulating layer 13, and the variable resistance layer 12 doped with a metal element from the lower wiring 20 side. But you can.

The lower wirings 20 ₁ , 20 ₂ ,..., 20 _n are, for example, metal conductors having a width and thickness of several nm to several tens of nm, and the upper wirings 23 ₁ , 23 _{2 ,.} Is a metal conductor having a width and thickness of several nm to several tens of nm, for example. As the material of the lower wirings 20 ₁ , 20 ₂ ,..., 20 _n and the upper wirings 23 ₁ , 23 ₂ ,..., 23 _m , an inert metal such as Pt, W, Mo, Ta, TiN is used. be able to.

  Next, a modification of the second embodiment will be described with reference to FIG. In the second embodiment described above, in the memory cell array, the variable resistance structure 22 is not separated for each memory cell, but is formed as one laminated film. In this modification, an example in which the variable resistance structure 22 is separated for each memory cell will be described.

  FIGS. 7A and 7B are cross-sectional views showing a resistance change memory according to a modification of the second embodiment. 7A corresponds to the cross section cut along the line A-A ′ shown in FIG. 5, and FIG. 7B corresponds to the cross section cut along the line B-B ′ shown in FIG. 5.

As shown in FIG. 7 (a), on the lower wiring 20 _1, a plurality of variable resistive structure 22 which is separated is placed. On the variable resistance structure 22, upper wirings 23 ₁ , 23 ₂ ,..., 23 _m are respectively arranged. Interlayer insulating films 24 ₁ , 24 ₂ ,..., 24 _m−1 are disposed between adjacent variable resistance structures 22 and between upper wirings 23.

Further, in the cross section perpendicular to the cross section shown in FIG. 7 (a), as shown in FIG. 7 (b), the lower wiring ₂₀ 1, ₂₀ 2, ..., a plurality of variable resistor structure on 20 _n 22 Are arranged respectively. On top a variable resistive structure 22 wiring 23 ₁ are formed. Interlayer insulating films 21 ₁ , 21 ₂ ,..., 21 _n−1 are formed between the adjacent variable resistance structures 22 and the lower wiring 20.

  In the modified example, since the interlayer insulating films 24 and 21 are disposed between the adjacent variable resistance structures 22, electrical leakage does not occur between the adjacent wirings via the variable resistance layer. Therefore, it is not necessary to control the concentration of the metal element doped in the variable resistance layer in order to suppress leakage between the wirings. Accordingly, it is possible to determine the amount of the metal element doped into the variable resistance layer in consideration of only the switch operation.

  In the second embodiment, by eliminating the metal layer as the ion source layer and using a variable resistance layer in which the ion source is embedded instead, electrical leakage between wirings in the cross-point structure can be suppressed.

  Further, in the cross-point type structure, there is a problem that a sneak current is generated in a non-selected cell at the time of memory writing or reading. Since the variable resistance element according to the present embodiment can have rectifying properties, this sneak current can be reduced. Other configurations and effects are the same as those of the first embodiment.

[Third Embodiment]
In the third embodiment, a stacked cross-point type resistance change memory in which the resistance change memories of the second embodiment are stacked will be described.

  FIGS. 8A and 8B are cross-sectional views showing the structure of the resistance change memory according to the third embodiment.

  The third embodiment has a structure in which two layers of the basic structure of the variable resistance element shown in FIGS. 6A and 6B are stacked, and corresponds to the structure of the stacked cross-point type memory.

  As shown in FIGS. 8A and 8B, the resistance change memory according to the third embodiment includes a wiring 31, a variable resistance layer 32, an insulating layer 33, a variable resistance layer 34, a wiring 35, and a variable resistance layer 36. The insulating layer 37, the variable resistance layer 38, and the wiring 39 are stacked in this order.

  The resistance change element 40 includes a wiring 31, a variable resistance layer 32, an insulating layer 33, a variable resistance layer 34, and a wiring 35. The resistance change element 41 includes a wiring 35, a variable resistance layer 36, an insulating layer 37, and a variable resistance layer 38. , And wiring 39. In the resistance change element 40 and the resistance change element 41, one wiring is shared by the wiring 35. Furthermore, the variable resistance structure 50 includes a variable resistance layer 32, an insulating layer 33, and a variable resistance layer 34, and the variable resistance structure 51 includes a variable resistance layer 36, an insulating layer 37, and a variable resistance layer 38.

  The order of stacking is different between the resistance change element 40 and the resistance change element 41. That is, in the resistance change element 40, the variable resistance layer 32 doped with the metal element, the insulating layer 33, and the variable resistance layer 34 are stacked in this order, whereas in the resistance change element 41, the variable resistance layer 36 and the insulating layer 37 are stacked. The variable resistance layer 38 doped with a metal element is stacked in this order.

  However, the order of these stacks may be reversed. That is, in the resistance change element 40, the variable resistance layer 32, the insulating layer 33, and the variable resistance layer 34 doped with the metal element are stacked in this order. In the resistance change element 41, the variable resistance layer 36 doped with the metal element, the insulating layer 37 and the variable resistance layer 38 may be laminated in this order.

  Moreover, the insulating layer 33 and the insulating layer 37 shall satisfy | fill the conditions of the insulating layer 13 in 1st Embodiment.

  A plurality of wirings 31 are arranged in parallel, and an interlayer insulating film 42 is disposed between the wirings 31. The wirings 31 are electrically insulated from each other by the interlayer insulating film 42. A plurality of wirings 35 are arranged in parallel, and an interlayer insulating film 43 is disposed between the wirings 35. The wirings 35 are electrically insulated from each other by the interlayer insulating film 43. Further, a plurality of wirings 39 are arranged in parallel, and an interlayer insulating film 44 is disposed between the wirings 39. The wirings 39 are electrically insulated from each other by the interlayer insulating film 44.

  The wiring 31 and the wiring 35 are arranged so as to cross each other, and the wiring 35 and the wiring 39 are arranged so as to cross each other.

In the variable resistance layer doped with the metal element, the condition of the variable resistance layer 12 of the first embodiment is satisfied, and in the variable resistance layer not doped with the metal element, the condition of the variable resistance layer 14 of the first embodiment. Shall be satisfied. In addition, the concentration of the metal element in the variable resistance layer doped with the metal element is typically 1 × 10 ¹⁸ atom / cm ⁻³ or less as described in the second embodiment. In particular, by setting the metal element concentration in the range of 1 × 10 ¹⁵ atom / cm ⁻³ to 1 × 10 ¹⁷ atom / cm ⁻³ , leakage current between adjacent wirings in a fine memory cell structure can be suppressed. .

  Next, a modification of the third embodiment will be described with reference to FIG. In the third embodiment described above, in the memory cell array, the variable resistance structures 50 and 51 are not separated for each memory cell, but are formed as one laminated film. In this modification, an example in which the variable resistance structures 50 and 51 are separated for each memory cell will be described.

  FIGS. 9A and 9B are cross-sectional views showing a resistance change memory according to a modification of the third embodiment.

  As shown in FIG. 9A, a plurality of separated variable resistance structures 50 are arranged on the wiring 31. On the variable resistance structure 50, wirings 35 are respectively arranged. A plurality of separated variable resistance structures 51 are respectively arranged on the wiring 35. A wiring 39 is arranged on the variable resistance structure 51. Further, an interlayer insulating film 45 is disposed between the adjacent variable resistance structures 50, between the wirings 35, and between the variable resistance structures 51.

  In a cross section orthogonal to the cross section shown in FIG. 9A, a plurality of separated variable resistance structures 50 are arranged on the wiring 31, as shown in FIG. 9B. A wiring 35 is arranged on the variable resistance structure 50. A plurality of separated variable resistance structures 51 are arranged on the wiring 35. On the variable resistance structure 51, wirings 39 are respectively arranged. An interlayer insulating film 46 is disposed between the adjacent wirings 31 and between the variable resistance structures 50. Further, an interlayer insulating film 47 is disposed between the adjacent variable resistance structures 51 and between the wirings 39.

  In the modification, since the interlayer insulating film is disposed between the adjacent variable resistance structures, electrical leakage does not occur between the adjacent wirings via the variable resistance layer. Therefore, it is not necessary to control the concentration of the metal element doped in the variable resistance layer in order to suppress leakage between the wirings. Accordingly, it is possible to determine the amount of the metal element doped into the variable resistance layer in consideration of only the switch operation.

  The third embodiment and the modification can be applied to an element structure that is turned upside down, and a laminated cross-point type resistance change memory can be formed. Other configurations and effects are the same as those of the first and second embodiments.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 10 ... Variable resistance element, 11 ... 1st electrode, 12 ... 1st variable resistance layer, 12a ... Metal ion, 13 ... Insulating layer, 14 ... 2nd variable resistance layer, 15 ... 2nd electrode, 16, 17, 18 ... metal _filament, 20 _1, 20 2, · · ·, 20 n _... lower _{wiring, 21 1, 21 2, ···} , 21 n-1 ... interlayer insulation film, 22 ... variable resistance _structures 23 1, ₂₃ 2, ..., 23 _m ... upper wiring, 24 ₁ , 24 ₂ , ..., 24 _m-1 ... interlayer insulating film, 31 ... wiring, 32 ... variable resistance layer, 33 ... insulating layer, 34 ... variable resistance layer, 35 ... wiring, 36 ... variable resistance layer, 37 ... insulating layer, 38 ... variable resistance layer, 39 ... wiring, 40 ... resistance change element, 41 ... resistance change element, 42, 43, 44, 45, 46, 47 ... interlayer Insulating film, 50, 51 ... variable resistance structure.

Claims (5)

First and second electrodes;
A first variable resistance layer disposed between the first electrode and the second electrode and doped with a metal element;
A second variable resistance layer disposed between the first variable resistance layer and the second electrode;
An insulating layer disposed between the first variable resistance layer and the second variable resistance layer;
A variable resistance element comprising:   The metal element includes at least one of Ag, Co, Ni, Cu, Ti, Al, Au, Cr, Mn, Fe, Zn, Sn, In, Pd, Pb, and Bi. The resistance change element according to 1.   3. The variable resistance element according to claim 1, wherein the first and second variable resistance layers are any one of silicon, germanium, silicon germanium, and carbon-doped silicon.   4. The variable resistance element according to claim 1, wherein the insulating layer is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. First and second wirings adjacent to each other;
A third wiring and a fourth wiring, which are arranged to cross the first and second wirings and are adjacent to each other;
A first variable resistance layer disposed between the first and second wirings and the third and fourth wirings and doped with a metal element;
A second variable resistance layer disposed between the first variable resistance layer and the third and fourth wirings;
An insulating layer disposed between the first variable resistance layer and the second variable resistance layer;
A variable resistance element comprising:

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