CN112242369A - 封装体 - Google Patents
封装体 Download PDFInfo
- Publication number
- CN112242369A CN112242369A CN201910923170.XA CN201910923170A CN112242369A CN 112242369 A CN112242369 A CN 112242369A CN 201910923170 A CN201910923170 A CN 201910923170A CN 112242369 A CN112242369 A CN 112242369A
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- CN
- China
- Prior art keywords
- layer
- molding material
- conductive
- metallization layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 238000001465 metallisation Methods 0.000 claims abstract description 75
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- 229910052802 copper Inorganic materials 0.000 description 15
- 239000010949 copper Substances 0.000 description 15
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- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- ZTXONRUJVYXVTJ-UHFFFAOYSA-N chromium copper Chemical compound [Cr][Cu][Cr] ZTXONRUJVYXVTJ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- CGZLUZNJEQKHBX-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti][Ti][W] CGZLUZNJEQKHBX-UHFFFAOYSA-N 0.000 description 1
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Abstract
一种封装体包括:第一层模制材料;第一金属化层,位于第一层模制材料上;第二层模制材料,位于第一金属化层及第一层模制材料上;第二金属化层,位于第二层模制材料上;穿孔,位于第二层模制材料内,穿孔从第一金属化层延伸到第二金属化层;集成无源器件,位于第二层模制材料内;重布线结构,以电性方式位于第二金属化层及第二层模制材料上,重布线结构连接到穿孔及集成无源器件;以及至少一个半导体器件,位于重布线结构上,所述至少一个半导体器件连接到重布线结构。
Description
技术领域
本发明实施例涉及一种封装体。
背景技术
半导体行业通过不断减小最小特征大小(minimum feature size)来不断改善各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度,这使得更多组件(因此更多功能)被集成到给定面积中。具有高功能性(high functionality)的集成电路需要许多输入/输出焊盘。然而,小的封装体可期望用于小型化为重要的应用。
集成扇出型(Integrated Fan Out,InFO)封装技术正变得越来越流行,特别是当与晶片级封装(Wafer Level Packaging,WLP)技术结合时,在晶片级封装技术中,集成电路被封装在通常包括重布线层(redistribution layer,RDL)或后钝化互连件(postpassivation interconnect)的封装体中,所述重布线层或后钝化互连件用于对封装体的接触焊盘进行扇出型配线(fan-out wiring),以使得可以比集成电路的接触焊盘大的节距进行电接触。这种所得的封装结构以相对低的成本及高性能封装体提供高功能密度(functional density)。
发明内容
根据本公开的实施例,一种形成封装体的方法,包括:在载体衬底之上形成第一模制材料层;在所述第一模制材料层之上形成穿孔;将第一集成无源器件放置在所述第一模制材料层之上,其中所述第一集成无源器件在横向上相邻于所述穿孔;在所述第一模制材料层之上沉积第二模制材料层,所述第二模制材料层在横向上环绕所述穿孔且在横向上环绕所述第一集成无源器件;在所述第二模制材料层之上形成重布线结构,所述重布线结构电连接到所述穿孔;以及将半导体器件放置在所述重布线结构上。
根据本公开的实施例,一种形成封装体的方法,包括:在载体衬底上形成多个接触焊盘;在所述多个接触焊盘之上形成第一模制材料层;在所述第一模制材料层上形成第一金属化层,所述第一金属化层通过所述第一模制材料层电连接到所述多个接触焊盘;在所述第一金属化层上形成电连接到所述第一金属化层的多个穿孔;将第一无源器件贴合到所述第一金属化层;在所述第一模制材料层、所述第一无源器件及所述多个穿孔之上形成第二模制材料层;在所述第二模制材料层上形成重布线结构,所述重布线结构电连接到所述多个穿孔且电连接到所述第一无源器件;将半导体管芯贴合到所述重布线结构,所述半导体管芯电连接到所述重布线结构。
根据本公开的实施例,一种封装体,包括第一层模制材料、第一金属化层、第二层模制材料、第二金属化层、多个穿孔、多个集成无源器件、重布线结构以及至少一个半导体器件。第一金属化层位于所述第一层模制材料上。第二层模制材料位于所述第一金属化层及所述第一层模制材料上。第二金属化层位于所述第二层模制材料上。多个穿孔位于所述第二层模制材料内,所述多个穿孔从所述第一金属化层延伸到所述第二金属化层。多个集成无源器件位于所述第二层模制材料内。重布线结构以电性方式位于所述第二金属化层及所述第二层模制材料上,所述重布线结构连接到所述多个穿孔及所述多个集成无源器件。至少一个半导体器件位于所述重布线结构上,所述至少一个半导体器件连接到所述重布线结构。
附图说明
结合附图阅读以下详细说明,会最好地理解本公开的各个方面。应注意,根据本行业中的标准惯例,各种特征并非按比例绘制。事实上,为使论述清晰起见,可任意增大或减小各种特征的尺寸。
图1到图8示出根据一些实施例的形成互连结构的中间步骤的剖视图。
图9到图10示出根据一些实施例的形成重布线结构的中间步骤的剖视图。
图11到图14示出根据一些实施例的形成封装结构的中间步骤的剖视图。
图15A及图15B示出根据一些实施例的在不同类型的载体衬底上形成封装结构的中间步骤。
[符号的说明]
102:载体衬底
104:接触焊盘
106:接触通孔
108:第一模制材料
110:第一金属化层
112:穿孔
120:电气器件
122、404:导电连接件
130:第二模制材料
132:第二金属化层
150:互连结构
208A、208G:绝缘层
209A、209F:重布线层
210:导电连接件
212:外部连接件
220:重布线结构
222:底部填充材料
300:半导体器件
302:集成器件
400:封装结构
400':中间结构
406:集成器件
具体实施方式
以下公开内容提供用于实施本发明的不同特征的许多不同的实施例或实例。以下阐述组件及布置的具体实例以简化本公开。当然,这些仅为实例而非旨在进行限制。举例来说,以下说明中将第一特征形成在第二特征之上或第二特征上可包括其中第一特征与第二特征被形成为直接接触的实施例,且也可包括其中第一特征与第二特征之间可形成有附加特征从而使得所述第一特征与所述第二特征可不直接接触的实施例。另外,本公开可能在各种实例中重复使用参考编号和/或字母。这种重复使用是出于简洁及清晰的目的,而不是自身指示所论述的各种实施例和/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“在...之下(beneath)”、“在...下方(below)”、“下部的(lower)”、“在...上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括器件在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向),且本文中所使用的空间相对性描述语可同样相应地进行解释。
在本公开中,阐述器件封装体及形成器件封装体的各个方面。器件封装体可为例如系统级封装体(system-in-package)。在一些实施例中,可在模制材料层内形成集成无源器件,且然后可在模制材料之上形成重布线结构。然后将半导体器件贴合到重布线结构。通过将集成无源器件定位在模制材料层内并将集成无源器件连接到重布线结构,可减小半导体器件与集成无源器件之间的距离,且可改善封装体的电性能。另外,模制材料可提供增加的结构支撑并减少封装体的翘曲。
图1到图14示出根据一些实施例的形成封装结构400(参见图14)的中间步骤的剖视图。图1到图8示出根据一些实施例的形成互连结构150(参见图8)的中间步骤的剖视图。图9到图10示出根据一些实施例的形成重布线结构220(参见图10)的中间步骤的剖视图。图11到图14示出根据一些实施例的形成封装结构400(参见图14)的中间步骤的剖视图。
现参照图1,图1示出根据一些实施例的上面已形成接触焊盘104的载体衬底102。载体衬底102可包含例如硅系材料(例如,硅衬底(例如,硅晶片)、玻璃材料、氧化硅)或其他材料(例如,氧化铝)、类似材料、或组合。在一些实施例中,载体衬底102可为面板结构(panel structure),所述面板结构可为例如由合适的介电材料(例如,玻璃材料或有机材料)形成的支撑衬底,且面板结构可具有矩形形状。载体衬底102可为平坦的,以适于形成附加特征(例如,接触焊盘104)。
作为说明性实例,图15A及图15B示出根据一些实施例的在使用不同类型的载体衬底102形成封装结构400时的中间结构400'。图15A示出其中载体衬底102是硅晶片的实施例,且图15B示出其中载体衬底102是面板结构的实施例。图15A到图15B示出形成在载体衬底102上的多个中间结构400'。在形成封装结构400期间,所示的中间结构400'大致对应于图11中所示的中间结构,但针对图1到图14阐述的任意或全部实施例或结构可类似地适用。以这种方式,可使用不同类型的载体衬底102来形成多个封装结构400。以下针对图14阐述,可随后将形成在载体衬底102上的中间结构400'单体化以形成单独的封装结构400。
转回图1,在一些实施例中,可在载体衬底102的顶表面上形成释放层(未示出),以促进随后进行的载体衬底102的剥离。释放层可由聚合物系材料形成,释放层可与载体衬底102一起从将在随后的步骤中形成的上覆结构被移除。在一些实施例中,释放层为当受热时会失去其粘合性质的环氧系热释放材料(epoxy-based thermal-release material),例如光热转换(Light-to-Heat-Conversion,LTHC)释放涂层。在其他实施例中,释放层可为当暴露到紫外(ultra-violet,UV)光时会失去其粘合性质的紫外(UV)胶。释放层可以液体形态被分配并被固化,可为层叠到载体衬底102上的层叠膜(laminate film)等。释放层的顶表面可被整平(level)且可具有高的共面度(degree of co-planarity)。
在实施例中,形成接触焊盘104可通过使用合适的形成工艺(例如,物理气相沉积(physical vapor deposition,PVD)、化学气相沉积(chemical vapor deposition,CVD)、溅镀等)首先形成钛层、铜层或钛铜合金层中一者或多者的晶种层(未示出)。晶种层形成在载体衬底102或释放层(如果存在的话)之上。然后可形成光刻胶(也未示出)以覆盖晶种层,且然后将光刻胶图案化以暴露出晶种层的位于随后将形成接触焊盘104的位置上的那些部分。一旦光刻胶已形成并被图案化,便可在晶种层上形成导电材料。导电材料可为例如铜、钛、钨、铝、另一种金属、类似金属、或其组合等材料。导电材料可通过例如以下沉积工艺形成:电镀或无电镀覆等。然而,尽管所论述的材料及方法适用于形成导电材料,但这些材料及方法仅为实例。作为另外一种选择,可使用任何其它合适的材料或任何其它合适的形成工艺(例如,CVD或PVD)来形成接触焊盘104。一旦已形成导电材料,便可通过合适的移除工艺(例如,灰化或化学剥除(chemical stripping))来移除光刻胶。另外,在移除光刻胶之后,可通过例如合适的湿式刻蚀工艺或干式刻蚀工艺移除晶种层的曾被光刻胶覆盖的那些部分,所述合适的湿式刻蚀工艺或干式刻蚀工艺可使用导电材料作为刻蚀掩模。晶种层的剩余部分及导电材料形成接触焊盘104。
转到图2,在接触焊盘104之上形成接触通孔106。在一些实施例中,可以类似于接触焊盘104的方式形成接触通孔106。举例来说,形成接触通孔106可通过使用合适的形成工艺(例如,PVD、CVD、溅镀等)首先形成钛层、铜层或钛铜合金层中一者或多者的晶种层(未示出)。然后可形成光刻胶(也未示出)以覆盖晶种层,且然后将光刻胶图案化以暴露出晶种层的位于随后将形成接触通孔106的位置上的那些部分。一旦光刻胶已形成并被图案化,便可使用例如镀覆工艺在晶种层上形成导电材料。导电材料可为例如铜、钛、钨、铝、另一种金属、类似金属、或其组合等材料。一旦已形成导电材料,便可通过合适的移除工艺(例如,灰化或化学剥除(chemical stripping))来移除光刻胶。另外,在移除光刻胶之后,可通过例如合适的湿式刻蚀工艺或干式刻蚀工艺移除晶种层的曾被光刻胶覆盖的那些部分,所述合适的湿式刻蚀工艺或干式刻蚀工艺可使用导电材料作为刻蚀掩模。晶种层的剩余部分及导电材料形成接触通孔106。
转到图3,在载体衬底102之上、接触焊盘104之上及接触通孔106之上形成第一模制材料108。第一模制材料108在横向上环绕接触焊盘104,且在横向上环绕接触通孔106。如下所述,可将第一模制材料108形成为覆盖接触焊盘104的顶表面或接触通孔106的顶表面,且然后随后将第一模制材料108平坦化。作为实例,第一模制材料108可包含环氧树脂、有机聚合物、添加有硅系或玻璃填料的聚合物或未添加有硅系或玻璃填料的聚合物、或其他材料。在一些实施例中,在被施加时,第一模制材料108包含作为凝胶型液体(gel typeliquid)的液体模制化合物(liquid molding compound,LMC)。在被施加时,第一模制材料108也可包含液体或固体。作为另外一种选择,第一模制材料108可包含其他绝缘材料或包封材料。在一些实施例中,使用晶片级模制工艺来施加第一模制材料108。可使用例如压缩模制(compressive molding)、传递模制(transfer molding)或其他技术来对第一模制材料108进行模制。
在一些实施例中,可使用固化工艺(curing process)来对第一模制材料108进行固化。固化工艺可包括使用退火工艺(anneal process)或其他加热工艺将第一模制材料108加热到预定温度达预定时间段。固化工艺还可包括紫外(UV)光曝光工艺(exposureprocess)、红外线(infrared,IR)能量曝光工艺、其组合等。作为另外一种选择,可使用其他技术来对第一模制材料108进行固化。在一些实施例中,不执行固化工艺。
仍然参照图3,可视需要执行平坦化工艺(planarization process)例如,化学机械抛光(chemical-mechanical polish,CMP)工艺或研磨工艺以移除第一模制材料108的位于接触焊盘104及接触通孔106之上的多余部分。如图3中所示,在执行平坦化工艺之后,可暴露出接触通孔106的顶表面。在一些实施例中,在平坦化工艺之后,第一模制材料108及接触通孔106具有共面的顶表面。在一些实施例中,在平坦化工艺之后,第一模制材料108具有约2μm与约150μm之间的厚度。使用模制材料(例如,第一模制材料108)来环绕接触焊盘104及接触通孔106可提供结构支撑或增加刚度(rigidity),从而减少最终器件中的翘曲量。
转到图4,在第一模制材料108及接触通孔106之上形成第一金属化层110。在一些实施例中,可以类似于接触焊盘104或接触通孔106的方式形成第一金属化层110。举例来说,形成第一金属化层110可通过使用合适的形成工艺(例如,PVD、CVD、溅镀等)首先形成钛层、铜层或钛铜合金层中一者或多者的晶种层(未示出)。然后可形成光刻胶(也未示出)以覆盖晶种层,且然后将光刻胶图案化以暴露出晶种层的位于随后将形成第一金属化层110的图案的位置上的那些部分。一旦光刻胶已形成并被图案化,便可使用例如镀覆工艺在晶种层上形成导电材料。导电材料可为例如铜、钛、钨、铝、另一种金属、类似金属、或其组合等材料。一旦已形成导电材料,便可通过合适的移除工艺(例如,灰化或化学剥除)来移除光刻胶。另外,在移除光刻胶之后,可通过例如合适的湿式刻蚀工艺或干式刻蚀工艺移除晶种层的曾被光刻胶覆盖的那些部分,所述合适的湿式刻蚀工艺或干式刻蚀工艺可使用导电材料作为刻蚀掩模。晶种层的剩余部分及导电材料形成第一金属化层110。
转到图5,在第一金属化层110及第一模制材料108之上形成穿孔112。在一些实施例中,可通过以下步骤来形成穿孔112:在第一金属化层110及第一模制材料108之上形成晶种层;且然后在晶种层之上形成图案化光刻胶,其中图案化光刻胶中的多个开口中的每一者对应于要形成的穿孔112的位置。使用合适的技术(例如,电镀或无电镀覆)以导电材料(例如,铜)来填充图案化光刻胶中的开口。然后使用合适的工艺(例如,灰化或剥除工艺)移除光刻胶。然后,可使用合适的刻蚀工艺移除晶种层上没有形成穿孔112的部分。可将穿孔112形成为在第一金属化层110及第一模制材料108上方延伸的导电柱。用于形成穿孔112的其他技术也是可能的,且完全旨在包括在本公开的范围内。在一些实施例中,可将穿孔112形成为具有约25μm与约1000μm之间的高度或约10μm与约500μm之间的宽度。
接下来,在图6中,根据一些实施例,将电气器件120贴合到第一金属化层110。电气器件120可为管芯、芯片、或封装体、半导体器件或包括一个或多个无源器件(例如,电容器、电阻器、电感器等)的其他器件。电气器件120可为例如集成无源器件(integrated passivedevice,IPD)。在一些实施例中,电气器件120是包括电容器(例如,多层式陶瓷电容器(multi-layer ceramic capacitor,MLCC)等)的无源器件。在一些实施例中,电气器件120具有约5μm与约1000μm之间的厚度。电气器件120可具有小于穿孔112、大于穿孔112或约相同于穿孔112的厚度。在一些情况下,通过将电气器件120相邻于穿孔112贴合,可减小电气器件120与半导体器件(例如,图12的半导体器件300)之间的布线距离(routingdistance),这可减小电气器件120与半导体器件之间的电感及电阻。以这种方式,较短的布线距离可改善器件的较高频率操作,且提供得到改善的电压稳定性或电流稳定性。
电气器件120可在一个侧或多个侧上包括导电连接件122。举例来说,图6示出在电气器件120的相对的侧上具有导电连接件122的电气器件120,但是在其他实施例中,电气器件120可仅在电气器件120的一个侧上具有导电连接件122。在一些实施例中,电气器件120通过导电连接件122电连接到第一金属化层110的一个或多个区。导电连接件122可包括导电凸块、焊料区、导电焊盘等。可例如通过以下步骤将电气器件120连接到第一金属化层110:将导电连接件122依序浸入焊剂中;且然后使用拾取及放置(pick-and-place)工具来将导电连接件122与第一金属化层110的对应的区实体地对准。在一些情况下,可执行回焊(reflow)以将导电连接件122结合到第一金属化层110。在一些实施例中,可将电气器件120配置成提供电压稳定性或电流稳定性给最终器件。在一些实施例中,可将一个电气器件120或多于两个电气器件120连接到第一金属化层110。在包括连接到第一金属化层110的多个电气器件120的实施例中,电气器件120可全部为类似的器件或者可为不同类型的器件。
转到图7,在第一模制材料108、第一金属化层110、穿孔112及电气器件120之上形成第二模制材料130。第二模制材料130在横向上环绕穿孔112,且在横向上环绕电气器件120。在一些实施例中,穿孔112与电气器件120被第二模制材料130分离开。如下所述,可将第二模制材料130形成为覆盖穿孔112的顶表面或电气器件120的顶表面,且然后随后将第二模制材料130平坦化。作为实例,第二模制材料130可包含环氧树脂、有机聚合物、添加有硅系或玻璃填料的聚合物或未添加有硅系或玻璃填料的聚合物、或其他材料。在一些实施例中,在被施加时,第二模制材料130包含作为凝胶型液体的液体模制化合物(LMC)。在被施加时,第二模制材料130也可包含液体或固体。作为另外一种选择,第二模制材料130可包含其他绝缘材料或包封材料。第二模制材料130可为类似于或不同于第一模制材料108的材料。在一些实施例中,使用晶片级模制工艺来施加第二模制材料130。可使用例如压缩模制、传递模制或其他技术来对第二模制材料130进行模制。第二模制材料130可以与第一模制材料108相同的方式形成或者以与第一模制材料108不同的方式形成。
在一些实施例中,可使用固化工艺来对第二模制材料130进行固化。固化工艺可包括使用退火工艺或其他加热工艺将第二模制材料130加热到预定温度达预定时间段。固化工艺还可包括紫外(UV)光曝光工艺、红外线(IR)能量曝光工艺、其组合等。作为另外一种选择,可使用其他技术来对第二模制材料130进行固化。在一些实施例中,不执行固化工艺。在一些实施例中,使用相同的固化工艺来同时对第一模制材料108与第二模制材料130进行固化。
转到图8,可视需要执行平坦化工艺(例如,CMP工艺或研磨工艺)以移除第二模制材料130的位于穿孔112及电气器件120之上的多余部分,从而形成互连结构150。平坦化工艺暴露出穿孔112的顶表面。在一些实施例中,平坦化工艺暴露出电气器件120的顶表面。电气器件120的暴露出的顶表面可包括导电连接件122,如图8中所示。在一些实施例中,在平坦化工艺之后,第二模制材料130、穿孔112或电气器件120具有共面的顶表面。在一些实施例中,在平坦化工艺之后,第二模制材料130具有约25μm与约1000μm之间的厚度。使用模制材料(例如,第二模制材料130)来环绕穿孔112或电气器件120可提供结构支撑或增加刚度,从而减少最终器件中的翘曲量。在一些情况下,使用第一模制材料108及第二模制材料130二者可减少比仅使用第一模制材料108或第二模制材料130中的一者来得多的翘曲。
转到图9,在互连结构150的穿孔112、电气器件120及第二模制材料130之上形成第二金属化层132。在一些实施例中,可通过以下步骤来形成第二金属化层132:形成晶种层;且然后在晶种层之上形成图案化光刻胶,其中图案化光刻胶中的多个开口中的每一者对应于要形成的第二金属化层132的图案。使用合适的技术(例如,电镀或无电镀覆)以导电材料(例如,铜)来填充图案化光刻胶中的开口。然后使用合适的工艺(例如,灰化或剥除工艺)移除光刻胶。然后,可使用合适的刻蚀工艺移除晶种层的多余部分。可以类似于第一金属化层110的形成方式的方式形成第二金属化层132,不过用于形成第二金属化层132的其他技术也是可能的,且完全旨在包括在本公开的范围内。在一些实施例中,电气器件120的暴露出的多个导电连接件122中的一些导电连接件122或全部导电连接件122不包含第二金属化层132,如图9中所示。
转到图10,根据一些实施例,在第二模制材料130及第二金属化层132之上形成重布线结构220。所示的重布线结构220包括绝缘层208A到绝缘层208G(为清楚起见,仅标记绝缘层208A及绝缘层208G),且包括重布线层209A到重布线层209F(为清楚起见,仅标记重布线层209A及重布线层209F)。在一些情况下,第二金属化层132或导电连接件210(在下文中更详细地阐述)可被视为重布线结构220的部分。在其他实施例中,可在重布线结构220中形成与本文所述不同数目的绝缘层或重布线层。在一些实施例中,重布线结构220可以与本文所述的工艺不同的工艺形成。在一些实施例中,重布线结构220可为例如扇出型结构。在一些实施例中,位于第二模制材料130上方的重布线结构220可具有约50μm与约500μm之间的厚度。
仍然参照图10,绝缘层208A形成在第二金属化层132之上及第二模制材料130的顶表面之上。在一些实施例中,绝缘层208A也可形成在第一模制材料108的侧壁之上及第二模制材料130的侧壁之上,如图10中所示。在一些实施例中,第一模制材料108的侧壁或第二模制材料130的侧壁不包含绝缘层208A。举例来说,在一些实施例中,可在单个载体衬底102上形成多个封装结构400(例如,如图15A到图15B中所示),且将第一模制材料108和/或第二模制材料130形成为在相邻的封装结构400之间充分地延伸。绝缘层208A可由一种或多种合适的介电材料(例如,氧化物(例如,氧化硅)、氮化物(例如,氮化硅)、聚合物材料(例如,感光性聚合物材料)、聚酰亚胺材料、低介电常数(low dielectric constant,low-k)介电材料、另一种介电材料、类似材料、或其组合)制成。绝缘层208A可通过例如以下工艺形成:旋转涂布、层叠(lamination)、CVD、类似工艺、或其组合。位于第二模制材料130之上的绝缘层208A可具有约30μm与约1000μm之间(例如,约500μm)的厚度,不过也可使用任何合适的厚度。可使用合适的光刻掩模及刻蚀工艺来形成在绝缘层208A中的开口。举例来说,可在绝缘层208A之上形成光刻胶且将光刻胶图案化,且利用一种或多种刻蚀工艺(例如,湿式刻蚀工艺或干式刻蚀工艺)来移除绝缘层208A的部分。在一些实施例中,绝缘层208A由感光性聚合物(例如,聚苯并恶唑(polybenzoxazole,PBO)、聚酰亚胺、苯并环丁烯(benzocyclobutene,BCB)等)形成,其中可使用光刻掩模及刻蚀工艺直接将开口图案化。绝缘层208A中的开口可暴露出第二金属化层132或电气器件120的导电连接件122。
然后可形成重布线层209A,以在重布线结构220内提供附加的布线以及电连接。在实施例中,可使用类似于第二金属化层132的材料及工艺来形成重布线层209A。举例来说,可形成晶种层,在晶种层的顶部放置光刻胶且将光刻胶图案化成重布线层209A所期望的图案。然后可使用例如镀覆工艺在光刻胶的图案化开口中形成导电材料(例如,铜、钛等)。然后可移除光刻胶并对晶种层进行刻蚀,从而形成重布线层209A。以这种方式,重布线层209A可形成到第二金属化层132或导电连接件122的电连接。
然后,可在重布线层209A及绝缘层208A之上形成附加的绝缘层208B到绝缘层208G及重布线层209B到重布线层209F,以在重布线结构220内提供附加的布线以及电连接。可将绝缘层208B到绝缘层208G及重布线层209B到重布线层209F形成为交替的多个层,且可使用类似于用于绝缘层208A或重布线层209A的工艺及材料的工艺及材料来形成绝缘层208B到绝缘层208G及重布线层209B到重布线层209F。举例来说,可在重布线层(例如,重布线层209A)之上形成绝缘层(例如,绝缘层208B),且然后使用合适的光刻掩模及刻蚀工艺制作穿过绝缘层的开口以暴露出下伏重布线层的部分。可在绝缘层之上形成晶种层,且在晶种层的部分上形成导电材料,从而形成上覆重布线层(例如,重布线层209B)。可重复这些步骤来形成具有合适的绝缘层及重布线层的数目及配置的重布线结构220。作为另外一种选择,绝缘层208B到绝缘层208G或重布线层209B到重布线层209F可与绝缘层208A或重布线层209A不同地形成。可将绝缘层208B到绝缘层208G形成为各自具有约5μm与约60μm之间(例如,约15μm)的厚度。可将重布线层209B到重布线层209F中的每一者的部分形成为具有约1μm与约20μm之间(例如,约7μm)的厚度。在一些实施例中,重布线结构220是扇出型结构。在其他实施例中,第二重布线结构220可以与本文所述方式不同的方式形成。
仍然参照图10,在重布线结构220的最顶部重布线层(例如,重布线层209F)之上形成导电连接件210。在一些实施例中,导电连接件210可以类似于重布线层209A到重布线层209F的方式形成。举例来说,使用合适的光刻掩模及刻蚀工艺制作穿过最顶部绝缘层(例如,绝缘层208G)的开口,以暴露出下伏重布线层(例如,重布线层209F)的部分。可在绝缘层之上形成晶种层,且在晶种层的部分上形成导电材料,从而形成导电连接件210。
仍然参照图10,在一些实施例中,导电连接件210包括凸块下金属化结构(under-bump metallization structures,UBMs,未示出)。UBMs可例如包括三种导电材料层(例如,钛层、铜层及镍层)。然而,可使用适用于形成UBMs的其他材料及层的布置,例如铬/铬铜合金/铜/金的布置、钛/钛钨/铜的布置或者铜/镍/金的布置。任何合适的材料或材料层均可用于UBMs,且完全旨在包括在当前申请的范围内。可通过在重布线结构220的最顶部绝缘层之上以及在最顶部绝缘层中形成的开口内形成UBMs的每一层来形成UBMs。可在导电连接件210的先前沉积的导电材料之上形成UBMs的每一层。每一层的形成可使用镀覆工艺(例如,电镀或无电镀覆)来执行,不过作为另外一种选择,也可根据期望的材料而定,使用其他形成工艺,例如溅镀、蒸镀或等离子体增强型化学气相沉积(plasma-enhanced chemicalvapor deposition,PECVD)工艺。一旦已形成期望的层,然后便可通过合适的光刻掩模及刻蚀工艺移除不期望的材料来移除层的部分,且从而使UBMs处于期望的形状(例如,圆形形状、八边形形状、正方形形状或矩形形状),不过作为另外一种选择,也可形成任何期望的形状。
转到图11,在导电连接件210之上形成外部连接件212。可在UBMs(如果存在的话)之上形成外部连接件212。外部连接件212可为例如接触凸块或焊料球,不过也可利用任何合适类型的连接件。在其中外部连接件212是接触凸块的实施例中,外部连接件212可包含例如锡等材料、或例如银、无铅锡或铜等其他合适的材料。在其中外部连接件212是锡焊料凸块的实施例中,形成外部连接件212可通过使用例如蒸镀、电镀、印刷、焊料转移、植球等技术首先形成锡层。一旦已在结构上形成锡层,便可执行回焊,以使材料成形为外部连接件212所期望的凸块形状。在一些实施例中,一个或多个导电连接件210不包含外部连接件212,例如在无源器件(集成器件302)(参见图12)可被连接的区中。在一些实施例中,外部连接件212可具有约3μm与约50μm之间的厚度。在一些实施例中,外部连接件212可具有约20μm与约250μm之间的节距。
转到图12,可将一个或多个半导体器件300贴合到外部连接件212,以形成与重布线结构220的电连接。也可将一个或多个集成器件302连接到重布线结构220,且可将一个或多个集成器件302贴合到外部连接件212或导电连接件210(如图所示)。可例如通过以下步骤将半导体器件300或集成器件302连接到外部连接件212或导电连接件210:依序地将半导体器件300或集成器件302的连接件(例如,导电凸块或焊盘),例如焊料球(未示出)浸入焊剂中,且然后使用拾取及放置工具将半导体器件300或集成器件302的连接件与对应的外部连接件212或导电连接件210实体地对准。在一些情况下,可执行回焊以将半导体器件300或集成器件302的连接件结合到外部连接件212或导电连接件210。
如图12中所示,可将底部填充材料222分配在半导体器件300与重布线结构220之间。底部填充材料222环绕外部连接件212及导电连接件210。底部填充材料222可为任何可接受的材料,例如聚合物、环氧树脂、模制底部填充胶(molding underfill)等。可使用毛细流动工艺(capillary flow process)或使用另一种合适的工艺并使用针或喷射分配器(jetting dispenser)来分配底部填充材料222。在一些实施例中,可执行固化工艺来对底部填充材料222进行固化。尽管图12中未示出,但底部填充材料222可沿半导体器件300的侧壁延伸。半导体器件300可包括一个或多个器件,所述一个或多个器件可包括为预期目的设计的器件,例如存储器管芯(例如,动态随机存取存储器(dynamic random access memory,DRAM)管芯、堆叠存储器管芯、高带宽存储器(high-bandwidth memory,HBM)管芯等)、逻辑管芯、中央处理器(central processing unit,CPU)管芯、系统芯片(system-on-a-chip,SoC)、组件晶片(component on a wafer,CoW)、集成扇出型结构(integrated fan-outstructure,InFO)、封装体、类似器件、或其组合。在实施例中,根据特定功能的期望而定,在本文中,半导体器件300包括集成电路器件,例如晶体管、电容器、电感器、电阻器、金属化层、外部连接件等。在一些实施例中,半导体器件300可包括多于一个相同类型的器件,或者可包括不同的器件。图12示出单个半导体器件300,但在其他实施例中,可将一个、两个或多于三个的半导体器件300贴合到重布线结构220。
集成器件302可为例如半导体器件或包括一个或多个无源器件(例如,电容器、电阻器、电感器等)的其他器件。集成器件302可为例如IPD或MLCC。在一些实施例中,电气器件120与半导体器件300之间的布线距离可小于集成器件302与半导体器件300之间的布线距离。举例来说,从集成器件302到半导体器件300的布线距离可包括沿着重布线层209A在横向上的布线。由于例如放置工艺的限制,集成器件302与半导体器件300之间在横向上的距离可为约0.5mm或大于0.5mm的距离。在一些实施例中,重布线结构220的总垂直厚度可小于集成器件302与半导体器件300之间在横向上的距离。举例来说,在一些实施例中,重布线结构220的总厚度可小于约0.5mm。因此,垂直延伸穿过重布线结构220的电气器件120与半导体器件300之间的布线距离可小于在横向上延伸穿过重布线层209A的集成器件302与半导体器件300之间的布线距离。
图13示出根据一些实施例的对载体衬底102进行的剥离。可使用例如热工艺(thermal process)改变设置在载体衬底102上的释放层的粘合性质而从接触焊盘104及第一模制材料108剥离载体衬底102。在特定实施例中,利用能量源(energy source),例如紫外(UV)激光器、二氧化碳(CO2)激光器或红外(IR)激光器来照射及加热释放层,直到释放层失去其粘合性质中的至少一些粘合性质为止。一旦执行,载体衬底102与释放层便可实体地分离开并从接触焊盘104及第一模制材料108移除。在一些实施例中,可翻转所述结构以贴合到临时衬底(未示出),例如条带(tape)、晶片、面板、框架、环等。图13还示出在已执行接触焊盘104的选择性的凹陷之后的接触焊盘104。可使用刻蚀工艺(例如,湿式刻蚀工艺、干式刻蚀工艺、或组合)来执行凹陷。
图14示出根据一些实施例的对结构进行单体化以形成封装结构400。在实施例中,可使用将结构分离成分立的片的一个或多个锯片(saw blade)来对结构进行单体化,从而形成一个或多个经单体化的封装结构400。然而,还可利用任何合适的单体化方法,包括激光烧蚀(laser ablation)或者一种或多种湿式刻蚀。在单体化(如果使用的话)之后,可从临时衬底移除封装结构400。在一些实施例中,可通过单体化工艺移除位于第一模制材料108的侧壁之上或第二模制材料130的侧壁之上的绝缘层208A。第一模制材料108、第二模制材料130或重布线结构220可具有共面的侧壁。在一些实施例中,封装结构400可具有约5mm乘5mm与约500mm乘500mm之间(例如,约14mm乘14mm)的横向尺寸,不过封装结构400也可具有除这些尺寸之外的其他尺寸。在一些实施例中,封装结构400可具有约50μm与约3000μm之间的垂直厚度。
仍然参照图14,在接触焊盘104之上形成导电连接件404且将导电连接件404电连接到接触焊盘104。导电连接件404可为例如接触凸块或焊料球,不过也可利用任何合适类型的连接件。在其中导电连接件404是接触凸块的实施例中,导电连接件404可包括例如锡等材料、或例如银、无铅锡或铜等其他合适的材料。在其中导电连接件404是锡焊料凸块的实施例中,形成导电连接件404可通过使用例如蒸镀、电镀、印刷、焊料转移、植球等技术首先形成锡层。一旦已在结构上形成锡层,便可执行回焊,以将材料成形为导电连接件404所期望的凸块形状。可在封装结构400单体化之前或在封装结构400单体化之后形成导电连接件404。在一些实施例中,导电连接件404可具有约150μm与约1,000μm之间的节距。
仍然参照图14,根据一些实施例,将选择性的集成器件406贴合到接触104。集成器件406可为器件、管芯、芯片或封装体,例如IPD、MLCC等。集成器件406通过导电连接件电耦合到接触焊盘104。导电连接件可为例如导电凸块、焊料球、导电焊盘等。导电连接件可类似于导电连接件404。可使用例如拾取及放置工艺来放置集成器件406。
通过在包含模制材料的层中形成具有导电元件穿孔或电气器件的封装体,可改善封装体的刚度。举例来说,具有较大横向尺寸的结构可能更容易翘曲或分层(delamination)。如本文所述使用第一模制材料108和/或第二模制材料130可为封装结构400提供结构支撑,从而减少封装结构400的翘曲。以这种方式,可减少封装体的翘曲,且因此可减少与翘曲相关的问题(例如,破裂或分层)。另外,相对于使用其他材料、结构或工艺(例如,使用有机芯结构(organic core structure)或使用工艺,例如倒装芯片工艺(flip-chip process)),使用模制材料可降低制造成本。
另外,通过形成其中电气器件120被设置成相邻于穿孔112或位于重布线结构220与接触焊盘104之间的封装结构400,可改善封装结构400的电性能。举例来说,可减小电气器件120与半导体器件300之间的距离,这可减小布线距离,且因此减小电气器件120与半导体器件300之间的电阻或电感。举例来说,通过以这种方式减小距离,也可减小由电阻引起的电压降(voltage drop)。通过减小电感,可改善封装结构400的高频性能。举例来说,可增大封装体的操作的可用频率范围。另外,由于更稳定的电性能,可改善封装结构400的功率完整性。
在一些情况下,设置在重布线结构220的相对的侧上的半导体器件300与电气器件120之间的布线距离(如图14中所示)可小于位于重布线结构220的同一侧上的半导体器件300与相邻于半导体器件300安装的器件(例如,集成器件302)之间的布线距离。电气器件120与半导体器件300之间的布线距离也可小于安装在封装结构400的相对的侧上的半导体器件300与集成器件(例如,集成器件406)之间的布线距离。在一些实施例中,电气器件120与半导体器件300之间的垂直距离可小于约10mm,例如小于约0.05mm的距离。
在一些情况下,重布线结构220可使用比其他技术(例如,使用有机芯结构来布线)稳健而可靠的技术来形成。举例来说,重布线结构220可使用扇出型工艺形成(例如,在半导体制作厂中)。通过使用更稳健的工艺,重布线结构220可具有比使用其他技术高的良率。在一些情况下,与其他工艺(例如,增层法工艺(build-up process))相比,用于形成重布线结构220的工艺可形成具有更小的尺寸且具有更小的线宽粗糙度(line width roughness)的重布线层。在一些情况下,重布线结构220的线宽粗糙度可小于约Ra=0.1μm。在一些情况下,可在不存在不期望的导电集肤效应(conductive skin effect)的条件下减小线宽粗糙度。因此,相对于例如有机芯结构等其他类型的布线结构,重布线结构220可具有改善的电性能,特别是在高频率操作(例如,大于2G位/秒(bit/second))的情况下。举例来说,重布线结构220的绝缘层(例如,绝缘层208A到绝缘层208G)可为在较高频率下具有低的信号损耗的介电材料,例如具有小于约0.01的损耗正切(loss tangent)Df的介电材料。举例来说,可使用具有低的损耗正切Df的聚酰亚胺材料。在一些情况下,重布线结构220的绝缘层的厚度可小于另一种类型的布线结构的绝缘层的厚度,且因此可使得绝缘层内或绝缘层上形成的布线的电阻和/或电感减小。通过使用重布线结构220来降低信号损耗、电阻和/或电感,可改善封装体的信号完整性及效率,且可降低封装体的电子噪声,尤其是在较高速度操作时。这可改善高速操作的性能,例如可改善可以更高速度操作的串行器/解串行器(“SerDes”)电路或封装体内的其他电路的高速操作的性能。在一些情况下,重布线结构220的总厚度可小于另一种类型的布线结构的厚度,且因此使用重布线结构220可使得封装体的总厚度更小。另外,封装体的功能测试可在与制造相同的设施中执行,这可减少总体的测试时间及成本。
根据实施例,一种方法包括:在载体衬底之上形成第一模制材料层;在所述第一模制材料层之上形成穿孔;将第一集成无源器件放置在所述第一模制材料层之上,其中所述第一集成无源器件在横向上相邻于所述穿孔;在所述第一模制材料层之上沉积第二模制材料层,所述第二模制材料层在横向上环绕所述穿孔且在横向上环绕所述第一集成无源器件;在所述第二模制材料层之上形成重布线结构,所述重布线结构电连接到所述穿孔;以及将半导体器件放置在所述重布线结构上。在实施例中,所述方法包括:在所述载体衬底之上形成多个接触焊盘,其中所述第一模制材料层在横向上环绕所述多个接触焊盘。在实施例中,所述方法包括:将第二集成无源器件放置在所述重布线结构上。在实施例中,所述第一集成无源器件包括多层式陶瓷电容器(MLCC)。在实施例中,形成所述重布线结构包括:在所述第二模制材料层的顶表面上以及在所述第一模制材料层的多个侧壁上及在所述第二模制材料层的多个侧壁上形成绝缘层。在实施例中,所述重布线结构电连接到所述第一集成无源器件。在实施例中,所述方法包括:在所述第二模制材料层上形成金属化层,其中所述重布线结构通过所述金属化层电连接到所述穿孔。在实施例中,所述第一集成无源器件不包含所述金属化层。
根据实施例,一种方法包括:在载体衬底上形成多个接触焊盘;在所述多个接触焊盘之上形成第一模制材料层;在所述第一模制材料层上形成第一金属化层,所述第一金属化层通过所述第一模制材料层电连接到所述多个接触焊盘;在所述第一金属化层上形成电连接到所述第一金属化层的多个穿孔;将第一无源器件贴合到所述第一金属化层;在所述第一模制材料层、所述第一无源器件及所述多个穿孔之上形成第二模制材料层;在所述第二模制材料层上形成重布线结构,所述重布线结构电连接到所述多个穿孔且电连接到所述第一无源器件;将半导体管芯贴合到所述重布线结构,所述半导体管芯电连接到所述重布线结构。在实施例中,所述第一无源器件在横向上设置在所述多个穿孔中的两个穿孔之间。在实施例中,所述方法包括:对所述第二模制材料层执行平坦化工艺,所述平坦化工艺暴露出所述第一无源器件的表面。在实施例中,将所述无源器件贴合到所述金属化层包括:将所述第一无源器件电连接到所述金属化层。在实施例中,所述方法包括:将第二无源器件贴合到所述多个接触焊盘中的接触焊盘。在实施例中,所述方法包括:在所述第二模制材料层上形成第二金属化层。在实施例中,所述方法包括:形成穿过所述第一模制材料层延伸到所述多个接触焊盘的多个通孔。
根据实施例,一种封装体包括:第一层模制材料;第一金属化层,位于所述第一层模制材料上;第二层模制材料,位于所述第一金属化层及所述第一层模制材料上;第二金属化层,位于所述第二层模制材料上;多个穿孔,位于所述第二层模制材料内,所述多个穿孔从所述第一金属化层延伸到所述第二金属化层;多个集成无源器件,位于所述第二层模制材料内;重布线结构,以电性方式位于所述第二金属化层及所述第二层模制材料上,所述重布线结构连接到所述多个穿孔及所述多个集成无源器件;以及至少一个半导体器件,位于所述重布线结构上,所述至少一个半导体器件连接到所述重布线结构。在实施例中,所述第一层模制材料是与所述第二层模制材料相同的材料。在实施例中,所述多个集成无源器件的多个表面、所述多个穿孔的多个表面及所述第二层模制材料的表面是共面的。在实施例中,所述第一层模制材料的侧壁、所述第二层模制材料的侧壁及所述重布线结构的侧壁是共面的。在实施例中,所述多个集成无源器件包括至少一个多层式陶瓷电容器(MLCC)。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解,其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本公开的精神及范围,而且他们可在不背离本公开的精神及范围的条件下在本文中作出各种改变、代替及变更。
Claims (1)
1.一种封装体,包括:
第一层模制材料;
第一金属化层,位于所述第一层模制材料上;
第二层模制材料,位于所述第一金属化层及所述第一层模制材料上;
第二金属化层,位于所述第二层模制材料上;
多个穿孔,位于所述第二层模制材料内,所述多个穿孔从所述第一金属化层延伸到所述第二金属化层;
多个集成无源器件,位于所述第二层模制材料内;
重布线结构,以电性方式位于所述第二金属化层及所述第二层模制材料上,所述重布线结构连接到所述多个穿孔及所述多个集成无源器件;以及
至少一个半导体器件,位于所述重布线结构上,所述至少一个半导体器件连接到所述重布线结构。
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