CN112242116A

CN112242116A - Method of driving display panel and display apparatus for performing the same

Info

Publication number: CN112242116A
Application number: CN202010689873.3A
Authority: CN
Inventors: 朴世爀; 权祥颜; 金鸿洙; 卢珍永; 李孝真
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2019-07-18
Filing date: 2020-07-17
Publication date: 2021-01-19
Also published as: US20220148524A1; US11244633B2; EP3767614A1; US20210020113A1; KR20210010736A; US11694635B2

Abstract

A method of driving a display panel and a display apparatus for performing the method are provided. The method of driving a display panel includes: dividing an input image into a plurality of segments; generating a flicker value for a segment of the plurality of segments; determining whether to compensate for a flicker value of a segment according to a segment size; compensating for a flicker value of the segment based on the segment size; determining a frame rate of the display panel based on the flicker values of the segments; and outputting the data voltage to the display panel at a frame rate. The flicker value of a segment is compensated based on the flicker value of the segment and the flicker values of the segments adjacent to the segment.

Description

Method of driving display panel and display apparatus for performing the same

Technical Field

The technical field relates to a method of driving a display panel and a display apparatus for performing the method, such as a method of driving a display panel for reducing power consumption and enhancing display quality, as an example.

Background

Recently, methods for minimizing power consumption of electronic devices such as tablet computers and notebook computers have been studied.

In order to minimize power consumption of an electronic device including a display panel, power consumption of the display panel may be minimized. That is, when the display panel displays a still image, the display panel may be driven at a relatively low frequency, so that power consumption of the display panel may be reduced.

When the display panel is driven at a relatively low frequency, flicker may be generated, thereby degrading display quality.

Disclosure of Invention

Exemplary embodiments of the inventive concept provide a method of driving a display panel capable of reducing power consumption and enhancing display quality.

Exemplary embodiments of the inventive concept also provide a display apparatus for performing the above-described method.

In an exemplary embodiment of a method of driving a display panel according to the inventive concept, the method includes: dividing an input image into a plurality of segments; generating a flicker value for a segment of the plurality of segments; compensating for a flicker value of a segment based on a segment size, the flicker value of the segment, and a plurality of flicker values of a plurality of adjacent segments located around the segment; determining a frame rate of the display panel based on the flicker values of the segments; and outputting the data voltage to the display panel at a frame rate. .

In an exemplary embodiment, compensating for flicker values of segments may include: determining not to compensate for a flicker value of a segment when the segment size is equal to or greater than a compensation threshold; and determining to compensate for the flicker value of the segment when the segment size is less than the compensation threshold.

In an exemplary embodiment, the method may further include: determining a compensation size, wherein the compensation size represents the flicker value of the compensation target segment and the number of the plurality of flicker values of the plurality of segments adjacent to the compensation target segment; and wherein the compensation size is used to compensate the compensation of the target segment when the segment size is less than the compensation threshold.

In an exemplary embodiment, the compensation size may be determined such that the product of the segment size and the compensation size is equal to or greater than the compensation threshold.

In an exemplary embodiment, the compensation size may be determined to be the smallest integer that satisfies the product of the segment size and the compensation size being equal to or greater than the compensation threshold.

In an exemplary embodiment, determining the magnitude of the compensation may include: determining a first compensation magnitude representing a flicker value of a compensation target section and a number of a plurality of flicker values of a plurality of sections adjacent to the compensation target section in a first direction; and determining a second compensation magnitude representing the flicker value of the compensation target section and the number of the plurality of flicker values of a plurality of sections adjacent to the compensation target section in a second direction different from the first direction, wherein the first compensation magnitude and the second compensation magnitude are each used for compensation of the compensation target section.

In an exemplary embodiment, the method may further include determining a compensation size. The size of the compensation may be determined by dividing the compensation threshold by the segment size. Compensating for flicker values of the segments may include: when the segment size is equal to or less than 1, determining not to compensate the flicker value of the segment; and compensating for a flicker value of the segment when the segment size is greater than 1.

In an exemplary embodiment, determining the magnitude of the compensation may include: determining a first compensation magnitude representing the flicker value of the compensation target section and the number of flicker values of a plurality of sections adjacent to the compensation target section in the first direction; and determining a second compensation magnitude representing the flicker value of the compensation target section and the number of the plurality of flicker values of a plurality of sections adjacent to the compensation target section in a second direction different from the first direction, wherein the first compensation magnitude and the second compensation magnitude are used for compensation of the compensation target section.

In an exemplary embodiment, the method may further include: it is determined whether the input image represents a still image or a video image. When the input image represents a still image, the frame rate of the display panel may be determined based on the flicker values of the segments.

In an exemplary embodiment, generating the flicker values for the segments may include: converting the luminance of the plurality of pixels into a plurality of flicker values of the plurality of pixels; and operating on a plurality of flicker values for a plurality of pixels in the segment.

In an exemplary embodiment, operating on a plurality of flicker values for a plurality of pixels in a segment may include: a plurality of flicker values for a plurality of pixels in a segment are summed.

In an exemplary embodiment, operating on a plurality of flicker values for a plurality of pixels in a segment may include: setting a plurality of weights for the plurality of pixels according to a plurality of positions of the plurality of pixels; and operating a weighted summation of the plurality of flicker values for the plurality of pixels by using the plurality of weights for the plurality of pixels.

In an exemplary embodiment, determining the frame rate of the display panel may include: the maximum of the plurality of flicker values for the plurality of segments is compared to a threshold.

In an exemplary embodiment, determining the frame rate of the display panel may include: an average value of the plurality of flicker values of the plurality of segments is compared to a threshold value, the average value being greater than a predetermined flicker value.

In an exemplary embodiment of a display device according to the present inventive concept, the display device includes a display panel, a low frequency driver, and a data driver. The display panel is configured to display an image. The low frequency driver is connected to the display panel and configured to divide an input image into a plurality of segments, generate flicker values of the segments of the plurality of segments, determine whether to compensate the flicker values of the segments depending on segment sizes, compensate the flicker values of the segments depending on the segment sizes, and determine a frame rate of the display panel based on the flicker values of the segments. The data driver is connected to the display panel and configured to output the data voltage to the display panel at a frame rate.

In an exemplary embodiment, the low frequency driver may be configured to determine not to compensate for the flicker value of the segment when the segment size is equal to or greater than a compensation threshold. The low frequency driver may be configured to determine to compensate for a flicker value of the segment when the segment size is less than a compensation threshold.

In an exemplary embodiment, the low frequency driver may be configured to determine a compensation magnitude representing a flicker value of the compensation target section and a number of a plurality of flicker values of a plurality of sections adjacent to the compensation target section, the compensation magnitude being used for compensation of the compensation target section when the section size is less than a compensation threshold value.

In an exemplary embodiment, the low frequency driver may be configured to determine the magnitude of the compensation. The compensation size may be determined based on the flicker value of the compensation target section and the number of the plurality of flicker values of the plurality of sections adjacent to the compensation target section, the compensation size being used for compensation of the compensation target section. The size of the compensation may be determined by dividing the compensation threshold by the segment size. The low frequency driver may be configured to determine not to compensate for a flicker value of the segment when the segment size is equal to or less than 1. The low frequency driver may be configured to determine to compensate for a flicker value of the segment when the segment size is greater than 1.

In an exemplary embodiment, the low frequency driver may include a still image determiner, wherein the still image determiner is configured to determine whether the input image represents a still image or a video image. The low frequency driver may be configured to determine a frame rate of the display panel based on the flicker values of the segments when the input image represents a static image.

According to the method of driving the display panel and the display apparatus for performing the method, the frame rate is determined according to the image displayed on the display panel, thereby making it possible to reduce power consumption of the display apparatus. In addition, the frame rate is determined by using the flicker value of the segment of the image on the display panel, so that the flicker of the image can be prevented and the display quality of the display panel can be enhanced. In addition, the flicker value of a segment is compensated by using a plurality of flicker values of a plurality of adjacent segments, thereby making it possible to further enhance the display quality of the display panel.

Drawings

The above and other features and advantages of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

fig. 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present inventive concept;

FIG. 2 is a block diagram illustrating the drive controller of FIG. 1;

FIG. 3 is a block diagram showing the low frequency drive of FIG. 2;

FIG. 4 is a conceptual diagram illustrating a segment defined by the segment determiner of FIG. 3;

FIGS. 5A and 5B illustrate flicker values according to a segment of a first image;

FIGS. 6A and 6B illustrate flicker values according to a segment of a second image;

FIGS. 7A and 7B illustrate a method of compensating for flicker values of a segment from a first image;

FIGS. 8A and 8B illustrate a method of compensating for flicker values of a segment from a second image;

FIGS. 9A, 9B, and 9C illustrate a method of compensating for flicker values of a segment regardless of the segment size;

FIG. 10 is a flowchart illustrating the operation of the compensation determiner, the compensation size determiner, the flicker value compensator, and the frame rate determiner of FIG. 3;

fig. 11 is a block diagram illustrating a low frequency driver of a display apparatus according to an exemplary embodiment of the present inventive concept;

FIG. 12 is a flowchart illustrating the operation of the compensation magnitude and compensation determiner, flicker value compensator, and frame rate determiner of FIG. 11;

fig. 13 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present inventive concept;

fig. 14 is a circuit diagram showing a pixel of the display panel of fig. 13; and

fig. 15 is a timing chart showing input signals applied to the pixel of fig. 14.

Detailed Description

Hereinafter, embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings. Each of the various components referred to in this specification, including but not limited to, for example, "generators," "drivers," "converters," "determiners," "compensators," "controllers," may be hardware components, such as, for example, integrated circuits, microprocessors, and the like. Alternatively, at least some of these components may be implemented in software.

Exemplary embodiments are described with reference to the accompanying drawings. The described embodiments may be modified in various ways, all without departing from the spirit or scope of the present disclosure.

In the present disclosure, like reference numerals may indicate like elements.

In the drawings, the size of elements may be exaggerated for clarity.

Although the terms first, second, etc. may be used to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. A first element could be termed a second element without departing from the teachings of one or more embodiments. The description of an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," and the like may be used to distinguish different classes or groups of elements. For the sake of brevity, the terms "first", "second", etc. may denote "a first type (or first group)", "a second type (or second group)", etc., respectively.

When a first element is referred to as being "on" a second element, the first element can be directly on the second element, or one or more intervening elements may be present between the first and second elements. When a first element is referred to as being "directly on" a second element, there are no intervening elements (other than the ambient element, such as air) intended between the first and second elements. When a first element is referred to as being "connected to" a second element, the first element can be directly connected (physically and/or electrically) and/or attached to the second element, or one or more intervening elements may be connected between the first and second elements.

In this specification, unless explicitly described to the contrary, the word "comprise", and variations such as "comprises" or "comprising", may imply the inclusion of stated elements but may not necessarily exclude any other elements.

The term "connected" may mean "electrically connected". The term "insulating" may mean "electrically insulating".

Fig. 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the inventive concept.

Referring to fig. 1, the display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500, each of which may be a hardware component such as, for example, an integrated circuit, a microprocessor, and the like. In alternative embodiments, at least some of these components may be implemented in software.

In some exemplary embodiments, the driving controller 200 and the data driver 500 may be integrally formed (e.g., formed as a single component). In some exemplary embodiments, the driving controller 200, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed. The driving module including at least the integrally formed driving controller 200 and the data driver 500 may be referred to as a timing controller embedded data driver (TED).

The display panel 100 has a display area displaying an image and a peripheral area adjacent to the display area.

The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels connected to the plurality of gate lines GL and the plurality of data lines DL. The gate line GL extends in a first direction D1, and the data line DL extends in a second direction D2 intersecting the first direction D1.

The driving controller 200 receives input image data IMG and input control signals CONT from an external device (not shown). The input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also comprise white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signals CONT may include a master clock signal and a data enable signal. The input control signals CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3, each based on the input control signal CONT. The driving controller 200 also generates the DATA signal DATA based on the input image DATA IMG.

The driving controller 200 generates the first control signal CONT1 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signals CONT1 may also include a vertical start signal and a gate clock signal. The first control signal CONT1 is used to control the operation of the gate driver 300.

The driving controller 200 generates the second control signal CONT2 based on the input control signal CONT and outputs the second control signal CONT2 to the data driver 500. The second control signals CONT2 include a horizontal start signal and a load signal. The second control signal CONT2 is used to control the operation of the data driver 500.

The driving controller 200 generates the DATA signal DATA based on the input image DATA IMG. The driving controller 200 outputs the DATA signal DATA to the DATA driver 500.

In an exemplary embodiment, the driving controller 200 may adjust the frame rate of the display panel 100 based on the input image data IMG.

The driving controller 200 generates a third control signal CONT3 based on the input control signal CONT and outputs the third control signal CONT3 to the gamma reference voltage generator 400. The third control signal CONT3 is used to control the operation of the gamma reference voltage generator 400.

The structure and operation of the driving controller 200 are explained in detail by referring to fig. 2 to 10.

The gate driver 300 generates a gate signal driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 outputs a gate signal to the gate line GL. For example, the gate driver 300 may sequentially output a plurality of gate signals to a plurality of gate lines GL. The gate driver 300 may be mounted on the display panel 100, or the gate driver 300 may be integrated on the display panel 100.

The gamma reference voltage generator 400 generates the gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 supplies the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the DATA signal DATA.

In an exemplary embodiment, the gamma reference voltage generator 400 may be disposed in the driving controller 200 or in the data driver 500.

The DATA driver 500 receives the second control signal CONT2 and the DATA signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The DATA driver 500 converts the DATA signal DATA into a DATA voltage having an analog type by using the gamma reference voltage VGREF. The data driver 500 outputs a data voltage to the data line DL.

Fig. 2 is a block diagram illustrating the driving controller 200 of fig. 1. Fig. 3 is a block diagram illustrating the low frequency driver 240 of fig. 2. Fig. 4 is a diagram illustrating a segment defined by the segment determiner 242 of fig. 3.

Referring to fig. 1 to 4, the driving controller 200 includes an image converter 220, a low frequency driver 240, and a signal generator 260.

The image converter 220 compensates the gray DATA of the input image DATA IMG and rearranges the input image DATA IMG to generate the DATA signal DATA. The DATA signal DATA may correspond to a DATA type of the DATA driver 500 and may have a digital type. The image converter 220 outputs the DATA signal DATA to the DATA driver 500.

For example, the image converter 220 may include an adaptive color correction part (not shown) and a dynamic capacitance compensation part (not shown). The adaptive color correction section receives gradation data of the input image data IMG and operates adaptive color correction ("ACC"). The adaptive color correction part may compensate the gray data by using a gamma curve. The dynamic capacitance compensation part applies dynamic capacitance compensation ("DCC") for compensating for gray data of the current frame data by using the previous frame data and the current frame data.

The low frequency driver 240 receives input image data IMG. The low frequency driver 240 determines a frame rate FR of the display panel 100 based on the input image data IMG. The low frequency driver 240 may output the frame rate FR to the signal generator 260. The low frequency driver 240 may output the frame rate FR to the image converter 220.

The signal generator 260 receives the input control signal CONT. The signal generator 260 generates the first control signal CONT1 to control the driving timing of the gate driver 300 based on the input control signal CONT and the frame rate FR. The signal generator 260 generates the second control signal CONT2 to control the driving timing of the data driver 500 based on the input control signal CONT and the frame rate FR. The signal generator 260 generates a third control signal CONT3 to control the driving timing of the gamma reference voltage generator 400 based on the input control signal CONT and the frame rate FR.

The signal generator 260 outputs the first control signal CONT1 to the gate driver 300. The signal generator 260 outputs the second control signal CONT2 to the data driver 500. The signal generator 260 outputs the third control signal CONT3 to the gamma reference voltage generator 400.

The low frequency driver 240 includes a static image determiner 241, a segment determiner 242, a pixel flicker determiner 243, a segment flicker determiner 244, a compensation determiner 245, a compensation size determiner 246, a flicker value compensator 247, and a frame rate determiner 248, each of which may be hardware components such as, for example, an integrated circuit, a microprocessor, and the like.

The still image determiner 241 receives input image data IMG. The still image determiner 241 determines whether the input image data IMG represents a still image or a video image. Video images may also be referred to as dynamic images and may refer to images depicting movement and/or motion.

The segment determiner 242 divides the input image data IMG into a plurality of segments S1 to S100. Although the input image data IMG is divided into one hundred sections of ten rows and ten columns in fig. 4, the inventive concept is not limited to the number of the sections.

Each of the plurality of segments S1 through S100 may have a rectangular shape. For human vision, flicker is more perceived in a rectangular shape including a long side extending in the horizontal direction than in a rectangular shape including a long side extending in the vertical direction. Accordingly, each of the plurality of segments S1 through S100 may have a rectangular shape including a long side extending in the horizontal direction to effectively prevent flicker in the rectangular shape including the long side extending in the horizontal direction. Alternatively, in other exemplary embodiments, each of the plurality of segments S1 through S100 may have a square shape. The segment size may mean the size of one of the plurality of segments S1 through S100. The segment size may be expressed as the number of pixels in the horizontal direction and the number of pixels in the vertical direction.

The pixel flicker determiner 243 determines a flicker value according to the luminance of the pixel. The flicker value represents the degree of flicker perceived by the user. The flicker value of the pixel may vary according to the luminance of the pixel and the frame rate FR of the display panel 100. For example, the flicker value may be generated by visual inspection by changing the brightness of the pixel and/or the frame rate FR of the display panel being tested. In general, the flicker value may be relatively high in a low luminance region. In addition, when the frame rate FR is low, the flicker value may be relatively high. In addition, the flicker value may vary according to the characteristics of the display panel 100.

The pixel flicker determiner 243 may determine the flicker value of the pixel by using a plurality of flicker values according to the luminance of a plurality of pixels and a plurality of frame rates FR.

For example, the pixel flicker determiner 243 may include a look-up table including a plurality of flicker values according to the luminance of a plurality of pixels and a plurality of frame rates FR.

The input image data IMG may include red gray scale R, green gray scale G, and blue gray scale B. The input image data IMG may be determined in the RGB color space. The low frequency driver 240 may extract the luminance of the pixel from the input image data IMG in the RGB color space. For example, the low frequency driver 240 may include an RGB to Y converter to extract the luminance of the pixel from the input image data IMG in the RGB color space.

The segment flicker determiner 244 generates flicker values for the segments. The segment flicker determiner 244 generates flicker values of the segments by using the flicker values of the pixels.

For example, the segment flicker determiner 244 may sum a plurality of flicker values for a plurality of pixels in a segment.

When a segment includes one hundred pixels, the pixel flicker determiner 243 may determine one hundred flicker values for the one hundred pixels, respectively, and the segment flicker determiner 244 may sum the one hundred flicker values for the one hundred pixels to generate a flicker value for the segment.

Alternatively, the segment flicker determiner 244 may set a plurality of weights for the plurality of pixels according to a plurality of positions of the plurality of pixels. The segment flicker determiner 244 may operate a weighted summation of a plurality of flicker values for a plurality of pixels to generate a flicker value for a segment.

For example, the outer portion of the display panel 100 is generally weaker than flicker, so that pixels in the outer portion may have relatively high weights.

Alternatively, the segment flicker determiner 244 may perform various operations on a plurality of flicker values of a plurality of pixels to generate flicker values of the segments.

For example, when the display panel 100 has one hundred segments, the segment flicker determiner 244 generates one hundred flicker values of the first segment S1 through the one hundred segments S100.

In an exemplary embodiment, the segment determiner 242, the pixel flicker determiner 243, and the segment flicker determiner 244 may operate when the input image data IMG represents a still image.

In an exemplary embodiment, the positions of the segment determiner 242 and the pixel flicker determiner 243 may be switched to each other.

The compensation determiner 245 may determine whether the flicker value of the segment is compensated according to the segment size.

For example, when the segment size is equal to or greater than the minimum size TH, the flicker value is not compensated, and below the minimum size TH, the flicker is perceptible to the user. The minimum size TH at which flicker is perceived by the user may be referred to as a compensation threshold TH.

In contrast, when the segment size is smaller than the minimum size TH, the flicker value of the segment may be compensated based on the flicker value of the segment and the flicker values of the neighboring segments, while below the minimum size TH, the flicker is perceivable to the user.

When the segment size is less than the compensation threshold TH, the compensation size determiner 246 may determine a mask size (filter size) to compensate for the flicker value. The mask size (filter size) may mean the number of the compensation target section and the plurality of sections adjacent to the compensation target section and may be used for compensation. The mask size (filter size) may mean a flicker value of the compensation target section and the number of a plurality of flicker values of a plurality of sections adjacent to the compensation target section and may be used for the compensation. The mask size (filter size) may be referred to as the compensation size.

The flicker value compensator 247 may compensate the flicker value of the segment based on the flicker value of the segment and a plurality of flicker values of a plurality of adjacent segments. The flicker value compensator 247 may compensate the flicker value of the segment based on the flicker value of the segment corresponding to the compensation size and a plurality of flicker values of a plurality of adjacent segments.

The frame rate determiner 248 determines the frame rate FR of the display panel 100 based on the flicker values of the segments.

Frame rate determiner 248 may compare the maximum flicker value for the plurality of segments to a threshold to determine a frame rate FR.

The frame rate determiner 248 may compare an average value of a plurality of flicker values of a plurality of segments having a plurality of relatively high flicker values with a threshold value to determine the frame rate FR of the display panel 100. For example, the plurality of relatively high flicker values may be greater than a predetermined flicker value.

Alternatively, the frame rate determiner 248 may perform various operations on a plurality of flicker values of a plurality of segments to determine the frame rate FR.

In an exemplary embodiment, when the input image data IMG represents a video image, the frame rate determiner 248 may determine the frame rate FR as a high frequency regardless of the flicker value of the segment. When the input image data IMG represents a still image, the frame rate determiner 248 may determine the frame rate FR as one of a plurality of low frequencies based on the flicker value of the segment.

Fig. 5A and 5B show flicker values according to a segment of a first image. Fig. 6A and 6B show flicker values according to a segment of a second image. Fig. 7A and 7B illustrate a method of compensating for flicker values of segments according to a first image. Fig. 8A and 8B illustrate a method of compensating a flicker value of a segment according to a second image.

Hereinafter, a method of determining the flicker value of the segment and the frame rate FR corresponding to the flicker value is explained with reference to fig. 5A to 8B.

In fig. 5A, the input image of the display panel 100 is a first image. In the first image, the plurality of segments S32 to S35, S42 to S45, and S52 to S55 of three rows and four columns have flicker values corresponding to 60Hz, and the segments other than the plurality of segments S32 to S35, S42 to S45, and S52 to S55 of three rows and four columns have flicker values corresponding to 1 Hz.

The plurality of flicker values of the plurality of segments may be represented as shown in fig. 5B. The frame rate determiner 248 may determine the frame rate FR of the display panel 100 as 60Hz based on a maximum value of the plurality of flicker values of the plurality of segments. As used herein, "maximum value" refers to the maximum flicker value of a segment.

In fig. 6A, the input image of the display panel 100 is a second image. In the second image, the segment S43 has a flicker value corresponding to 60Hz, and the segments other than the segment S43 have flicker values corresponding to 1 Hz.

The plurality of flicker values of the plurality of segments may be represented as shown in fig. 6B. The frame rate determiner 248 may determine the frame rate FR of the display panel 100 as 60Hz based on a maximum value of the plurality of flicker values of the plurality of segments.

For example, when the segment size is considerably small and a plurality of segments S32 to S35, S42 to S45, and S52 to S55 of three rows and four columns have a high flicker value (as shown in fig. 5A), high frame rate driving may be required to prevent the user from perceiving flicker. In contrast, when the segment size is quite small and the single segment S43 has a high flicker value (as shown in fig. 6A), the flicker of the single segment S43 may not be perceived by the user. In the latter case, high frame rate driving may not be required. Avoiding the perception of flicker by using multiple high flicker values for multiple adjacent segments (e.g., by adjusting the frame rate drive speed) is referred to herein as "compensation".

When the flicker values of the segments are not compensated based on the flicker values of the adjacent segments, the display panel in fig. 5A and the display panel in fig. 6A are driven at a high frame rate of 60 Hz. In contrast, when the flicker value of a segment is compensated based on a plurality of flicker values of a plurality of adjacent segments, the display panel in fig. 5A is driven at a high frame rate of 60Hz, and the display panel in fig. 6A may be driven at a frame rate less than 60 Hz.

In fig. 7A, the input image of the display panel 100 is a first image similar to the first image of fig. 5A. In fig. 7B, the flicker values of the segments may be compensated by using a plurality of flicker values of a plurality of adjacent segments.

When the compensation size is 3 × 3, the flicker value of the forty-second segment S42 may be compensated by using a plurality of flicker values of the plurality of segments S31, S32, S33, S41, S42, S43, S51, S52, and S53. For example, the flicker value of the forty-second segment S42 may be compensated by using an average value of a plurality of flicker values of a plurality of segments S31, S32, S33, S41, S42, S43, S51, S52, and S53. For example, the flicker value of the forty-second segment S42 may be compensated by using weighted values of a plurality of flicker values of a plurality of segments S31, S32, S33, S41, S42, S43, S51, S52, and S53. For example, the flicker value of the forty-second segment S42 may have the highest weight, and the weight may decrease as the distance from the forty-second segment S42 increases.

When the compensation size is 3 × 3, the flicker value of the forty-th section S43 may be compensated by using a plurality of flicker values of the plurality of sections S32, S33, S34, S42, S43, S44, S52, S53, and S54. When the compensation size is 3 × 3, the flicker value of the forty-fourth segment S44 may be compensated by using a plurality of flicker values of the plurality of segments S33, S34, S35, S43, S44, S45, S53, S54, and S55.

When the compensation size is 5 × 5, the flicker value of the forty-third section S43 may be compensated by using a plurality of flicker values of a plurality of sections S21, S22, S23, S24, S25, S31, S32, S33, S34, S35, S41, S42, S43, S44, S45, S51, S52, S53, S54, S55, S61, S62, S63, S64, and S65. When the compensation size is 5 × 5, the flicker value of the forty-fourth segment S44 may be compensated by using a plurality of flicker values of a plurality of segments S22, S23, S24, S25, S26, S32, S33, S34, S35, S36, S42, S43, S44, S45, S46, S52, S53, S54, S55, S56, S62, S63, S64, S65, and S66.

The flicker value of the section compensated by the flicker value compensator 247 may be represented as shown in fig. 7B. The frame rate determiner 248 may determine the frame rate FR of the display panel 100 as 60Hz based on a maximum value of the plurality of flicker values of the plurality of segments.

In fig. 8A, the input image of the display panel 100 is a second image similar to the second image of fig. 6A. In fig. 8B, the flicker values of the segments may be compensated by using a plurality of flicker values of a plurality of adjacent segments.

The flicker value of the section compensated by the flicker value compensator 247 may be represented as shown in fig. 8B. The frame rate determiner 248 may determine the frame rate FR of the display panel 100 as 15Hz based on a maximum value of the plurality of flicker values of the plurality of segments.

In fig. 8B, when the flicker value of the forty-third segment S43 is a maximum value, the frame rate determiner 248 may compare the flicker value of the forty-third segment S43 with a plurality of frame rate threshold values. The flicker value of the forty-third segment S43 is greater than the threshold value of 1Hz and equal to or less than the threshold value of 15Hz, so that the frame rate FR of the display panel 100 may be determined to be 15 Hz.

In fig. 6B, when the segment size is relatively small, the blinking may not be displayed to the user. However, the frame rate FR is determined only by using the flicker value of the segment in fig. 6B, and the display panel 100 may be driven at a frame rate higher than a required frame rate. In contrast, in fig. 8B, the flicker value of a segment is compensated by using a plurality of flicker values of a plurality of adjacent segments, so that the frame rate of the display panel 100 can be reduced without unnecessary degradation of the display quality of the display panel 100.

When the flicker value of a segment is compensated for by using a plurality of flicker values of a plurality of adjacent segments regardless of the segment size, the display panel 100 may be driven at an inappropriate frame rate FR.

Fig. 9A to 9C illustrate a method of compensating for flicker values of segments regardless of segment sizes.

In fig. 9A, the plurality of segments S35, S44, S45, S46, S54, S55, S56, S67, S68, S77, and S78 may represent a gray scale value of 19, and the plurality of segments S34, S36, S37, S38, S47, S48, S57, S58, S64, S65, S66, S74, S75, and S76 may represent a gray scale value of 255.

As shown in fig. 9B, the flicker value of the gradation value of 19 may be 204, and as shown in fig. 9B and 9C, the frame rate FR corresponding to the gradation value of 19 may be 30 Hz. As shown in fig. 9B, the flicker value of the gradation value of 255 may be 0, and as shown in fig. 9B and 9C, the frame rate FR corresponding to the gradation value of 255 may be 1 Hz.

In fig. 9A to 9C, the segment size is large enough so that the flicker of a single segment can be perceived by the user. In this case, when the display panel 100 is driven at the frame rate FR of 30Hz corresponding to the gradation value of 19, flicker may not be perceived by the user.

When the flicker value of the segment is compensated by the flicker value compensator 247 by using the compensation size CS of 5 × 5 regardless of the segment size, the flicker value corresponding to the compensation size CS of 5 × 5 may be an average value of a plurality of segments S34, S35, S36, S37, S38, S44, S45, S46, S47, S48, S54, S55, S56, S57, S58, S64, S65, S66, S67, S68, S74, S75, S76, S77, and S78. The average value was 89.8. According to fig. 9C, the frame rate FR corresponding to the flicker value of 89.8 may be 2 Hz. When the display panel 100 is driven at the frame rate FR of 2Hz, the flicker of the display panel 100 may not be perceived by the user.

Fig. 10 is a flowchart illustrating operations of the compensation determiner 245, the compensation size determiner 246, the flicker value compensator 247, and the frame rate determiner 248 of fig. 3.

Referring to fig. 1 to 10, the low frequency driver 240 of the present exemplary embodiment may include a compensation determiner 245 to determine whether to compensate for a flicker value of a segment according to a segment size (step S100).

When the segment size is equal to or greater than the compensation threshold TH, the compensation determiner 245 may determine not to compensate for the flicker value of the segment. When the segment size is less than the compensation threshold TH, the compensation determiner 245 may determine to compensate for the flicker value of the segment.

When the segment size is large enough such that the flicker of a single segment is perceived by the user, steps S200 and S300 of compensating for the flicker value of the segment may be skipped. Accordingly, the frame rate FR can be determined by using the flicker value of the uncompensated segment (step S400).

In contrast, when the segment size is small such that the flicker of a single segment is not perceived by the user, the flicker value of the segment may be compensated through steps S200 and S300. Accordingly, the frame rate FR may be determined by using the flicker value of the compensated segment (step S400).

When the segment size is smaller than the compensation threshold TH, the compensation size determiner 246 may determine the compensation size CS, which represents the flicker value of the segment and the number of the plurality of flicker values of the plurality of neighboring segments for compensating the flicker value of the segment (step S200).

The compensation size CS may be determined such that the product of the segment size and the compensation size CS is equal to or greater than the compensation threshold TH. For example, the compensation size CS may be determined to be the smallest integer that satisfies that the product of the segment size and the compensation size CS is equal to or greater than the compensation threshold TH.

For example, when the compensation threshold TH (meaning the segment size at which the user perceives flicker) is 300 × 300 and the actual segment size is 512 × 512, the steps S200 and S300 of compensating the flicker value of the segment may be skipped, and the frame rate FR may be determined by using the flicker value of the segment that is not compensated.

For example, when the compensation threshold TH (meaning the segment size at which flicker is perceived by the user) is 300 × 300 and the actual segment size is 64 × 64, the flicker value of the segment may be compensated through steps S200 and S300, and the frame rate FR may be determined by using the flicker value of the compensated segment.

Herein, the compensation size CS may be determined as a value greater than 4.6875 × 4.6875. The compensation size CS may be determined from a plurality of values 5 x 5, 6 x 6, 7 x 7 and 8 x 8, etc. For example, the compensation size CS may be determined as a value of 5 × 5.

The compensation magnitude determiner 246 may independently determine the first compensation magnitude and the second compensation magnitude. The first compensation magnitude means a flicker value of a segment and the number of a plurality of flicker values of a plurality of adjacent segments for compensating the flicker value of the segment in the first direction D1 (row direction). The second compensation magnitude means the flicker value of the segment and the number of flicker values of the neighboring segments for compensating the flicker value of the segment in the second direction D2 (column direction).

As explained above, the first and second compensation magnitudes having values such as 5 × 5, 6 × 6, 7 × 7, 8 × 8, and the like may be equal to each other. Alternatively, the first and second compensation sizes may be different from each other when the degree of flicker is different in the first direction D1 from the degree of flicker in the second direction D2 according to the characteristics of the display panel 100.

The flicker value compensator 247 may compensate the flicker value of the segment based on the compensation size CS (step S300).

The frame rate determiner 248 may determine the frame rate FR based on the compensated flicker value or the uncompensated flicker value (step S400).

According to the present exemplary embodiment, the frame rate FR is determined according to the image displayed on the display panel 100, thereby making it possible to reduce the power consumption of the display apparatus. In addition, the frame rate FR is determined by using the flicker value of the segment of the image displayed on the display panel 100, so that flicker of the image (e.g., flicker perceived by a user) may be prevented and the display quality of the display panel 100 may be enhanced. In addition, the flicker value of the segment is compensated by using the flicker values of the adjacent segments, thereby making it possible to further enhance the display quality of the display panel 100.

Fig. 11 is a block diagram illustrating a low frequency driver 240A of a display apparatus according to an exemplary embodiment of the inventive concept. Fig. 12 is a flowchart illustrating operations of the compensation magnitude and compensation determiner 245A, the flicker value compensator 247, and the frame rate determiner 248 of fig. 11.

The method of driving a display panel and the display apparatus according to the present exemplary embodiment are substantially the same as those of the previous exemplary embodiment explained with reference to fig. 1 to 10, except for the structure and operation of the low frequency driver. Therefore, the same reference numerals will be used to refer to the same or similar parts as those described in the previous exemplary embodiment of fig. 1 to 10, and any repetitive explanation regarding the above elements will be omitted.

Referring to fig. 1, 2, 4 to 9C, 11 and 12, the display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

The driving controller 200 includes an image converter 220, a low frequency driver 240A, and a signal generator 260.

The low frequency driver 240A receives input image data IMG. The low frequency driver 240A determines the frame rate FR of the display panel 100 based on the input image data IMG. The low frequency driver 240A may output the frame rate FR to the signal generator 260. The low frequency driver 240A may output the frame rate FR to the image converter 220.

The low frequency driver 240A includes a still image determiner 241, a segment determiner 242, a pixel flicker determiner 243, a segment flicker determiner 244, a compensation magnitude and compensation determiner 245A, a flicker value compensator 247, and a frame rate determiner 248.

In the present exemplary embodiment, the compensation size CS may be determined before determining whether to operate compensation based on the segment size.

The compensation-magnitude and compensation determiner 245A determines the compensation magnitude CS by dividing the compensation threshold TH by the segment size (step S500). The compensation magnitude and compensation determiner 245A determines whether to compensate the flicker value of the segment based on the determined compensation magnitude CS (step S600).

When the determined compensation size CS is equal to or less than 1, it may not be necessary to compensate for the flicker value of the segment. Therefore, when the determined compensation size CS is equal to or less than 1, the step S700 of compensating for the flicker value of the segment may be skipped, and the frame rate FR may be determined based on the flicker value of the uncompensated segment (step S800).

When the determined compensation size CS is greater than 1, it may be necessary to compensate for the flicker value of the segment. Accordingly, when the determined compensation size CS is greater than 1, the flicker value of the segment may be compensated (step S700), and the frame rate FR may be determined based on the flicker value of the compensated segment (step S800).

For example, when the compensation threshold TH (meaning the segment size perceived by the user as flickering) is 300 × 300, and the actual segment size is 512 × 512, the compensation size CS may be (300 × 300)/(512 × 512), such that the compensation size CS may be less than 1. Accordingly, the step S700 of compensating for the flicker value of the segment may be skipped, and the frame rate FR may be determined based on the flicker value of the uncompensated segment.

For example, when the compensation threshold TH (meaning the segment size perceived by the user as flickering) is 300 × 300, and the actual segment size is 64 × 64, the compensation size CS may be (300 × 300)/(64 × 64), such that the compensation size CS may be greater than 1. Accordingly, the flicker value of the segment may be compensated (step S700), and the frame rate FR may be determined based on the compensated flicker value of the segment.

The compensation magnitude and compensation determiner 245A may independently determine the first compensation magnitude and the second compensation magnitude. The first compensation size may mean a flicker value of a segment and the number of a plurality of flicker values of a plurality of adjacent segments for compensating the flicker value of the segment in the first direction D1 (row direction). The second compensation size may mean a flicker value of a segment and the number of a plurality of flicker values of a plurality of adjacent segments for compensating the flicker value of the segment in the second direction D2 (column direction).

The flicker value compensator 247 may compensate the flicker value of the segment based on the compensation size CS (step S700).

The frame rate determiner 248 may determine the frame rate FR based on the compensated flicker value or the uncompensated flicker value (step S800).

According to the present exemplary embodiment, the frame rate FR is determined according to the image displayed on the display panel 100, thereby making it possible to reduce the power consumption of the display apparatus. In addition, the frame rate FR is determined by using the flicker value of the segment of the image displayed on the display panel 100, so that the flicker of the image can be prevented and the display quality of the display panel 100 can be enhanced. In addition, the flicker value of the segment is compensated by using a plurality of flicker values of a plurality of adjacent segments, thereby making it possible to further enhance the display quality of the display panel 100.

Fig. 13 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the inventive concept. Fig. 14 is a circuit diagram illustrating a pixel of the display panel 100 of fig. 13. Fig. 15 is a timing chart showing input signals applied to the pixel of fig. 14.

The method of driving a display panel and the display apparatus according to the present exemplary embodiment are substantially the same as those of the previous exemplary embodiment explained with reference to fig. 1 to 10, except for some of the structures of the display panel. Therefore, the same reference numerals will be used to refer to the same or similar parts as those described in the previous exemplary embodiment of fig. 1 to 10, and any repetitive explanation regarding the above elements will be omitted.

Referring to fig. 2 to 10 and 13 to 15, the display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

The display panel 100 includes a plurality of gate lines GWPL, GWNL, GIL, and GBL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels electrically connected to the plurality of gate lines GWPL, GWNL, GIL, and GBL, the plurality of data lines DL, and the plurality of emission lines EL. The plurality of gate lines GWPL, GWNL, GIL, and GBL may extend in a first direction D1, the data line DL may extend in a second direction D2 intersecting the first direction D1, and the emission line EL may extend in a first direction D1.

The driving controller 200 receives input image data IMG and input control signals CONT from an external device (not shown).

The driving controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a fourth control signal CONT4 based on the input control signals CONT. The drive controller 200 also generates the DATA signal DATA3 based on the input image DATA IMG.

The emission driver 600 generates an emission signal to drive the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output an emission signal to the emission line EL.

The display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

The pixel receives a plurality of data write gate signals GWP and GWN, a data initialization gate signal GI, an organic light emitting element initialization signal GB, a data voltage VDATA, and an emission signal EM, and the organic light emitting element OLED of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

In the present exemplary embodiment, the pixel may include a switching element of a first type and a switching element of a second type different from the first type. The first type of switching element may be a polysilicon thin film transistor. The first type of switching element may be a Low Temperature Polysilicon (LTPS) thin film transistor. The second type of switching element may be an oxide thin film transistor. The first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

The plurality of data write gate signals GWP and GWN may include a first data write gate signal GWP and a second data write gate signal GWN. The first data write gate signal GWP may be applied to the P-type transistor such that the first data write gate signal GWP has an activation signal of a low level corresponding to a data write timing. The second data write gate signal GWN may be applied to the N-type transistor such that the second data write gate signal GWN has an activation signal of a high level corresponding to a data write timing.

At least one of the plurality of pixels may include first to seventh pixel switching elements T1 to T7, a storage capacitor CST, and an organic light emitting element OLED.

The first pixel switching element T1 includes a control electrode connected to a first node N1, an input electrode connected to a second node N2, and an output electrode connected to a third node N3.

The first pixel switching element T1 may be a polysilicon thin film transistor. The first pixel switching element T1 may be a P-type thin film transistor. The control electrode of the first pixel switching element T1 may be a gate electrode, the input electrode of the first pixel switching element T1 may be a source electrode, and the output electrode of the first pixel switching element T1 may be a drain electrode.

The second pixel switching element T2 includes a control electrode applied with the first data write gate signal GWP, an input electrode applied with the data voltage VDATA, and an output electrode connected to the second node N2.

The second pixel switching element T2 may be a polysilicon thin film transistor. The second pixel switching element T2 may be a P-type thin film transistor. The control electrode of the second pixel switching element T2 may be a gate electrode, the input electrode of the second pixel switching element T2 may be a source electrode, and the output electrode of the second pixel switching element T2 may be a drain electrode.

The third pixel switching element T3 includes a control electrode to which the second data write gate signal GWN is applied, an input electrode connected to the first node N1, and an output electrode connected to the third node N3.

The third pixel switching element T3 may be an oxide thin film transistor. The third pixel switching element T3 may be an N-type thin film transistor. The control electrode of the third pixel switching element T3 may be a gate electrode, the input electrode of the third pixel switching element T3 may be a source electrode, and the output electrode of the third pixel switching element T3 may be a drain electrode.

The fourth pixel switching element T4 includes a control electrode to which the data initialization gate signal GI is applied, an input electrode to which the initialization voltage VI is applied, and an output electrode connected to the first node N1.

The fourth pixel switching element T4 may be an oxide thin film transistor. The fourth pixel switching element T4 may be an N-type thin film transistor. The control electrode of the fourth pixel switching element T4 may be a gate electrode, the input electrode of the fourth pixel switching element T4 may be a source electrode, and the output electrode of the fourth pixel switching element T4 may be a drain electrode.

The fifth pixel switching element T5 includes a control electrode to which the emission signal EM is applied, an input electrode to which the high power voltage ELVDD is applied, and an output electrode connected to the second node N2.

The fifth pixel switching element T5 may be a polysilicon thin film transistor. The fifth pixel switching element T5 may be a P-type thin film transistor. The control electrode of the fifth pixel switching element T5 may be a gate electrode, the input electrode of the fifth pixel switching element T5 may be a source electrode, and the output electrode of the fifth pixel switching element T5 may be a drain electrode.

The sixth pixel switching element T6 includes a control electrode to which the emission signal EM is applied, an input electrode connected to the third node N3, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

The sixth pixel switching element T6 may be a polysilicon thin film transistor. The sixth pixel switching element T6 may be a P-type thin film transistor. The control electrode of the sixth pixel switching element T6 may be a gate electrode, the input electrode of the sixth pixel switching element T6 may be a source electrode, and the output electrode of the sixth pixel switching element T6 may be a drain electrode.

The seventh pixel switching element T7 includes a control electrode to which the organic light emitting element initialization signal GB is applied, an input electrode to which the initialization voltage VI is applied, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

The seventh pixel switching element T7 may be an oxide thin film transistor. The seventh pixel switching element T7 may be an N-type thin film transistor. The control electrode of the seventh pixel switching element T7 may be a gate electrode, the input electrode of the seventh pixel switching element T7 may be a source electrode, and the output electrode of the seventh pixel switching element T7 may be a drain electrode.

The storage capacitor CST includes a first electrode to which the high power voltage ELVDD is applied and a second electrode connected to the first node N1.

The organic light emitting element OLED includes an anode electrode connected to the output electrode of the sixth pixel switching element T6 and a cathode electrode applied with the low power voltage ELVSS.

As shown in fig. 15, the first node N1 and the storage capacitor CST are initialized in response to the data initialization gate signal GI during the first duration DU 1. During the second duration DU2, the threshold voltage of the first pixel switching element T1 is compensated in response to the first and second data write gate signals GWP and GWN, and the data voltage VDATA is written to the first node N1 while the data voltage VDATA of the threshold voltage is compensated. In addition, during the second duration DU2, the anode electrode of the organic light emitting element OLED is initialized in response to the organic light emitting element initialization signal GB. During the third duration DU3, the organic light emitting element OLED emits light in response to the emission signal EM to cause the display panel 100 to display an image.

In the present exemplary embodiment, some of the plurality of pixel switching elements may be designed by using oxide thin film transistors. In the present exemplary embodiment, the third pixel switching element T3, the fourth pixel switching element T4, and the seventh pixel switching element T7 may be oxide thin film transistors. The first pixel switching element T1, the second pixel switching element T2, the fifth pixel switching element T5, and the sixth pixel switching element T6 may be polysilicon thin film transistors.

The display panel 100 may be driven in a normal driving mode in which the display panel 100 is driven at a normal driving frequency and in a low frequency driving mode in which the display panel 100 is driven at a low frequency. The low frequency may be lower than the normal driving frequency.

For example, when the input image data represents a video image, the display panel 100 may be driven in the normal driving mode. When the input image data represents a still image, the display panel may be driven in a low frequency driving mode. When the display device is operated in the normally-on mode, the display panel may be driven in a low frequency driving mode.

The display panel 100 may be driven in units of frames. In the normal driving mode, the display panel 100 may be refreshed in every frame. Therefore, the normal driving mode includes only a write frame for writing data in the pixel.

In the low frequency driving mode, the display panel 100 may be refreshed at a low frequency. Therefore, the low frequency driving mode includes a writing frame in which data is written in the pixels and a holding frame in which the written data is maintained without writing the data in the pixels.

For example, when the frequency of the normal driving mode is 60Hz and the frequency of the low frequency driving mode is 1Hz, the low frequency driving mode includes one write frame and fifty-nine hold frames per second. For example, when the frequency of the normal drive mode is 60Hz and the frequency of the low-frequency drive mode is 1Hz, fifty-nine consecutive hold frames are arranged between two adjacent write frames.

For example, when the frequency of the normal driving mode is 60Hz and the frequency of the low frequency driving mode is 10Hz, the low frequency driving mode includes ten write frames and fifty hold frames per second. When the frequency of the normal drive mode is 60Hz and the frequency of the low frequency drive mode is 10Hz, five consecutive hold frames are arranged between two adjacent write frames.

In the present exemplary embodiment, the second data write gate signal GWN and the data initialization gate signal GI may have the first frequency in the low frequency driving mode. The first frequency may be a frequency of the low frequency drive mode. In contrast, the first data writing gate signal GWP, the emission signal EM, and the organic light emitting element initialization signal GB may have a second frequency greater than the first frequency. The second frequency may be a normal frequency of the normal driving mode.

The low frequency driver 240 in fig. 3 may be applied to the structure of the display panel 100 of the present exemplary embodiment. In addition, the low frequency driver 240A in fig. 11 may be applied to the structure of the display panel 100 of the present exemplary embodiment.

According to the present exemplary embodiment, the frame rate FR is determined according to the image displayed on the display panel 100, thereby making it possible to reduce the power consumption of the display apparatus. In addition, the frame rate FR is determined by using the flicker value of the segment of the image displayed on the display panel 100, thereby making it possible to prevent flicker of the image and improve the display quality of the display panel 100. In addition, the flicker value of the segment is compensated by using a plurality of flicker values of a plurality of adjacent segments, thereby making it possible to further improve the display quality of the display panel 100.

According to the present exemplary embodiment, power consumption of the display device may be reduced, and display quality of the display panel may be enhanced.

The foregoing is illustrative of the concepts of the invention and is not to be construed as limiting thereof. Although a few exemplary embodiments of this inventive concept have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. In the claims means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures. Therefore, the foregoing is illustrative of the inventive concept and is not to be construed as limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims. The inventive concept is defined by the following claims, with equivalents of the claims to be included therein.

Claims

1. A method of driving a display panel, the method comprising:

dividing an input image into a plurality of segments;

generating a flicker value for a segment of the plurality of segments;

compensating for the flicker value of the segment based on a segment size, the flicker value of the segment, and a plurality of flicker values of a plurality of adjacent segments located around the segment;

determining a frame rate of the display panel based on the flicker values of the segments; and

outputting a data voltage to the display panel at the frame rate.

2. The method of claim 1, wherein compensating the flicker values of the segment comprises:

determining not to compensate for the flicker value of the segment when the segment size is equal to or greater than a compensation threshold; and

determining to compensate for the flicker value of the segment when the segment size is less than the compensation threshold.

3. The method of claim 2, further comprising:

the size of the compensation is determined,

wherein the compensation magnitude represents a flicker value of a compensation target segment and a number of a plurality of flicker values of a plurality of segments adjacent to the compensation target segment; and is

Wherein the compensation size is used for compensation of the compensation target segment when the segment size is smaller than the compensation threshold.

4. The method of claim 3, wherein the compensation size is determined such that a product of the segment size and the compensation size is equal to or greater than the compensation threshold.

5. The method of claim 4, wherein the compensation size is determined as a smallest integer that satisfies the product of the segment size and the compensation size being equal to or greater than the compensation threshold.

6. The method of claim 3, wherein determining the compensation size comprises:

determining a first compensation magnitude representing the flicker value of the compensation target section and the number of the plurality of flicker values of the plurality of sections adjacent to the compensation target section in a first direction; and

determining a second compensation magnitude representing the flicker value of the compensation target section and the number of the plurality of flicker values of the plurality of sections adjacent to the compensation target section in a second direction different from the first direction,

wherein the first compensation magnitude and the second compensation magnitude are each used for compensation of the compensation target section.

7. The method of claim 1, further comprising:

the size of the compensation is determined,

wherein the compensation size is determined by dividing a compensation threshold by the segment size,

wherein compensating the flicker value of the segment comprises:

determining not to compensate for the flicker value of the segment when the segment size is equal to or less than 1; and

compensating for the flicker value of the segment when the segment size is greater than 1.

8. The method of claim 7, wherein determining the compensation size comprises:

determining a first compensation magnitude representing a flicker value of a compensation target section and a number of the plurality of flicker values of the plurality of sections adjacent to the compensation target section in a first direction; and

wherein the first compensation magnitude and the second compensation magnitude are used for compensation of the compensation target section.

9. The method of claim 1, further comprising:

determining whether the input image represents a still image or a video image,

wherein the frame rate of the display panel is determined based on the flicker value of the segment when the input image represents the static image.

10. The method of claim 1, wherein generating the flicker value for the segment comprises:

converting the luminance of a plurality of pixels into a plurality of flicker values for the plurality of pixels; and

operating on the plurality of flicker values for the plurality of pixels in the segment.

11. The method of claim 10, wherein operating on the plurality of flicker values for the plurality of pixels in the segment comprises:

summing the plurality of flicker values for the plurality of pixels in the segment.

12. The method of claim 10, wherein operating on the plurality of flicker values for the plurality of pixels in the segment comprises:

setting a plurality of weights for the plurality of pixels according to a plurality of positions of the plurality of pixels; and

operating a weighted summation of the plurality of flicker values for the plurality of pixels by using the plurality of weights for the plurality of pixels.

13. The method of claim 1, wherein determining the frame rate of the display panel comprises:

a maximum value of a plurality of flicker values of the plurality of segments is compared to a threshold value.

14. The method of claim 1, wherein determining the frame rate of the display panel comprises:

comparing an average of a plurality of flicker values of the plurality of segments to a threshold, the average being greater than a predetermined flicker value.

15. A display device, comprising:

a display panel configured to display an image;

a low frequency driver connected to the display panel and configured to divide an input image into a plurality of segments, generate flicker values of segments of the plurality of segments, compensate for the flicker values of the segments as a function of segment size, and determine a frame rate of the display panel based on the flicker values of the segments; and

a data driver connected to the display panel and configured to output a data voltage to the display panel at the frame rate.

16. The display device of claim 15, wherein the low frequency driver is configured to determine not to compensate for the flicker value of the segment when the segment size is equal to or greater than a compensation threshold; and

wherein the low frequency driver is configured to determine to compensate for the flicker value of the segment when the segment size is less than the compensation threshold.

17. The display device of claim 16, wherein the low frequency driver is configured to determine a compensation magnitude representing a flicker value of a compensation target segment and a number of a plurality of flicker values of a plurality of segments adjacent to the compensation target segment, the compensation magnitude being used for compensation of the compensation target segment when the segment size is less than the compensation threshold.

18. The display device of claim 17, wherein the compensation size is determined such that a product of the segment size and the compensation size is equal to or greater than the compensation threshold.

19. The display device of claim 15, wherein the low frequency driver is configured to determine a compensation magnitude;

wherein the compensation magnitude is determined based on a flicker value of a compensation target section and a number of a plurality of flicker values of a plurality of sections adjacent to the compensation target section, the compensation magnitude being used for compensation of the compensation target section;

wherein the compensation size is determined by dividing a compensation threshold by the segment size;

wherein the low frequency driver is configured to determine not to compensate for the flicker value of the segment when the segment size is equal to or less than 1; and is

Wherein the low frequency driver is configured to determine to compensate for the flicker value of the segment when the segment size is greater than 1.

20. The display device of claim 15, wherein the low frequency driver comprises:

a still image determiner configured to determine whether the input image represents a still image or a video image; and is

Wherein the low frequency driver is configured to determine the frame rate of the display panel based on the flicker value of the segment when the input image represents the static image.