KR102104360B1 - Liquid crystal display device, appatus and method for driving the same - Google Patents

Abstract

The present invention discloses a liquid crystal display device. More specifically, the present invention is a liquid crystal display device that improves the flicker phenomenon occurring in a liquid crystal display device that realizes low-frequency driving by using an oxide (oxide) thin film transistor having excellent cut-off characteristics. It relates to a driving device and method.
According to an embodiment of the present invention, by applying a compensation value to the PWM signal applied to the backlight unit in response to the refresh period, the luminance of the backlight is adjusted according to the shape of the image, thereby improving flicker defects and realizing high-quality images. It has the effect.

Description

Liquid crystal display device, driving device and method thereof {LIQUID CRYSTAL DISPLAY DEVICE, APPATUS AND METHOD FOR DRIVING THE SAME}

The present invention relates to a liquid crystal display device, and in particular, a liquid crystal having improved flicker phenomenon occurring in a liquid crystal display device that realizes low-frequency driving by using an oxide thin film transistor having excellent cut-off characteristics. It relates to a display device, a driving device and a method thereof.

In order to meet these requirements, a thin film transistor (TFT) to be applied as a display device switching and driving device having excellent performance without increasing costs is required along with the enlargement of a substrate such as glass.

A typical amorphous silicon thin film transistor (a-Si TFT) as a driving and switching device for a display device is a device that can be uniformly formed on a large substrate over 2 m at a low cost and is a device widely used at present.

However, in accordance with the trend of large-scale and high-definition display devices, high performance of devices is also required, so it is judged that the existing a-Si TFT with a mobility of 0.5 cm2 / Vs will reach the limit.

Therefore, there is a need for a high-performance TFT and manufacturing technology with higher mobility than a-Si TFT. In addition, as the a-Si TFT continues to operate as the greatest weakness, the device characteristics continue to deteriorate and pose a reliability problem that cannot maintain initial performance.

Currently, research to overcome the limitations of the a-Si TFT is ongoing, and among them, an oxide semiconductor TFT.

These oxide TFTs have higher mobility than amorphous silicon (a-Si) TFTs, and are more advantageous for realizing a driving circuit for controlling a switching element as well as a switching element in a liquid crystal panel provided in a liquid crystal display device. The driving frequency of the liquid crystal display device is variable to 60 Hz or less, thereby reducing the current consumption.

1 is a graph showing a pixel charging characteristic of a conventional liquid crystal display device. Referring to FIG. 1, when a gate high signal VGH is applied for one horizontal period (1H) for each gate wiring within one frame, TFT Is turned on and the data signal Vdata is applied in synchronization with it. At this time, the pixel voltage Vp charged in the actual pixel is gradually charged according to the RC delay of the data line, and the TFT turns when the potential of the gate high signal VGH transitions to the gate low signal VGL at the time of the buffering. It is off (Toff). The turn-off period of the TFT is maintained until the next frame. The figure shows an example in which the data signal Vdata alternates with a positive polarity and a negative polarity for each frame by driving inversion.

On the other hand, the potential of the pixel voltage Vp is lowered to a certain amount by the leakage current generated in each TFT on the turn-off substrate of the TFT for the buffered pixel (ΔVp). The amount of leakage current is attributable to the cut-off characteristic of the TFT, and the oxide TFT has a characteristic that the amount of leakage current is small as it is superior to an amorphous silicon TFT or a polysilicon TFT. Therefore, during the turn-off period of the TFT, the amount of change in the pixel voltage (ΔVp) is minimized, and even if the period is extended, little variation in the image occurs, so that low-frequency driving is possible.

Accordingly, a liquid crystal display device using an oxide TFT may be provided with a driving frequency setting unit, and a low frequency driving liquid crystal display device may be implemented by skipping a frame.

2 is a diagram schematically showing a structure of a conventional driving frequency variable type liquid crystal display device.

Referring to FIG. 2, in the conventional driving frequency tunable liquid crystal display, a liquid crystal panel 1 in which a pixel is formed using an oxide TFT, and timing to generate control signals of a driving unit by receiving image data and timing signals from the outside The control unit 2 and the driving unit 3 for driving the liquid crystal panel 1 according to the control signal applied from the timing control unit 2 and the driving frequency setting for adjusting the driving frequency of the liquid crystal panel 1 according to the set frequency Part 5 is included.

Particularly, in a conventional liquid crystal display device, the driving frequency is set to 60 Hz or higher by default, and displays an image in correspondence with image data of 60 frames input from the outside. When driving it at a low frequency of 60 Hz or less, instead of driving the input 60 frames of image data as it is, a predetermined frame is skipped according to the setting value of the driving frequency setting unit 5 to the pixel during the previous frame charging period. A predetermined image is displayed through the charged pixel voltage.

However, even if a predetermined frame is skipped, the pixel voltage of each pixel must be periodically refreshed according to an image, and flicker due to bending of light occurs in the refresh period.

3 is a graph showing a luminance relationship of an image according to a signal waveform of a conventional low-frequency driving liquid crystal display device.

Referring to FIG. 3, in the conventional low-frequency driving liquid crystal display, the gate driving voltage Vg is applied in the refresh period according to the gate clock signal gclk, and the TFT is turned on. In addition, it can be seen that, in synchronization with this, when the data voltage Vdata of positive or negative polarity is applied, the luminance of the image is instantaneously decreased in the section. This decrease in brightness causes the viewer to perceive the flicker.

This is due to the asymmetry between the polarities between the pixel voltages pre-charged in the previous section and the large variation in the angle of the liquid crystal due to polarity reversal when the data voltage is charged to the pixel in the refresh section. It causes the image quality to deteriorate.

The present invention has been devised to solve the above-mentioned problems, and relates to a liquid crystal display device having improved flicker defects in a liquid crystal display device using an oxide TFT, and a driving device and method thereof.

In order to achieve the above object, a liquid crystal display device according to a preferred embodiment of the present invention, a plurality of pixels is formed a liquid crystal panel; A plurality of driving units for controlling the liquid crystal panel; A backlight unit providing light to the liquid crystal panel in response to a PWM signal; A timing control unit receiving image data and timing signals and generating control signals of the plurality of driving units and backlight control signals; A driving frequency setting unit skipping a predetermined frame of the image data when driving at a low frequency in conjunction with the timing control unit according to a set driving frequency; And a luminance compensator for compensating the luminance of the backlight unit by applying different compensation values to the PWM signal in the refresh section of the image data corresponding to the backlight control signal.

In addition, a driving circuit of a liquid crystal display device according to an embodiment of the present invention is a driving circuit of a liquid crystal display device including a backlight unit, a control signal determination block for receiving the backlight control signal and determining a frame skip mode; A DBV adjustment block for reducing the duty ratio of the PWM signal by a set value when the PWM signal is set to a DC waveform with reference to the image brightness value included in the backlight control signal; A duty cycle setting block for determining a compensation value for the PWM signal in a refresh period with reference to a set value; A range setting block for determining a range of the refresh section; And a PWM generation block that generates a PWM signal according to the setting result and outputs it to the backlight unit.

In addition, a method of driving a liquid crystal display device including a backlight unit according to an embodiment of the present invention includes: receiving the backlight control signal and determining a frame skip mode; Lowering the duty ratio of the PWM signal by a set value when the PWM signal is set to a DC waveform with reference to the image brightness value included in the backlight control signal; Determining a compensation value for the PWM signal in a refresh period with reference to a set value; Determining a range of the refresh period; And generating a PWM signal according to the setting result and outputting it to the backlight unit.

In the liquid crystal display device according to an embodiment of the present invention, a flicker defect is improved by adjusting a luminance of a backlight according to a shape of an image by applying a compensation value to a PWM signal applied to a backlight unit in response to a refresh period, thereby improving flicker defects and of high quality. It has the effect of realizing an image.

1 is a graph showing a pixel charging characteristic of a conventional liquid crystal display device.
2 is a diagram schematically showing a structure of a conventional driving frequency variable type liquid crystal display device.
3 is a graph showing a luminance relationship of an image according to a signal waveform of a conventional low-frequency driving liquid crystal display device.
4 is a view showing the structure of a liquid crystal display device according to an embodiment of the present invention.
5A is a block diagram showing a timing control unit of a liquid crystal display device according to an exemplary embodiment of the present invention.
5B is a waveform diagram showing an example of a signal waveform for a PWM signal generated by the backlight control signal bbcs of FIG. 5A.
6 is a view showing an equivalent circuit diagram of a logic operation circuit included in a backlight control signal generation block according to an embodiment of the present invention.
7 is a block diagram showing the structure of a luminance compensation unit according to an embodiment of the present invention.
8 is a flowchart illustrating a driving method using a driving circuit of the liquid crystal display shown in FIG. 7.
9 is a view showing a signal output form by a method of driving a liquid crystal display device according to an embodiment of the present invention.

Hereinafter, a liquid crystal display device, a driving device and a driving method thereof according to a preferred embodiment of the present invention will be described with reference to the drawings.

4 is a view showing the structure of a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 4, the liquid crystal display device of the present invention receives a liquid crystal panel 100 having a plurality of pixels, image data and timing signals, and receives control signals of the plurality of driving units 120 and 130 and a backlight control signal. The generated timing control unit 110, a plurality of driving units 120 and 130 for controlling the liquid crystal panel 100, and a backlight unit 140 providing light to the liquid crystal panel 100 in response to a PWM signal, are set Depending on the driving frequency, the driving frequency setting unit 150 skips a predetermined frame of image data when driving at a low frequency in conjunction with the timing control unit 110, and PWM in a refresh section and a hold section of the image data in response to a backlight control signal. And a luminance compensator 160 that controls the signal to adjust the luminance of the backlight 140 differently.

The liquid crystal panel 100 includes two transparent substrates spaced apart at a predetermined distance and a liquid crystal layer interposed therebetween. Among the two substrates described above, a plurality of gate lines GL and a plurality of data lines DL are arranged in a matrix on the lower substrate, and a plurality of pixels PX are defined at the intersection. A thin film transistor T and a liquid crystal capacitor LC as switching elements are formed in each pixel PX. Although not illustrated, the liquid crystal capacitor LC may be further connected to a storage capacitor (not shown) to stably maintain the potential of the pixel voltage charged in the pixel PX.

In particular, the thin film transistor T of the liquid crystal panel 100 according to an embodiment of the present invention is made of an oxide semiconductor whose active layer is not amorphous silicon. Here, the active layer is one or more materials selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al) and zinc (Zn) ), A material in which silicon (Si) is added to a metal material may be used. For example, silicon indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to indium zinc composite oxide (InZnO) and amorphous indium gallium zinc oxide (a-IGZO) may be used. Particularly, in the case of the thin film transistor T formed by using the a-IGZO as the active layer, it has a high mobility characteristic, is easy to control the doping concentration, and has the advantage of being able to deposit in a large area even at a low temperature.

On the other hand, a color filter for displaying three primary colors of red, green, blue, and a black matrix for partitioning each pixel region are formed on the upper substrate.

The timing controller 110 receives digital-type image data RGB and control-related timing signals CLK, Hsync, and Vsync from an external system (not shown) that provides a video source, and sorts and aligns them. Converted to generate the control signals (GCS, DCS) is input to each of the driving unit (120 130).

In particular, the timing control unit 110 of the present invention converts the control signals of the gate and data driving units 120 and 130 according to the frequency set in response to the frequency control signal (FCS) input from the driving frequency setting unit, and the backlight according to the set value Generate a control signal. To this end, the timing control unit 110 further includes a backlight control signal generation block (not shown), and receives backlight backlight dimming, brightness control block on and off, and backlight on and off as its parameter values. Will generate Detailed description of the backlight control block will be described later.

In addition, the above-described timing control unit 110 is connected to an external system (not shown) by a predetermined interface (interface) method to receive the above-described signals, such as LVDS (Low Voltage Differential Signal) interface and TTL interface Etc. can be applied.

The driving unit controlled by the control signal of the timing control unit 110 to control the liquid crystal panel 100 includes a gate driving unit 120 driving the thin film transistor T and a data driving unit 130 supplying a data signal Vdata. There is.

The gate driver 120 turns-on / off the thin film transistors T arranged on the liquid crystal panel 100 in response to the gate control signal GCS input from the timing controller 110. To control.

The gate driver 120 is composed of a shift register constituting a plurality of channels, and generates a gate driving signal Vg to input a gate high signal VGH to one gate wiring GL during one horizontal period 1H. By doing so, the thin film transistor T of the liquid crystal panel 110 is turned on. At the same time, the data signal Vdata is input from the data line DL and charged with the pixel voltage to the liquid crystal capacitor LC connected through each thin film transistor T. At this time, the gate low signal VGL is input to the other gate line GL, and the thin film transistor T connected to the other gate line GL maintains a turn-off state. The section in which the pixel voltage is charged is defined as an image data update time, and is defined as a holding period in which the currently charged pixel voltage is maintained between immediately before the next update starts.

In particular, the potential of the pixel voltage must be kept constant during the holding period, and in the case of low frequency driving, the holding period is extended. That is, in the case of a liquid crystal display device in which the driving frequency is set to 60 Hz for 60 seconds, the update is repeated for 1 second for all gate lines GL, but the driving frequency is set to a very low low frequency of 1 Hz. After updating the pixel voltage of one frame, the holding section of 59 frames is set.

Meanwhile, the gate control signal GCS input to the gate driver 120 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE). Etc., and the gate driving unit 120 sequentially inputs the gate driving signal Vg to the plurality of gate lines GL by shifting the input gate start pulse GSP in synchronization with the gate shift clock GSC. . Here, the pulse width of the gate driving signal Vg is controlled according to the gate output enable GOE.

The data driver 130 converts the digital image signal aRGB arranged by the timing controller 110 into an analog form according to the reference voltage in response to the data control signal DCS input from the timing controller 110. Then, each pixel PX of the liquid crystal panel 100 is supplied.

The above-described data control signal (DCS) includes a source start pulse (SSP), a source shift clock (SSC), and a source output enable (SOE) signal. The image signal aRGB input from 110 is converted into an analog waveform data signal Vdata and input to the liquid crystal panel 100. Specifically, the data driving circuit 130 samples and latches the image signal aRGB input from the timing controller 110 in correspondence with the source start pulse SSP and the source shift clock SSC, and then the source In response to the output enable SOE, a data signal Vdata for one horizontal line is supplied to the data line DL for each horizontal period 1H to which the gate driving signal VG is supplied.

The backlight unit 140 is disposed on the rear surface of the liquid crystal panel 100 and serves to provide light for image display. The backlight unit 140 is composed of a light source and a driving circuit for driving the same, and emits light in response to a backlight control signal generated from the timing control unit 110, but luminance compensation is performed by the luminance compensation unit 160 of the present invention. It is driven by the applied PWM (Pulse Width Modulation) signal.

The backlight unit 140 is driven by a PWM method that determines the lighting and flashing period of a light source according to a duty ratio. When the backlight dimming method is applied, the backlight unit 140 is grouped into a predetermined number and the liquid crystal panel 100 The surface light source irradiated to the light source may be divided into logical blocks. The direct dimming type is advantageous for the backlight dimming method, but an edge type may also be applied. In particular, a light emitting diode (LED) that is a point light source advantageous for blocking may be used as a light source of the backlight unit 140.

In order to increase the efficiency of light emitted from the backlight unit 140, an optical member (not shown) may be provided between the backlight unit 140 and the liquid crystal panel 100. A light guide plate and a prism sheet for guiding the emitted light, and a reflector may be included.

The driving frequency setting unit 150 supplies a control signal FCS for changing the driving frequency to the timing control unit 110 according to a preset driving frequency setting value. Particularly, when the driving frequency setting unit 150 is set to a low driving frequency of 60 Hz or less, the driving frequency setting unit 150 skips some of the frames of the image data RGB input to the timing control unit 110 Do it.

That is, in the case of a liquid crystal display device having a driving frequency set to 60 Hz or less, the update process is repeated less than 60 frames for 1 second, and when the driving frequency is set to a very low frequency of 1 Hz, the update frame of 1 frame and neighbors After the refresh period of 2-3 frames including one or two frames, the remaining period is set as a holding period. Therefore, the image data for the remaining 59 frames is skipped by the driving frequency setting unit 150.

The function of the driving frequency setting unit 150 may be blocked and integrated into the timing control unit 110 as an integrated IC.

The luminance compensator 160 generates a PWM signal for determining a backlight luminance value in response to the backlight control signal bbcs input from the timing controller 110 and applies it to the backlight 140. The backlight control signal (bcs) includes whether or not the current liquid crystal display device has frame skip due to low frequency driving, and a display brightness value (DBV) according to the currently displayed image type, and a luminance compensator 160 ) Considers this and determines the duty ratio of the PWM signal in the refresh period and the holding period.

In particular, the luminance compensator 160 determines the degree of control of the duty ratio of the PWM signal and the start and end timings of the PWM signal in the refresh section according to a preset set value. In particular, the liquid crystal panel is within the refresh section. When the displayed image has a high ratio to the white area, the luminance is not increased, but the luminance is lowered to minimize the degradation of the image quality due to excessively high luminance. In addition, in the case of an image of general luminance, when driving at low frequency, the luminance of the backlight is increased by a predetermined level compared to the holding period in the refresh period, thereby eliminating flicker defects due to the decrease in luminance. A more detailed description of the luminance compensation unit 160 will be described later.

According to the above-described structure, the liquid crystal display device of the present invention can improve a flicker defect generated in a refresh section when driving at a low frequency, thereby realizing a high quality image.

Hereinafter, the structure of the timing control unit provided in the liquid crystal display device of the present invention will be described in detail with reference to the drawings.

5A is a block diagram showing a timing control unit of a liquid crystal display device according to an exemplary embodiment of the present invention.

Referring to FIG. 5A, the timing control unit 110 of the present invention may process a control signal processing block 112 that generates control signals of a gate and a data driver in response to the timing signal, and the gate and data driver. An image signal processing block 114 that converts and outputs (aRGB) the image data (RGB) in a form, and a CABC block 115 that generates luminance data (Bdata) for the brightness of the backlight unit corresponding to the image data (RGB) ) And a backlight control signal generation block 117 generating the backlight control signal bbcs in response to the luminance data Bdata.

The control signal processing unit 112 controls the driving of the gate driving circuit and the data driving unit in response to timing signals such as vertical and horizontal synchronization signals (Vsync, Hsync) and clock signal (DCLK) input from an external system (not shown). For generating and outputting gate and data control signals (GCS, DCS).

The image data processing unit 114 receives the image data RGB and outputs the aligned image data aRGB by arranging it in a form that the data driver can process. In particular, the image data processing unit 114 refers to the luminance data (bdata) of the image data RGB from the CABC block 115, which will be described later, and the gamma control for adjusting the gamma voltage as a reference for conversion to an analog waveform by the data driver. Block 1141 may be further included.

CABC (Content Adaptive Brightness Control) block 115 is a circuit block that serves to adjust the brightness of the screen, and determines the overall luminance of the image displayed through the image data (RGB), thereby adjusting the gradation of the image or It is provided to reduce power consumption by adjusting the duty ratio of the PWM signal. Here, rather than adjusting the gradation of the image, the power consumed by the light source is higher, so the method of adjusting the PWM signal is preferred.

The CABC block 115 is a method of directly analyzing the luminance of an image according to image data (RGB), and another method of performing a similar function is a LABC (Light Sensor Automatic Brightness Control) method. LABC may replace the CABC block 115 as a method of detecting the brightness of the screen by adding a sensor.

The backlight control signal generation block 117 is a block that generates a backlight control signal bbcs that controls driving of the backlight unit with reference to luminance data Bdata. The backlight control signal (bcs) serves as a reference for determining the duty ratio of the PWM signal for driving the light source of the backlight unit, and the backlight dimming control is also performed by this signal (bcs). Accordingly, the luminance data Bdata includes a display brightness value (DBV) for the image, and the backlight control signal generation block 117 may include a DBV processing block 1171 for processing the image. .

In particular, the backlight control signal generation block 117 generates the backlight control signal bbcs within a range of a luminance set value Bset for a preset backlight luminance. The luminance set value (Bset) defines the luminance control range (0 to 255) of the backlight.

5B is a waveform diagram showing an example of a signal waveform for a PWM signal generated by the backlight control signal bbcs of FIG. 5A. Referring to FIG. 5B, when the backlight luminance control range is defined from 0d to 255d, when the backlight unit is turned off (0d), when turned on (255d), and the luminance is adjusted to 33%. An example of the case 88d can be confirmed, which is determined by the duty ratio.

In particular, when the image is a very bright image (255d), that is, when the on-state of the backlight is continued when the image brightness is maximum, the DC signal is maintained for a certain period of time, and the luminance is further increased in the refresh period. It becomes impossible. To overcome this limitation, the backlight control signal generation block of the present invention includes a circuit that reflects the DBV to the backlight control signal (bcs) according to the PWM signal waveform.

6 is a view showing an equivalent circuit diagram of a logic operation circuit included in a backlight control signal generation block according to an embodiment of the present invention.

Referring to FIG. 6, the backlight control signal generation block 117 of the present invention may further include a DBV processing block 1171 for reflecting an image brightness value (DBV) to the backlight control signal (bcs), and a plurality of controls The maximum luminance value determined according to the signals con1, con2, and con3 can be expressed as a circuit equivalent to a plurality of muxes (MUX1, MUX2, MUX3) reflected in the backlight control signal (bcs) as the image brightness value (DBV). have.

First, the first mux MUX1 outputs a preset maximum luminance value Max.bc when the backlight dimming is performed by the first control signal con1 that defines whether or not the backlight dimming is performed. Ground (GND), that is, 0 is output. Here, when the backlight dimming is not executed, a PWM signal with a fixed duty ratio is output, so that a luminance data value by CABC calculation is not required.

Next, the second MUX2 outputs the output value of the first MUX as it is when the second control signal con2, which defines the on / off state of the backlight control signal generation block, is on and off. In this case, ground (GND), that is, an O value is output.

Subsequently, when the third control signal con3 defining the on / off state of the backlight unit is turned on, the third mux MUX3 outputs the output value of the second mux MUX as it is, and when off, the ground GND ) That is, O value is output.

According to this structure, the DVB processing block 1171 sets the maximum luminance value of the preset backlight unit to the image brightness value (DBV) and provides it to the backlight control signal generation block, which is generated by the backlight control signal (bcs). ) To output to the luminance compensation unit.

Hereinafter, a luminance compensation unit of the low-frequency driving liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to the drawings.

7 is a block diagram showing the structure of a luminance compensation unit according to an embodiment of the present invention.

Referring to FIG. 7, the luminance compensator 160 of the present invention includes a control signal determination block 161 for receiving a backlight control signal bbcs and determining a frame skip mode, and a backlight control signal bbcs When the PWM signal is set as a DC waveform with reference to the image brightness value (DBV), the DBV adjustment block 162 lowers the duty ratio of the PWM signal by a set range and the PWM signal in the refresh section with reference to the set value. Duty cycle setting block 163 for adding the compensation value, range setting block 164 for setting the start and end time of the refresh section with reference to the set value, and PWM generation block 165 for generating a PWM signal by setting ).

The control signal determination block 161 receives the backlight control signal bbcs and determines whether or not the frame is skipped according to the low frequency driving included therein. When frame skipping occurs, the DBV adjustment block 162 is requested to adjust the image brightness value (DBV). Otherwise, the PWM generation block 165 generates a PWM signal according to the basic setting.

The DBV adjustment block 162 is a block that adjusts an image brightness value (DBV) according to a backlight driving type when frame skipping occurs. The backlight driving type corresponds to the PWM signal, and if the PWM signal is a DC waveform, it is a case where the maximum luminance value continues for a certain period and the received image brightness value (DBV) can be set to OxFF. At this time, there is no problem that the luminance falls in the refresh period, but the luminance can no longer be increased in the holding period, so it is impossible to compensate for the luminance by adjusting the duty ratio of the PWM signal. To overcome this limitation, according to an embodiment of the present invention, when the image brightness value (DBV) is the maximum luminance in the low frequency driving, the maximum luminance is reduced to 5% to 10% or less. In other words, when the brightness of the image (DBV) is OxFF and the brightness is 100%, lower it by 5% to adjust the image brightness (DBV) not to exceed 95%, 100% in the refresh section, and 95 in the hold section. By operating at the luminance of%, it is driven so that the luminance is relatively low in the refresh period.

The duty cycle setting block 163 serves to increase the duty ratio of the PWM signal in the refresh period according to the set value. The maximum luminance is determined by the DBV adjustment block 162, and a luminance reduction is compensated by adding a compensation value to the image brightness value DBV according to a ratio set in a refresh period in which luminance degradation occurs.

The range setting block 164 serves to determine the range of the refresh section according to the set value. Since the response speed of the liquid crystal panel is typically slower than the response speed of the LED, when the PWM signal compensated for luminance is applied immediately after the start of the refresh period, there may be a problem that the luminance increases instantaneously. In order to minimize this problem, the start time of the PWM signal is set to a time delayed by a predetermined time from the start time of the refresh section.

In particular, the range setting block 164 may determine a start point of a refresh period and a PWM start and end point of the timing signal of the liquid crystal display device in synchronization with the vertical sync signal Vsync.

The PWM generation block 165 serves to generate a PWM signal (PWM) having a duty ratio set by the blocks and supply it to the backlight unit.

Hereinafter, a driving method of a liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to the drawings.

8 is a flowchart illustrating a driving method using a driving circuit of the liquid crystal display shown in FIG. 7.

Referring to FIG. 8, a method of driving a liquid crystal display of the present invention includes receiving a backlight control signal and determining a frame skip mode (S110, S120), and when the frame skip mode is on, the backlight control signal When the PWM signal is set to a DC waveform with reference to the image brightness value included in the step, lowering the duty ratio of the PWM signal by a set range (S131, S132), and compensating for the PWM signal in the refresh section with reference to the set value Adding a value (S141, S142), setting a range of the refresh interval with reference to the set value (S151, S152), and generating a set PWM signal and supplying it to the backlight unit (S160) Includes.

First, the driving circuit of the liquid crystal display device receives the backlight control signal (bcs) including the image brightness value (DVB) (S110), and determines whether the frame skip mode is applied by the low-frequency driving unit (S120). Accordingly, when the frame skip mode is not applied, a PWM signal is generated according to the default setting value and output to the backlight unit (S160).

In addition, when the frame skip mode is applied, the PWM waveform is analyzed to adjust the image brightness value (DVB) within a range of 5% to 10% in the case of a DC waveform (S132). Subsequently, a reference value for a preset PWM duty cycle is referenced (S141), and a compensation value is added to the reference value set to the image brightness value (DVB) to increase the brightness of the backlight in the refresh period (S142). At this time, the adjusted image brightness value DVB may be the value adjusted in step S132.

Next, the range of the refresh period S151 is adjusted with reference to a preset value (S151) (S152). This may be set on a frame-by-frame basis, and a refresh period may be determined by including a predetermined frame as well as a frame where image data update starts to occur. In particular, since the image data update time corresponds to a time when the gate driving signal of the liquid crystal display device is output, the corresponding section can be set in synchronization with the vertical synchronization signal Vsync.

According to the above steps, the PWM signal according to the set duty ratio is generated and output to the backlight unit (S160).

Hereinafter, a signal output form according to a driving method of a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.

9 is a view showing a signal output form by a method of driving a liquid crystal display device according to an embodiment of the present invention.

As illustrated in FIG. 9, frames in which data update has occurred have R, and frames with no other have an identification code of N, and images from 1 frame to 10 frames are output by driving the liquid crystal display, and the image luminance value (DVB If) is 60%, the luminance compensator compensates luminance by adding compensation values (a, b, c) set for the image luminance value (DVB) from 3 frames in which image data is updated. In the drawing, an example is shown in which three frames are set as a refresh section and different luminance compensation values are added thereto.

In particular, the refresh section includes a predetermined number of 4 frames and 5 frames including 3 frames in which image data update is started. Accordingly, the luminance compensator is turned on for 1,2,3 times each in 3 to 5 frames, and the compensation value for the image brightness value (DBV) is applied by being delayed to a predetermined time in consideration of the response speed of the liquid crystal.

Accordingly, the image (out) output through the liquid crystal panel is output with the luminance at which the compensation values of a, b, and c are added in the corresponding section, thereby compensating for flicker.

Although many matters are specifically described in the foregoing description, it should be interpreted as an example of a preferred embodiment rather than limiting the scope of the invention. Therefore, the invention should not be determined by the described embodiments, but should be determined by equivalents to the claims and claims.

100: liquid crystal panel 110: timing control
120: gate driver 130: data driver
140: backlight unit 150: driving frequency setting unit
160: luminance compensation unit

Claims (21)

A liquid crystal panel in which a plurality of pixels are formed;
A plurality of driving units for controlling the liquid crystal panel;
A backlight unit providing light to the liquid crystal panel in response to a PWM (Pulse Width Modulation) signal;
A timing control unit receiving image data and timing signals and generating control signals of the plurality of driving units and backlight control signals;
A driving frequency setting unit skipping a predetermined frame of the image data when driving at a low frequency in conjunction with the timing control unit according to a set driving frequency; And
A luminance compensation unit that compensates the luminance of the backlight unit by applying different compensation values to the PWM signal in the refresh section of the image data corresponding to the backlight control signal.
Including,
The luminance compensation unit,
An image brightness value adjustment block for lowering the duty ratio of the PWM signal by a set value when the display brightness value (DBV) included in the backlight control signal is maximized and the PWM signal is set as a DC waveform;
A duty cycle setting block that increases the luminance of the backlight unit by adding a compensation value to the PWM signal in a refresh period with reference to the set value
A liquid crystal display device comprising a. According to claim 1,
The timing control unit,
A control signal processing block generating a control signal of the driver in response to the timing signal;
An image signal processing block that converts and outputs the image data in a form that the driver can process;
CABC (Content Adaptive Brightness Control) block for generating luminance data for the brightness of the backlight unit in response to the image data; And
A backlight control signal generation block that generates the backlight control signal in response to the luminance data
A liquid crystal display device comprising a. According to claim 2,
The backlight control signal generation block,
When generating the backlight control signal, further comprising an image brightness value processing block reflecting the image brightness value,
The image brightness value processing block,
A first mux for selecting the set maximum backlight luminance as the image brightness value (DVB) according to whether the CABC unit is driven;
A second mux for selecting one of output and disable values of the first mux according to whether the backlight control unit is on or off; And
The third mux outputs the backlight control signal by selecting one of the output and disable values of the second mux according to whether the backlight unit is on or off.
And an equivalent circuit. According to claim 1,
The luminance compensation unit,
A control signal determination block receiving the backlight control signal and determining a frame skip mode;
A range setting block for determining a range of the refresh section; And
PWM generation block that generates PWM signal according to the setting result
A liquid crystal display device comprising a. The method of claim 4,
The image brightness value adjustment block,
When the PWM signal is a DC waveform, if the image brightness value is 100%, the liquid crystal display device characterized in that the image brightness value is lowered to 90% to 95%. The method of claim 4,
The range setting block,
Among the timing signals, the liquid crystal display device, characterized in that to set the range of the refresh period in synchronization with the vertical synchronization signal (Vsync). The method of claim 6,
The refresh section,
A liquid crystal display device, characterized in that it is set to a point in time delayed by a predetermined time from the start point of the frame in which the image data is updated. The method of claim 6,
The refresh section
And a predetermined number of neighboring frames, including a frame in which the image data is updated. According to claim 1,
The pixel,
A liquid crystal display device, characterized in that the semiconductor layer comprises a thin film transistor made of oxide. As a driving circuit of a liquid crystal display device including a backlight unit,
A control signal determination block receiving the backlight control signal and determining a frame skip mode;
Adjust the image brightness value that lowers the duty ratio of the PWM signal by a set value when the PWM (Pulse Width Modulation) signal is set to the DC waveform by maximizing the display brightness value (DBV) included in the backlight control signal. block;
A duty cycle setting block for increasing the luminance of the backlight unit by adding a compensation value to the PWM signal in a refresh period with reference to the set value;
A range setting block for determining a range of the refresh section; And
PWM generation block that generates a PWM signal according to the setting result and outputs it to the backlight unit
A driving circuit of a liquid crystal display device comprising a. The method of claim 10,
The image brightness value adjustment block,
When the image brightness value is 100%, the driving circuit of the liquid crystal display device, characterized in that the image brightness value is lowered to 90% to 95%. The method of claim 10,
The range setting block,
A driving circuit of a liquid crystal display device, wherein the refresh section is set in response to a vertical synchronization signal (Vsync) among timing signals input from an external system. The method of claim 12,
The refresh section,
The driving circuit of the liquid crystal display device, characterized in that it is set to a point in time that is delayed by a predetermined time from the point in time when the image data is updated. The method of claim 13,
The refresh section,
The driving circuit of the liquid crystal display device further comprises a predetermined number of neighboring frames, including a frame in which the image data is updated. As a driving method of a liquid crystal display device including a backlight unit,
Receiving the backlight control signal and determining a frame skip mode;
Lowering the duty ratio of the PWM signal by a set value when the image brightness value included in the backlight control signal becomes maximum and a PWM (Pulse Width Modulation) signal is set as a DC waveform;
Increasing the luminance of the backlight unit by adding a compensation value to the PWM signal in a refresh period with reference to the set value;
Determining a range of the refresh period; And
Generating a PWM signal according to the setting result and outputting it to the backlight unit
Method of driving a liquid crystal display device comprising a. The method of claim 15,
Lowering the duty ratio of the PWM signal by a set value,
When the image brightness value is 100%, the method of driving a liquid crystal display device, characterized in that the image brightness value is lowered to 90% to 95%. The method of claim 15,
Determining the range of the refresh section,
A method of driving a liquid crystal display device, wherein a refresh period is set in response to a vertical synchronization signal (Vsync) among timing signals input from an external system. The method of claim 17,
Determining the range of the refresh section,
A method of driving a liquid crystal display device, characterized in that a refresh period is set to a time delayed by a predetermined time from a time when the image data is updated. The method of claim 18,
The refresh section,
A method of driving a liquid crystal display, further comprising a predetermined number of neighboring frames, including a frame in which the image data is updated. According to claim 1,
The luminance compensation unit,
The first compensation value (a) is added to the PWM signal during the Nth frame in which the image data is updated,
The second compensation value (b) is added to the PWM signal during the (N + 1) th frame, which is the next frame of the Nth frame,
And a third compensation value (c) is added to the PWM signal during the (N + 2) frame, which is the next frame of the (N + 1) frame. The method of claim 20,
The first compensation value (a) is added to the PWM signal at a time delayed by a predetermined time from the start time of the N-th frame in consideration of the response speed of the liquid crystal of the liquid crystal panel.

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