KR20150057851A - Liquid crystal display device, appatus and method for driving the same - Google Patents

Abstract

Disclosed is a liquid crystal display device. More particularly, the present invention relates to a liquid crystal display device capable of preventing a flicker phenomenon generated in a liquid crystal display which performs low frequency operation using an oxide thin film transistor having superior cut off property, an apparatus and a method for driving the same. According to the embodiment of the present invention, the brightness of a back light according to the shape of an image is controlled by applying a compensation value to a PWM signal applied to a back light part corresponding to a refresh range. Thereby, a flicker error is prevented. A high-quality image can be obtained.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display (LCD), a driving apparatus and a method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device in which a flicker phenomenon occurring in a liquid crystal display device that realizes low-frequency driving using an oxide thin film transistor having excellent cut- A display device, a driving apparatus and a method thereof.

In order to meet these requirements, there is a need for a thin film transistor (TFT) to be applied as a switching device for a display device and a driving device having excellent performance without an increase in cost, along with enlargement of a substrate such as a glass substrate.

A typical amorphous silicon thin film transistor (a-Si TFT) as a driving and switching device of a display device can be uniformly formed on a large substrate over 2 m at low cost, and is widely used today.

However, due to the trend toward larger and higher-quality display devices, high performance is required for device performance, and it is considered that the conventional a-Si TFT having a mobility of 0.5 cm 2 / Vs will reach the limit.

Therefore, there is a need for high-performance TFTs and manufacturing techniques with higher mobility than a-Si TFTs. In addition, the a-Si TFT continues to operate as the weakest point, and the device characteristics continue to deteriorate, which causes a reliability problem that the initial performance can not be maintained.

At present, researches to overcome the limitations of a-Si TFTs are being carried out continuously, and among them, oxide semiconductor TFTs are a typical example.

Such an oxide TFT has a higher mobility than an amorphous silicon (a-Si) TFT, and is more advantageous in implementing a driving circuit for controlling a switching element as well as a switching element in a liquid crystal panel provided in a liquid crystal display Accordingly, the driving frequency of the liquid crystal display device can be changed to 60 Hz or less to reduce the consumption current.

1 is a graph showing pixel charging characteristics of a conventional liquid crystal display device. Referring to FIG. 1, when a gate high signal (VGH) is applied for one horizontal period (1H) for each gate wiring in one frame, And the data signal Vdata is applied in synchronization with this. At this time, the pixel voltage (Vp) charged in the actual pixel is gradually charged according to the RC delay of the data line. When the potential of the gate high signal (VGH) transitions to the gate low signal (VGL) (Toff). The turn-off period of the TFT is maintained until the next frame. In the figure, an example in which the data signal Vdata is alternately changed to a positive polarity and a negative polarity for each frame by inversion driving is shown.

On the other hand, with respect to the buffered pixel, the potential of the pixel voltage Vp is lowered by a certain amount (DELTA Vp) due to the leakage current generated in each TFT on the turn-off substrate of the TFT. The amount of the leakage current is attributed to the cut-off characteristic of the TFT, and the oxide TFT is superior in characteristics to the amorphous silicon TFT or the polysilicon TFT, so that the amount of the leakage current is small. Therefore, during the turn-off period of the TFT, the pixel voltage variation amount? Vp is minimized, and even if the period is extended, the image hardly changes, and low frequency driving becomes possible.

Accordingly, a liquid crystal display device using an oxide TFT has a driving frequency setting unit and skips a frame, thereby realizing a low frequency driving liquid crystal display device.

2 is a view schematically showing the structure of a conventional driving frequency variable type liquid crystal display device.

Referring to FIG. 2, a conventional driving frequency variable type liquid crystal display device includes a liquid crystal panel 1 in which pixels are formed using an oxide TFT, a liquid crystal panel 1 that receives image data and a timing signal from outside, A driving unit 3 for driving the liquid crystal panel 1 according to a control signal applied from the timing control unit 2 and a driving frequency setting unit 3 for adjusting a driving frequency of the liquid crystal panel 1 (5).

Particularly, in the conventional liquid crystal display device, the driving frequency is set to 60 Hz or more as a default, and the image is displayed corresponding to image data of 60 frames input from the outside. In case of driving at a low frequency of 60 Hz or less, a predetermined number of frames are skipped according to the set value of the driving frequency setting unit 5, A predetermined image is displayed through the charged pixel voltage.

However, even if a predetermined frame is skipped, the pixel voltage of each pixel periodically needs to be refreshed according to the image, and a flicker due to the bending of light occurs in the refresh period.

3 is a graph showing a luminance relationship of an image according to a signal waveform of a conventional low frequency driving liquid crystal display device.

Referring to FIG. 3, in the conventional low frequency driving liquid crystal display device, the gate driving voltage Vg is applied in the refresh interval according to the gate clock signal gclk, and the TFT is turned on. In addition, when the data voltage Vdata having a positive or negative polarity is applied in synchronization with this, it can be confirmed that the brightness of the image instantaneously decreases in the interval. Such a decrease in luminance causes the viewer to be perceived as a flicker.

This is due to the asymmetry between the polarities of the pixel voltages precharged in the previous section and the large fluctuation of the liquid crystal angle due to the polarity reversal when the data voltage is charged in the pixel in the refresh interval, Which is a cause of deteriorating the image quality of the image.

SUMMARY OF THE INVENTION The present invention is conceived to solve the above-described problems, and relates to a liquid crystal display device, a driving apparatus and a method thereof, which improves the flicker defect of a liquid crystal display device which realizes low-frequency driving by using an oxide TFT.

In order to achieve the above object, a liquid crystal display according to a preferred embodiment of the present invention includes: a liquid crystal panel having a plurality of pixels; A plurality of drivers for controlling the liquid crystal panel; A backlight unit for supplying light to the liquid crystal panel in response to a PWM signal; A timing controller receiving the image data and the timing signal and generating a control signal of the plurality of drivers and a backlight control signal; A driving frequency setting unit that skips a predetermined frame of the image data when the low frequency driving is performed in association with the timing control unit in accordance with the set driving frequency; And a luminance compensator for compensating for the brightness of the backlight by applying different compensation values to the PWM signal in a refresh interval of the image data corresponding to the backlight control signal.

According to another aspect of the present invention, there is provided a driving circuit for a liquid crystal display including a backlight unit, the driving circuit comprising: a control signal judgment block for receiving the backlight control signal and determining a frame skip mode; A DBV adjusting block for lowering a duty ratio of the PWM signal by a set value when the PWM signal is set to a DC waveform by referring to a video brightness value included in the backlight control signal; A duty cycle setting block for determining a compensation value for the PWM signal in a refresh interval with reference to a set value; A range setting block for determining a range of the refresh period; And a PWM generation block for generating a PWM signal according to a setting result and outputting the PWM signal to the backlight unit.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display including a backlight unit, the method comprising: receiving the backlight control signal and determining a frame skip mode; Lowering the duty ratio of the PWM signal by a set value when the PWM signal is set to a DC waveform by referring to the image brightness value included in the backlight control signal; Determining a compensation value for the PWM signal in a refresh interval with reference to a set value; Determining a range of the refresh interval; And generating a PWM signal according to a setting result and outputting the PWM signal to the backlight unit.

The liquid crystal display according to the embodiment of the present invention applies the compensation value to the PWM signal applied to the backlight unit corresponding to the refresh period to adjust the brightness of the backlight according to the shape of the image to improve the flicker defect, The image can be implemented.

1 is a graph showing a pixel charging characteristic of a conventional liquid crystal display device.
2 is a view schematically showing the structure of a conventional driving frequency variable type liquid crystal display device.
3 is a graph showing a luminance relationship of an image according to a signal waveform of a conventional low frequency driving liquid crystal display device.
4 is a view showing the structure of a liquid crystal display device according to an embodiment of the present invention.
5A is a block diagram showing a timing controller of a liquid crystal display according to an embodiment of the present invention.
5B is a waveform diagram showing an example of a signal waveform for a PWM signal generated by the backlight control signal bcs of FIG. 5A.
6 is an equivalent circuit diagram of a logic operation circuit included in a backlight control signal generation block according to an embodiment of the present invention.
7 is a block diagram showing a structure of a luminance compensation unit according to an embodiment of the present invention.
8 is a flowchart showing a driving method using the driving circuit of the liquid crystal display shown in Fig.
9 is a diagram showing a signal output form by a driving method of a liquid crystal display according to an embodiment of the present invention.

Hereinafter, a liquid crystal display, a driving apparatus and a driving method thereof according to a preferred embodiment of the present invention will be described with reference to the drawings.

4 is a view showing the structure of a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 4, the liquid crystal display of the present invention includes a liquid crystal panel 100 having a plurality of pixels formed thereon, a liquid crystal panel 100 receiving the control signals of the plurality of drivers 120 and 130, A plurality of driving units 120 and 130 for controlling the liquid crystal panel 100, a backlight unit 140 for providing light to the liquid crystal panel 100 in response to the PWM signal, A driving frequency setting unit 150 for skipping a predetermined frame of the video data during low frequency driving in cooperation with the timing control unit 110 in accordance with the driving frequency, And a luminance compensation unit 160 for controlling the luminance of the backlight unit 140 by controlling the signals.

The liquid crystal panel 100 is composed of two transparent substrates bonded together with a predetermined distance therebetween and a liquid crystal layer interposed therebetween. Among the two substrates described above, a plurality of gate lines GL and a plurality of data lines DL are arranged in a matrix on a lower substrate, and a plurality of pixels PX are defined at intersections of the gate lines GL and the data lines DL. A thin film transistor T and a liquid crystal capacitor LC, which are switching elements, are formed in each pixel PX. Although not shown, the liquid crystal capacitor LC may further be connected to a storage capacitor (not shown) to stably maintain the potential of the pixel voltage charged in the pixel PX.

Particularly, in the thin film transistor T of the liquid crystal panel 100 according to the embodiment of the present invention, the active layer is made of an oxide semiconductor rather than amorphous silicon. Wherein the active layer comprises at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga) (Si) may be used as the metal material. For example, it may be made of indium zinc oxide (Si-InZnO: SIZO) and amorphous indium gallium zinc oxide (a-IGZO) in which silicon ions are added to an indium zinc composite oxide (InZnO). Particularly, in the case of the thin film transistor T in which the active layer is formed by using a-IGZO, it has a high mobility characteristic, is easy to control the doping concentration, and can be deposited in a large area even at a low temperature.

On the other hand, a color filter for displaying red, green, and blue primary colors and a black matrix for partitioning each pixel region are formed on the upper substrate.

The timing control unit 110 receives digital image data RGB and control related timing signals CLK, Hsync, and Vsync such as a clock signal from an external system (not shown) that provides a video source, And generates control signals GCS and DCS to be input to the respective drivers 120 and 130.

In particular, the timing controller 110 of the present invention converts the control signals of the gate and data drivers 120 and 130 according to the frequency set corresponding to the frequency control signal FCS input from the drive frequency setting unit, And generates a control signal. To this end, the timing controller 110 further includes a backlight control signal generating block (not shown). The timing controller 110 receives a backlight dimming signal, a brightness control block on / off state, and a backlight on / . A detailed description of this backlight control block will be described later.

The timing controller 110 is connected to an external system (not shown) through a predetermined interface scheme and receives the above signals. The interface includes an LVDS (Low Voltage Differential Signal) interface and a TTL interface Etc. may be applied.

The gate driver 120 for driving the thin film transistor T and the data driver 130 for supplying the data signal Vdata include a gate driver 120 for controlling the liquid crystal panel 100, .

The gate driver 120 turns on / off the thin film transistors T arranged on the liquid crystal panel 100 in response to a gate control signal GCS input from the timing controller 110. [ .

The gate driving unit 120 includes a shift register constituting a plurality of channels and generates a gate driving signal Vg to input a gate high signal VGH to one gate line GL for one horizontal period 1H And turns on the thin film transistor T of the liquid crystal panel 110. [ At the same time, the data signal Vdata is input from the data line DL and charged to the liquid crystal capacitor LC connected through each thin film transistor T with the pixel voltage. At this time, the gate line signal VGL is inputted to the other gate line GL so that the thin film transistor T connected to the other gate line GL is maintained in the turned off state. A period during which the pixel voltage is charged is defined as a video data update time and is defined as a holding period during which the currently charged pixel voltage is maintained until immediately before the next update starts.

In particular, the pixel voltage must be maintained constant during the holding period, and the holding period is extended in the low frequency driving. That is, in the case of a liquid crystal display device in which all the gate lines GL are driven for one frame and the driving frequency is set to 60 Hz, the update is repeated 60 times for 1 second, but when the driving frequency is set to a very low frequency of 1 Hz A holding period of 59 frames is set after the pixel voltage update of one frame.

The gate control signal GCS input to the gate driver 120 includes gate start pulses (GSP), gate shift clock (GSC), gate output enable (GOE) And the like. The gate driver 120 sequentially shifts the input gate start pulse GSP in synchronization with the gate shift clock GSC to sequentially input the gate driving signal Vg to the plurality of gate lines GL . Here, the pulse width of the gate driving signal Vg is controlled in accordance with the gate output enable GOE.

The data driver 130 converts the video signal aRGB of the digital form arranged by the timing controller 110 into an analog form according to the reference voltage in response to the data control signal DCS input from the timing controller 110 To the respective pixels PX of the post-liquid crystal panel 100.

The data control signal DCS includes a source start pulse (SSP), a source shift clock (SSC), and a source output enable (SOE) signal. The timing control section 110 into a data signal Vdata of an analog waveform and inputs the data signal Vdata to the liquid crystal panel 100. [ Specifically, the data driving circuit 130 samples and latches a video signal aRGB input from the timing control unit 110 corresponding to the source start pulse SSP and the source shift clock SSC, A data signal Vdata for one horizontal line is supplied to the data line DL every one horizontal period 1H in which the gate driving signal VG is supplied in response to the output enable SOE.

The backlight unit 140 is disposed on the back surface of the liquid crystal panel 100 to provide light for image display. The backlight unit 140 includes a light source and a driving circuit for driving the backlight unit 140. The backlight unit 140 emits light corresponding to the backlight control signal generated from the timing controller 110, And is driven by an applied PWM (Pulse Width Modulation) signal.

The backlight unit 140 is driven by a PWM method that determines the on and off periods of the light sources according to the duty ratio. When the backlight dimming method is applied, the backlight unit 140 is grouped into a predetermined number, The surface light source irradiating the surface light source may be divided into a plurality of logical blocks. The backlight dimming method can be applied to a direct type but also to an edge type. Particularly, as a light source of the backlight unit 140, a light emitting diode (LED) which is a point light source advantageous for blocking can be used.

An optical member (not shown) may be provided between the backlight unit 140 and the liquid crystal panel 100 to increase the efficiency of light emitted from the backlight unit 140. The optical member may include a light source A light guide plate and a prism sheet for guiding emitted light, a reflector, and the like.

The driving frequency setting unit 150 supplies the timing control unit 110 with a control signal FCS for changing the driving frequency according to a preset driving frequency setting value. In particular, the driving frequency setting unit 150 has a function of skipping a part of frames of the image data (RGB) input to the timing control unit 110 when the liquid crystal display device is set to a low driving frequency of 60 Hz or less .

That is, in the case of a liquid crystal display device in which the driving frequency is set to 60 Hz or less, the updating process is repeated a number of times smaller than 60 frames for 1 second. When the driving frequency is set to a very low frequency of 1 Hz, After the refresh interval of two or three frames including one or two frames, the remaining interval is set as the holding interval. Accordingly, the video data for the remaining 59 frames are skipped by the driving frequency setting unit 150. [

The function of the driving frequency setting unit 150 may be blocked and integrated into the timing control unit 110 as an integrated IC.

The luminance compensation unit 160 generates a PWM signal for determining the backlight luminance value corresponding to the backlight control signal bcs input from the timing controller 110 and applies the generated PWM signal to the backlight unit 140. [ The backlight control signal bcs includes whether the current liquid crystal display device has frame skipping according to the low frequency driving and the display brightness value DBV according to the currently displayed image type, ) Determines the duty ratio of the PWM signal in the refresh interval and the holding interval.

In particular, the brightness compensator 160 determines the degree of adjustment of the duty ratio of the PWM signal and the start and end points of the PWM signal in the refresh interval according to a predetermined set value. Particularly, in the refresh interval, When the ratio of the image being displayed to the white region is high, it is possible to minimize the deterioration of the image quality due to the excessively high luminance by lowering the luminance rather than increasing the luminance. With respect to an image with a normal luminance, flicker deficiency due to a decrease in luminance is eliminated by raising the luminance of the backlight at a predetermined level higher than the holding period in the refresh period during low-frequency driving. A more detailed description of the luminance compensation unit 160 will be described later.

According to the above-described structure, the liquid crystal display of the present invention improves the flicker defect occurring in the refresh period during low-frequency driving, thereby realizing a high-quality image.

Hereinafter, the structure of the timing controller included in the liquid crystal display device of the present invention will be described in detail with reference to the drawings.

5A is a block diagram showing a timing controller of a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 5A, the timing controller 110 of the present invention includes a control signal processing block 112 for generating control signals of the gate and data driver in response to the timing signal, A CABC block 115 for generating brightness data Bdata for the brightness of the backlight unit corresponding to the image data RGB; a video signal processor 114 for converting the video data RGB And a backlight control signal generation block 117 for generating the backlight control signal bcs corresponding to the brightness data Bdata.

The control signal processing unit 112 controls the driving of the gate driving circuit and the data driving unit in response to the timing signals such as the vertical and horizontal synchronizing signals Vsync and Hsync and the clock signal DCLK input from an external system And generates and outputs gate and data control signals (GCS and DCS).

The image data processing unit 114 receives the image data RGB and outputs the sorted image data aRGB by arranging the image data in a form that can be processed by the data driver. In particular, the image data processing unit 114 refers to the luminance data (bdata) of the image data (RGB) from the CABC block 115 to be described later and controls the gamma control Block 1141 may be further included.

The content adaptive brightness control (CABC) block 115 is a circuit block that controls the brightness of the screen and determines the overall brightness of the image displayed through the image data RGB, And adjusting the duty ratio of the PWM signal to reduce power consumption. Since the power consumed by the light source is higher than the gray level of the image, the method of adjusting the PWM signal is preferred.

The CABC block 115 directly analyzes the luminance of the image according to the image data RGB. Another method of performing the similar function is the LABC (Light Sensor Automatic Brightness Control) method. The LABC can replace the CABC block 115 as a method of adding a sensor to detect the brightness of the screen.

The backlight control signal generation block 117 is a block for generating a backlight control signal bcs for controlling the driving of the backlight unit by referring to the luminance data Bdata. The backlight control signal bcs serves as a reference for determining the duty ratio of the PWM signal for driving the light source of the backlight unit and the backlight dimming control is also performed by the signal bcs. Accordingly, the backlight control signal generating block 117 may include a DBV processing block 1171 for processing the brightness data bcs including the display brightness value DBV for the image .

In particular, the backlight control signal generating block 117 generates the backlight control signal bcs within the range of the brightness setting value Bset for the predetermined backlight luminance. The brightness setting value (Bset) defines the brightness control range (0 to 255) of the backlight.

5B is a waveform diagram showing an example of a signal waveform for a PWM signal generated by the backlight control signal bcs of FIG. 5A. 5B, when the backlight luminance control range is defined as 0d to 255d, when the backlight unit is turned off (0d), when the backlight unit is turned on (255d), and the luminance is adjusted to 33% An example of case (88d) can be seen, which is determined by the duty ratio.

Particularly, when the image is a very bright image 255d, that is, when the brightness of the image is maximum, if the ON state of the backlight is maintained, the DC signal is maintained for a predetermined period of the PWM signal and the brightness is further increased Can not. In order to overcome this limitation, the backlight control signal generation block of the present invention includes a circuit that reflects the DBV to the backlight control signal bcs according to the PWM signal waveform.

6 is an equivalent circuit diagram of a logic operation circuit included in a backlight control signal generation block according to an embodiment of the present invention.

6, the backlight control signal generating block 117 of the present invention may further include a DBV processing block 1171 for reflecting the image brightness value DBV to the backlight control signal bcs, (MUX1, MUX2, MUX3) that reflects the maximum brightness value determined according to the signals con1, con2, con3 as the image brightness value DBV in the backlight control signal bcs have.

First, the first multiplexer MUX1 outputs a preset maximum luminance value Max.bc when the backlight dimming is performed by the first control signal con1 defining whether or not the backlight dimming is performed, and if not, And outputs ground (GND), that is, 0. Here, when the backlight dimming is not performed, since the PWM signal having the fixed duty ratio is outputted, the luminance data value by the calculation of the CABC becomes unnecessary.

Next, the second Mux 2 outputs the output value of the first MUX as it is when the second control signal con2 defining the on / off state of the backlight control signal generating block is on, , It outputs a ground (GND), that is, an O value.

The third MUX3 outputs the output value of the second MUX as it is when the third control signal con3 defining the ON / OFF state of the backlight unit is ON. When the third control signal con3 is OFF, the third MUX3 outputs a ground ) That is, O value is output.

According to this structure, the DVB processing block 1171 sets the maximum luminance value of the predetermined backlight portion to the image brightness value DBV, and provides it to the backlight control signal generation block. The backlight control signal generation block supplies the backlight control signal bcs And outputs it to the luminance compensation unit.

Hereinafter, a luminance compensation unit of a low-frequency driving liquid crystal display according to an embodiment of the present invention will be described with reference to the drawings.

7 is a block diagram showing a structure of a luminance compensation unit according to an embodiment of the present invention.

7, the luminance compensator 160 of the present invention includes a control signal judgment block 161 for receiving a backlight control signal bcs and determining a frame skip mode, and a backlight control signal bcs A DBV adjusting block 162 for lowering the duty ratio of the PWM signal by a set range when the PWM signal is set to a DC waveform by referring to the image brightness value DBV obtained by the PWM comparator 162, A duty cycle setting block 163 for adding a compensation value, a range setting block 164 for setting the start and end points of the refresh interval with reference to the set value, and a PWM generating block 165 ).

The control signal judgment block 161 receives the backlight control signal bcs and judges whether or not the frame skipping is performed according to the low frequency driving included in the backlight control signal bcs. When the frame skip occurs, the image brightness value DBV is adjusted by requesting the DBV adjustment block 162. Otherwise, the PWM generation block 165 generates the PWM signal according to the basic setting.

The DBV adjustment block 162 is a block for adjusting the image brightness value DBV according to the backlight driving mode when a frame skip occurs. The backlight driving mode corresponds to the PWM signal, and if the PWM signal is a DC waveform, the maximum brightness value continues for a predetermined period, and the received image brightness value DBV can be set to OxFF. At this time, there is no problem of luminance drop in the refresh interval, but since the luminance can not be increased any more in the holding period, the luminance compensation can not be performed by adjusting the duty ratio of the PWM signal. In order to overcome this limitation, according to the embodiment of the present invention, when the image brightness value (DBV) in the low frequency driving is the maximum luminance, the maximum luminance is reduced to 5% to 10% or less. That is, if the brightness is 100% when the image brightness value (DBV) is OxFF, it is adjusted so that the image brightness value (DBV) does not exceed 95% by lowering the brightness by 5%, 100% in the refresh interval, % Luminance so that the luminance is relatively lowered in the refresh interval.

The duty cycle setting block 163 increases the duty ratio of the PWM signal in the refresh interval according to the set value. The maximum luminance is determined by the DBV adjustment block 162 and the compensation value is added to the image brightness value DBV in accordance with the ratio set in the refresh interval in which the luminance deterioration occurs to compensate for the luminance decrease.

The range setting block 164 serves to determine the range of the refresh interval according to the set value. Since the liquid crystal response speed of the liquid crystal panel is usually slower than the LED response speed, there is a problem that the brightness is instantaneously increased immediately when the brightness compensated PWM signal is applied immediately after the start of the refresh interval. In order to minimize such a problem, the start point of the PWM signal is set to a point of time delayed from the start point of the refresh period by a certain time.

Particularly, the range setting block 164 can determine the start point of the refresh interval and determine the PWM start and end points in synchronization with the vertical synchronization signal Vsync, among the timing signals of the liquid crystal display device.

The PWM generation block 165 generates a PWM signal PWM having a duty ratio set by the above blocks and supplies the generated PWM signal PWM to the backlight unit.

Hereinafter, a driving method of a liquid crystal display according to an embodiment of the present invention will be described with reference to the drawings.

8 is a flowchart showing a driving method using the driving circuit of the liquid crystal display shown in Fig.

Referring to FIG. 8, a method of driving a liquid crystal display according to the present invention includes steps S110 and S120 of receiving a backlight control signal and determining a frame skip mode, and controlling the backlight control signal (S131, S132) lowering the duty ratio of the PWM signal by a set range when the PWM signal is set to a DC waveform by referring to the image brightness value included in the PWM signal, (S151, S152) of setting a range of a refresh interval with reference to a set value, and a step (S160) of generating a set PWM signal and supplying it to the backlight unit .

First, the driving circuit of the liquid crystal display receives the backlight control signal bcs including the image brightness value DVB (S110), and determines whether the frame skip mode is applied by the low frequency driving unit (S120). If the frame skip mode is not applied, the PWM signal is generated according to the basic setting value and outputted to the backlight unit (S160).

When the frame skip mode is applied, the PWM waveform is analyzed to adjust the image brightness value DVB within a range of 5% to 10% for a DC waveform (S132). Next, the set value for the preset PWM duty cycle is referenced (S141), and the compensation value is added to the reference brightness value DVB to increase the brightness of the backlight in the refresh interval (S142). At this time, the adjusted image brightness value DVB may be a value adjusted in step S132.

Next, referring to the preset value (S151), the range of the refresh interval S151 is adjusted (S152). This can be set in units of frames, and a refresh interval including a predetermined number of frames is determined in addition to a frame in which image data starts to be updated. Particularly, since the video data update time corresponds to the timing at which the gate drive signal of the liquid crystal display device is outputted, the corresponding section can be set in synchronization with the vertical synchronization signal Vsync.

According to the above steps, a PWM signal according to the set duty ratio is generated and output to the backlight unit (S160).

Hereinafter, a signal output mode according to a driving method of a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.

9 is a diagram showing a signal output form by a driving method of a liquid crystal display according to an embodiment of the present invention.

As shown in FIG. 9, the frame in which the data update has occurred has the identification code of N, and the frame in which the data update has occurred has the identification code of N. The image of one frame to ten frames is output by driving the liquid crystal display device, ) Is 60%, the luminance compensator compensates the luminance by adding the compensation values (a, b, c) set for the image luminance value (DVB) from the three frames in which the image data is updated. In the drawing, three frames are set as a refresh interval, and different luminance compensation values are added.

In particular, the refresh interval includes a predetermined number of 4 frames and 5 frames adjacent to the 3 frames including the start of the update of the image data. Accordingly, the brightness compensation unit is turned on for 1, 2, and 3 times in 3 to 5 frames, and the compensation value for the image brightness value (DBV) is delayed to a predetermined point in consideration of the response speed of the liquid crystal.

Accordingly, the image out outputted through the liquid crystal panel is output with the luminance added with the compensation values of a, b, and c in the corresponding interval, thereby compensating for the flicker phenomenon.

While a number of embodiments have been described in detail above, it should be construed as being illustrative of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

100: liquid crystal panel 110: timing controller
120: Gate driver 130: Data driver
140: backlight unit 150: driving frequency setting unit
160: luminance compensation unit

Claims (19)

A liquid crystal panel in which a plurality of pixels are formed;
A plurality of drivers for controlling the liquid crystal panel;
A backlight unit for supplying light to the liquid crystal panel in response to a PWM signal;
A timing controller receiving the image data and the timing signal and generating a control signal of the plurality of drivers and a backlight control signal;
A driving frequency setting unit that skips a predetermined frame of the image data when the low frequency driving is performed in association with the timing control unit in accordance with the set driving frequency; And
A brightness compensation unit for applying a different compensation value to the PWM signal in the refresh interval of the image data corresponding to the backlight control signal to compensate the brightness of the backlight unit;
And the liquid crystal display device. The method according to claim 1,
Wherein the timing control unit comprises:
A control signal processing block for generating a control signal of the driving unit corresponding to the timing signal;
A video signal processing block for converting and outputting the image data in a form that can be processed by the driving unit;
A CABC block for generating luminance data on the brightness of the backlight unit corresponding to the image data; And
A backlight control signal generation block for generating the backlight control signal corresponding to the brightness data;
And the liquid crystal display device. 3. The method of claim 2,
The backlight control signal generating block includes:
Further comprising a DBV processing block for reflecting the image brightness value (DBV) when the backlight control signal is generated,
The DBV processing block includes:
A first mux for selecting the set backlight maximum luminance value as the image brightness value (DVB) according to whether the CABC unit is driven or not;
A second mux for selecting any one of an output and a disable value of the first mux depending on whether the backlight control unit is turned on or off; And
And a third mux for selecting either the output or the disable value of the second mux according to whether the backlight unit is turned on or off and outputting the backlight control signal,
And an equivalent circuit. The method according to claim 1,
Wherein the luminance compensation unit comprises:
A control signal judgment block for receiving the backlight control signal and judging a frame skip mode;
A DBV adjusting block for lowering a duty ratio of the PWM signal by a set value when the PWM signal is set to a DC waveform by referring to a video brightness value included in the backlight control signal;
A duty cycle setting block for determining a compensation value for the PWM signal in a refresh interval with reference to a set value;
A range setting block for determining a range of the refresh period; And
A PWM generation block for generating a PWM signal according to the setting result
And the liquid crystal display device. 5. The method of claim 4,
The DBV adjustment block includes:
Wherein when the PWM signal has a DC waveform and the image brightness value is 100%, the image brightness value is reduced to 90% to 95%. 5. The method of claim 4,
The range setting block includes:
And sets the range of the refresh period in synchronization with the vertical synchronization signal (Vsync) among the timing signals. The method according to claim 6,
The refresh period may include:
And a timing at which the image data is delayed by a predetermined time from a start timing of a frame in which the image data is updated. The method according to claim 6,
The refresh interval
Further comprising a predetermined number of neighboring frames including a frame in which the image data is updated. The method according to claim 1,
The pixel includes:
Wherein the semiconductor layer includes a thin film transistor formed of an oxide. A driving circuit of a liquid crystal display device including a backlight portion,
A control signal judgment block for receiving the backlight control signal and judging a frame skip mode;
A DBV adjusting block for lowering a duty ratio of the PWM signal by a set value when the PWM signal is set to a DC waveform by referring to a video brightness value included in the backlight control signal;
A duty cycle setting block for determining a compensation value for the PWM signal in a refresh interval with reference to a set value;
A range setting block for determining a range of the refresh period; And
Generating a PWM signal according to a setting result and outputting the PWM signal to the backlight unit,
And a driving circuit for driving the liquid crystal display device. 11. The method of claim 10,
The DBV adjustment block includes:
Wherein the image brightness value is reduced to 90% to 95% when the image brightness value is 100%. 11. The method of claim 10,
The range setting block includes:
And sets the refresh period corresponding to the vertical synchronization signal (Vsync) among the timing signals input from the external system. 13. The method of claim 12,
The refresh period may include:
Is set to a time point at which the image data is delayed by a predetermined time from a time point at which the image data is updated. 14. The method of claim 13,
The refresh period may include:
Further comprising a predetermined number of neighboring frames including a frame in which the image data is updated. A driving method of a liquid crystal display device including a backlight portion,
Receiving the backlight control signal and determining a frame skip mode;
Lowering the duty ratio of the PWM signal by a set value when the PWM signal is set to a DC waveform by referring to the image brightness value included in the backlight control signal;
Determining a compensation value for the PWM signal in a refresh interval with reference to a set value;
Determining a range of the refresh interval; And
Generating a PWM signal according to the setting result and outputting the PWM signal to the backlight unit
And a driving method of the liquid crystal display device. 16. The method of claim 15,
Wherein the step of lowering the duty ratio of the PWM signal by a set value comprises:
Wherein the image brightness value is reduced to 90% to 95% when the image brightness value is 100%. 16. The method of claim 15,
Wherein the step of determining the range of the refresh interval comprises:
Wherein a refresh interval is set corresponding to a vertical synchronization signal (Vsync) among timing signals input from an external system. 18. The method of claim 17,
Wherein the step of determining the range of the refresh interval comprises:
Wherein the refresh interval is set to a time point at which the image data is delayed by a predetermined time from a time point at which the image data is updated. 19. The method of claim 18,
The refresh period may include:
Further comprising a predetermined number of neighboring frames including a frame in which the image data is updated.

Images