CN112232019A - Logic resource assessment method - Google Patents

Logic resource assessment method Download PDF

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CN112232019A
CN112232019A CN202011119075.3A CN202011119075A CN112232019A CN 112232019 A CN112232019 A CN 112232019A CN 202011119075 A CN202011119075 A CN 202011119075A CN 112232019 A CN112232019 A CN 112232019A
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CN112232019B (en
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林铠鹏
祁仲冬
李伟
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Shanghai Guowei Silcore Technology Co Ltd
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    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level
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Abstract

The invention discloses a logic resource evaluation method, which comprises the following steps: acquiring a list of relevant features to be estimated; and inputting the relevant feature list to be estimated into an FPGA resource model to obtain an FPGA resource usage estimation value, wherein the FPGA resource model is obtained by training through a training data list based on the model to be trained, the training data list is a set of a feature training list and a resource usage data training list, and the feature training list is a set of RTL description relevant training features and design parameter relevant training features. The FPGA resource model obtained by the method can quickly obtain the on-chip resource usage amount required by RTL description in the initial stage of design, enhance the estimability of design and logic synthesis, and reduce the iteration times.

Description

Logic resource assessment method
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a logic resource evaluation method.
Background
A Field Programmable Gate Array (FPGA) is an important semiconductor device, and can be reprogrammed in the Field to implement a logic design required by a user. After a designer uses a hardware description language to perform Register Transfer Level (RTL) programming design on a circuit, RTL description is converted into bit stream data for configuring an internal structure of an FPGA through a plurality of design synthesis steps, wherein the design synthesis steps include logic synthesis, technical mapping, logic packing, layout, wiring and the like.
At present, for a given RTL description, the number of hardware resources on the FPGA chip required by the RTL description generally needs to be obtained after logic packing and wiring are completed. However, for a circuit design with a large scale, it often takes several hours or even tens of hours to perform a design synthesis flow from RTL description to wiring. When the problem of insufficient on-chip resources occurs, a designer needs to modify the RTL description and perform design synthesis flow iteration which is long in time consumption.
Because the design synthesis flow includes multiple steps, when writing and modifying the RTL description, a designer cannot quickly predict the number of on-chip hardware resources required for implementing a circuit on an FPGA, which may result in failure to complete technical mapping or wiring, and multiple design iterations. In addition, in the logic synthesis, the actual hardware resource quantity required by each part of RTL description also has guiding significance for the conversion and optimization process from the RTL to the gate-level netlist.
In summary, how to quickly obtain the on-chip resource usage amount required by the RTL description in the early stage of design is an important issue. The resource estimation model has important guiding significance for enhancing the estimability of design and logic synthesis and reducing the iteration times.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a method for evaluating logic resources. The technical problem to be solved by the invention is realized by the following technical scheme:
a method of logical resource evaluation, comprising: acquiring a list of relevant features to be estimated;
inputting the list of the relevant features to be estimated into an FPGA resource model to obtain an estimated value of the utilization amount of the FPGA resources, wherein,
the FPGA resource model is obtained by training through a training data list based on a model to be trained, the training data list is a set of a feature training list and a resource usage data training list, and the feature training list is a set of RTL description related training features and design parameter related training features.
In an embodiment of the present invention, obtaining a list of relevant features to be estimated includes:
respectively acquiring relevant features of RTL description to be estimated and relevant features of design parameters to be estimated;
and combining the RTL description related features to be estimated and the design parameter related features to be estimated to obtain the related feature list to be estimated.
In an embodiment of the present invention, the training of the FPGA resource model includes:
acquiring a plurality of groups of training data lists;
sequentially training the model to be trained by utilizing a plurality of groups of training data lists to obtain a plurality of candidate training models;
and performing quality verification on the candidate training models by using verification data to obtain the FPGA resource model.
In one embodiment of the present invention, the model to be trained is a multivariate adaptive regression spline model.
In one embodiment of the present invention, the training parameters of the model to be trained include a maximum number of product terms and an error threshold.
In an embodiment of the present invention, performing quality verification on the candidate training models by using verification data to obtain an output training model, includes:
inputting the verification data into the candidate training model to obtain a plurality of output results;
obtaining the average absolute error corresponding to the candidate training model according to the output results;
and comparing all the average absolute errors to obtain minimum target verification data, wherein the candidate training model corresponding to the minimum target verification data is an FPGA resource model.
In an embodiment of the invention, the RTL description-related training features are obtained by feature extraction through RTL description.
In one embodiment of the invention, the set of usage data training lists of the resources is obtained by routing results.
The invention has the beneficial effects that:
the invention provides a logic resource evaluation method aiming at the problem of how to quickly obtain the on-chip resource usage amount required by RTL description in the early stage of design.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a flow chart of a method for evaluating logic resources according to an embodiment of the present invention;
fig. 2 is a flowchart of another logic resource evaluation method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Referring to fig. 1 and fig. 2, fig. 1 is a flowchart of a logic resource evaluation method according to an embodiment of the present invention, and fig. 2 is a flowchart of another logic resource evaluation method according to an embodiment of the present invention. A method of logical resource evaluation, comprising:
step 1, obtaining a list of relevant features to be estimated.
Specifically, in this embodiment, before performing the RTL-level FPGA resource usage estimation based on machine learning, the list of the relevant features to be estimated needs to be obtained first.
Further, step 1 further comprises:
step 1.1, obtaining RTL description relevant characteristics to be estimated and design parameter relevant characteristics to be estimated respectively.
a. And analyzing the RTL description file by using an HDL (hardware description language) analyzer to obtain the relevant characteristics of the RTL description to be estimated.
Specifically, the list of the relevant features to be estimated includes the relevant features of the RTL description to be estimated, and the acquisition of the relevant features of the RTL description to be estimated needs to analyze the RTL description file by using an HDL parser, that is, the RTL description file is input into the HDL parser, the RTL description file is calculated by using output or internal data of the HDL parser, and the relevant features of the RTL description to be estimated are output.
The HDL parser may be, for example, Verific, and the RTL description file may be, for example, Verilog file.
The RTL description related feature to be estimated includes a series of statistical indicators, and the statistical indicator may be at least one of the following indicators, for example:
the total level number is obtained by counting the output or internal data of the HDL resolver;
leaf node examples, which are leaf nodes on the hierarchical tree and are the number of module examples located at the lowest position of each level;
an average level of leaf node instances;
maximum level of leaf node instance;
the average level of the leaf node example with the highest X% of the level, wherein X can be 5, 10, 15, etc.;
the level variance of leaf node instance is expressed as S2＝((l1-u)2+(l2-u)2+…(li-u)2…+(ln-u)2) N, where n is the total number of leaf node instances, liIs the level of the ith leaf node instance, and u is the level mean of the leaf node instance;
a logic complexity value of a leaf node instance, wherein the logic complexity is measured by the number of basic logic operations in combinational logic and the number of signal assignments in sequential logic;
maximum, mean, variance of the logical complexity of leaf node instances;
the highest average value of Y% for the logical complexity of leaf node instances, Y may be 5, 10, 15, etc.
b. And extracting the relevant characteristics of the design parameters to be estimated from the report file of the logic synthesis software.
Specifically, the list of the relevant features to be estimated includes relevant features of the design parameters to be estimated, and the relevant features of the design parameters to be estimated are design indexes given by a user and need to be extracted from a report file of logic synthesis software.
The relevant characteristics of the design parameters to be estimated comprise a series of statistical indexes which are respectively as follows:
a target frequency, which may be 300MHz, for example;
the threshold for resource utilization may be, for example, 80%;
the amount of on-chip storage available may be, for example, 500 MB.
And 1.2, combining the RTL description relevant characteristics to be estimated and the design parameter relevant characteristics to be estimated to obtain a relevant characteristic list to be estimated.
Specifically, let the RTL to be estimated describe the relevant features as { u }1，u2，…，ui，…，ufSetting relevant characteristics of design parameters to be estimated as { v }1，v2，…，vi，…，vhThe list of relevant features to be estimated is { p }1，p2，…，pi，…，pjAnd combining the estimated RTL description relevant characteristics and the design parameter relevant characteristics to be estimated to obtain a relevant characteristic list to be estimated, wherein the relevant characteristic list to be estimated is { p }1，p2，…，pi，…，pj}＝{u1，u2，…，ui，…，uf，v1，v2，…，vi，…，vh}。
Step 2, inputting the list of the relevant characteristics to be estimated into an FPGA resource model to obtain an estimated value of the utilization amount of the FPGA resources, wherein,
the FPGA resource model is obtained by training by utilizing a training data list based on a model to be trained, the training data list is a set of a feature training list and a resource usage data training list, and the feature training list is a set of RTL description related training features and design parameter related training features.
Specifically, after the FPGA resource model is obtained, the relevant feature list to be estimated is input into the FPGA resource model to calculate to obtain estimated values of different resources. If the FPGA resource model has m expressions, each expression can be used as the FPGA resource model to process the input related feature list to be estimated to obtain estimated values of a plurality of resources.
Further, the training of the FPGA resource model includes:
and 2.1, acquiring a plurality of groups of training data lists.
Further, the training data list is a set of a feature training list and a resource usage data training list, and the feature training list is a set of RTL description related training features and design parameter related training features.
The RTL description related training features are obtained by performing feature extraction on RTL description, feature extraction is performed on RTL description files by using an HDL (hardware description language) parser to obtain RTL description related training features, and design parameter related features are extracted from logic synthesis software report files.
The set of the usage data training list of the resource is obtained through the routing result.
Further, an FPGA comprehensive compiling software tool is used for converting the RTL description into a wiring result, and a set of resource usage data training lists is extracted from the wiring result.
Firstly, inputting the RTL description into an FPGA comprehensive compiling software tool, wherein the FPGA comprehensive compiling software tool can perform logic comprehensive processing to obtain a gate-level netlist, perform process mapping processing on the gate-level netlist to obtain a lookup table-level netlist, perform logic packaging processing on the lookup table-level netlist to obtain a logic block-level netlist, and perform layout and wiring processing on the logic block-level netlist respectively to obtain a wiring result.
The hardware structure of the FPGA includes different types of resources, mainly logic resources and storage resources required for implementing a logic circuit, input/output resources for providing an external interface, and wiring resources for connecting the first two types of units. Specifically, the memory device generally includes a look-up table (LUT), a flip-flop, a digital processing unit (DSP), a Block RAM (BRAM), and the like. The Logic resources such as lookup tables and triggers are generally present in a Logic block (Logic block or Slice). In the design synthesis process, the RTL description is converted into a gate-level netlist irrelevant to the FPGA structure by logic synthesis; then, the gate-level netlist is converted into a lookup table-level netlist formed by different units on the target FPGA through technical mapping; logic packing, and then aggregating a plurality of lookup tables and triggers in the lookup table level netlist into a logic block; in the layout stage, the positions of the logic blocks and other units on the FPGA are searched; in the wiring stage, wiring resources are used to realize the connection between units such as logic blocks; and finally, generating a bit stream for configuring the specific structure of the FPGA.
The FPGA comprehensive compiling software tool can be Xilinx or Vivado, for example, and the processing mode of the FPGA comprehensive compiling software tool comprises interface menu button operation and running command line operation.
The routing result contains usage data of various resources, and the resource usage data list comprises LUTs, DSPs, FFs, BRAMs and the like and is marked as { r1，r2，…，ri，…，rgAnd the resource usage data list comprises a series of statistical indexes, but is not limited to the following indexes:
the number of look-up tables LUT;
the number of flip-flops FF;
the number of digital processing units (DSPs);
the usage number of the block memory BRAM;
the number of registers REG.
And 2.2, training the model to be trained sequentially by utilizing a plurality of groups of training data lists to obtain a plurality of candidate training models.
Further, the model to be trained is a multivariate adaptive regression spline model.
Specifically, a plurality of sets of training data lists are respectively input into a Multivariate Adaptive Regression spline Model (MARS), the Multivariate Adaptive Regression spline model can automatically configure training parameters, the training parameters include the maximum product term number and an error threshold, preferably, the initial value of the maximum product term number can be set to 5, and the initial value of the error threshold is set to 0.05.
And 2.3, carrying out quality verification on the candidate training models by using the verification data to obtain the FPGA resource model.
Further, step 2.3 also includes:
and 2.3.1, inputting a plurality of verification data into the candidate training model to obtain a plurality of output results.
Specifically, the feature verification list and the resource usage data verification list are combined to obtain a multi-element data list, and the multi-element data list is a verification data list.
List of feature verifications { q1，q2，…，qi，…，qkAnd a usage data validation list of resources r1，r2，…，ri，…，rgAre combined to form a tuple { q }1，q2，…，qi，…，qk，r1，r2，…，ri，…，rgEach tuple can be used as a set of verification data, and the feature verification list describes a set of relevant verification features and design parameter relevant verification features for the RTL.
Further, a candidate training model may yield an output.
Let the candidate training model be { M1，M2，…，Mi，…，MnThe output result is { e }1，e2，…，ei，…，en}。
And 2.3.2, obtaining the average absolute error corresponding to the candidate training model according to a plurality of output results.
Specifically, according to output result { e }1，e2，…，ei，…，enGet candidate training model MiAverage absolute error of (e)1+e2+…+ei+…+en)/n。
And 2.3.3, comparing all the average absolute errors to obtain minimum target verification data, wherein the candidate training model corresponding to the minimum target verification data is an FPGA resource model.
Specifically, the candidate training models M are compared1、M2、…、Mi、…、MnThe minimum average absolute error is obtained, the minimum average absolute error is the minimum target verification data, and the candidate training model corresponding to the minimum target verification data is the FPGA resource model.
In summary, in this embodiment, before performing the RTL-level FPGA resource usage estimation based on machine learning, a to-be-estimated relevant feature list needs to be obtained first, where the to-be-estimated relevant feature list includes to-be-estimated RTL description relevant features and to-be-estimated design parameter relevant features, and the to-be-estimated relevant feature list is input to the FPGA resource model to obtain an FPGA resource usage estimation value. The training of the FPGA resource model requires firstly obtaining a plurality of training data lists, training the model to be trained sequentially by using the training data lists to obtain a plurality of candidate training models, and performing quality verification on the candidate training models by using verification data to obtain the FPGA resource model. The FPGA resource model obtained by the method can quickly obtain the on-chip resource usage amount required by RTL description in the initial stage of design, enhance the estimability of design and logic synthesis, and reduce the iteration times. The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (8)

1. A method for evaluating a logical resource, comprising:
acquiring a list of relevant features to be estimated;
inputting the list of the relevant features to be estimated into an FPGA resource model to obtain an estimated value of the utilization amount of the FPGA resources, wherein,
the FPGA resource model is obtained by training through a training data list based on a model to be trained, the training data list is a set of a feature training list and a resource usage data training list, and the feature training list is a set of RTL description related training features and design parameter related training features.
2. The logic resource evaluation method according to claim 1, wherein obtaining the list of relevant features to be evaluated comprises:
respectively acquiring relevant features of RTL description to be estimated and relevant features of design parameters to be estimated;
and combining the RTL description related features to be estimated and the design parameter related features to be estimated to obtain the related feature list to be estimated.
3. The logic resource assessment method of claim 1, wherein the training of the FPGA resource model comprises:
acquiring a plurality of groups of training data lists;
sequentially training the model to be trained by utilizing a plurality of groups of training data lists to obtain a plurality of candidate training models;
and performing quality verification on the candidate training models by using verification data to obtain the FPGA resource model.
4. The logic resource assessment method according to claim 3, wherein said model to be trained is a multivariate adaptive regression spline model.
5. The logic resource assessment method of claim 3, wherein the training parameters of the model to be trained comprise a maximum number of product terms and an error threshold.
6. The logic resource assessment method according to claim 3, wherein the quality verification of the candidate training models using verification data to obtain the FPGA resource model comprises:
inputting the verification data into the candidate training model to obtain a plurality of output results;
obtaining the average absolute error corresponding to the candidate training model according to the output results;
and comparing all the average absolute errors to obtain minimum target verification data, wherein the candidate training model corresponding to the minimum target verification data is an FPGA resource model.
7. The logic resource assessment method according to claim 1, wherein the RTL description-related training features are obtained by feature extraction through RTL description.
8. The logic resource evaluation method according to claim 1, wherein the set of usage data training lists of resources is obtained by routing results.
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