CN113779499A - Fast Fourier algorithm optimization method and system based on high-level comprehensive tool - Google Patents
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Abstract
The invention provides a fast Fourier algorithm optimization method and a system based on a high-level comprehensive tool for overcoming the defect of high resource consumption of an FFT algorithm implemented on an FPGA, wherein the method comprises the following steps: constructing a fast Fourier algorithm model according to a preset target function, wherein the fast Fourier algorithm model comprises a twiddle factor; optimally designing a twiddle factor in the fast Fourier algorithm model; converting the fast Fourier algorithm model into a fast Fourier algorithm model based on a hardware description language by adopting a high-level comprehensive tool, and burning the fast Fourier algorithm model into an FPGA chip for simulation; and judging the resource consumption of the FPGA chip, and finishing the optimization of the fast Fourier algorithm when the resource consumption is less than a preset threshold value. According to the invention, the twiddle factors in the fast Fourier algorithm model are optimally designed and then are recorded on the FPGA chip, so that the resource consumption on the FPGA can be effectively reduced.
Description
Technical Field
The invention relates to the field of digital data processing, in particular to a fast Fourier algorithm optimization method and system based on a high-level comprehensive tool.
Background
Fast Fourier Transform (FFT) is an efficient algorithm for Discrete Fourier Transform (DFT), and Fourier Transform is one of the most basic methods in time-frequency domain Transform analysis. In digital processing applications, discrete fourier transforms are the basis of many digital signal processing methods. An FPGA (Field-Programmable Gate Array), which is a Field-Programmable Gate Array, belongs to a Programmable device. At present, a low-level hardware description language (Verilog or VHDL) is mainly used for circuit design and then is burned to an FPGA for testing, so that the rapid molding of a product is realized.
The traditional design of the FFT algorithm based on Register Transfer Level (RTL) codes is mainly adopted in the FFT algorithm implemented on the FPGA at present, the difficulty is high, and particularly, a large amount of floating point operation is involved, so that the resource consumption of the FPGA is high.
Disclosure of Invention
The invention provides a fast Fourier algorithm optimization method based on a high-level comprehensive tool and a fast Fourier algorithm optimization system based on the high-level comprehensive tool, aiming at overcoming the defect that the FFT algorithm applied to FPGA in the prior art has high resource consumption.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a fast Fourier algorithm optimization method based on a high-level comprehensive tool comprises the following steps:
s1, constructing a fast Fourier algorithm model according to a preset target function, wherein the fast Fourier algorithm model comprises a twiddle factor;
s2, optimally designing a twiddle factor in the fast Fourier algorithm model;
s3, converting the fast Fourier algorithm model into a fast Fourier algorithm model based on a hardware description language by adopting a high-level comprehensive tool, and burning the model into an FPGA chip for simulation;
s4, judging the resource consumption of the FPGA chip: when the resource consumption is greater than or equal to a preset threshold value, skipping to execute the step S2; and when the resource consumption is less than a preset threshold value, finishing the optimization of the fast Fourier algorithm.
Preferably, the twiddle factor is set in the fast fourier algorithm model in the form of euler formula, and the expression formula is as follows:
in the formula, N represents the number of sampling points set by the fast fourier algorithm model.
Preferably, in the step S2, the step of optimally designing the twiddle factors in the fast fourier algorithm model includes: and pre-calculating a cosine value item and a sine value item in the twiddle factors.
Preferably, the step S2 further includes the following steps: and constructing an algorithm analysis model, inputting the optimally designed fast Fourier algorithm model into the algorithm detection model for feasibility analysis, executing the step S3 when an output analysis result is feasible, and otherwise, executing the step S1.
Preferably, in the step S4, the resource consumption includes a look-up table consumption, a trigger consumption, a digital signal processing amount, and a random access memory consumption.
Furthermore, the invention also provides a high-level comprehensive tool-based fast Fourier algorithm optimization system, which is applied to the high-level comprehensive tool-based fast Fourier algorithm optimization method provided by any technical scheme. Which comprises the following steps:
the algorithm model construction module is used for constructing a fast Fourier algorithm model according to a preset target function;
the optimization module is used for optimally designing the twiddle factors in the fast Fourier algorithm model;
the model conversion module is used for converting the fast Fourier algorithm model into a fast Fourier algorithm model based on a hardware description language by adopting a high-level comprehensive tool;
the FPGA chip is used for executing the fast Fourier algorithm model;
and the judging module is used for judging the resource consumption of the FPGA chip.
As a preferred scheme, the optimization module includes a cosine value item calculation unit and a sine value item calculation unit, which are respectively used for pre-calculating a cosine value item and a sine value item in a rotation factor in the fast fourier algorithm model.
As a preferred scheme, the judging module comprises a lookup table consumption detecting unit, a trigger consumption detecting unit, a digital signal processing amount detecting unit, a random access memory consumption detecting unit and a judging unit, wherein the lookup table consumption detecting unit, the trigger consumption detecting unit, the digital signal processing amount detecting unit and the random access memory consumption detecting unit are respectively used for detecting lookup table consumption, trigger consumption, digital signal processing amount and random access memory consumption, and respectively input into the judging unit; and the judging unit judges the consumption of the lookup table, the consumption of the trigger, the digital signal processing capacity and the consumption of the random access memory which are obtained by detection according to a preset threshold value, and returns a working signal to the optimizing module when the resource consumption is greater than or equal to the preset threshold value.
As a preferred scheme, the system further comprises an algorithm analysis module, wherein the input end of the algorithm analysis module is connected with the output end of the optimization module; the algorithm analysis module receives the optimized fast Fourier algorithm model and then conducts feasibility analysis, and when the output analysis result is feasible, a working signal is sent to the model conversion module; and when the output analysis result is not feasible, sending a working signal to the algorithm model building module.
Preferably, the FPGA chip adopts an XC7Z020-1CLG484 type chip of Xilinx.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that: according to the method, the twiddle factors in the fast Fourier algorithm model are optimally designed and then are recorded on the FPGA chip, so that the resource consumption of the FFT algorithm on the FPGA can be effectively reduced; the invention further judges whether the fast Fourier algorithm model needs to be further optimized or not according to the resource consumption condition of the FPGA chip, thereby ensuring the optimization effect of the fast Fourier algorithm model.
Drawings
Fig. 1 is a flowchart of a fast fourier algorithm optimization method based on a high-level synthesis tool according to embodiment 1.
FIG. 2 shows the result of the Visual Studio operation of the FFT model before optimization.
FIG. 3 shows the result of the optimized FFT algorithm model in Visual Studio operation.
FIG. 4 is the result of the fast Fourier algorithm model before optimization in Xilinx Vivado.
FIG. 5 is the operation result of the optimized fast Fourier algorithm model in Xilinx Vivado.
FIG. 6 is an architecture diagram of the high-level synthesis tool-based fast Fourier algorithm optimization system of example 2.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the patent; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
Example 1
The embodiment provides a fast fourier algorithm optimization method based on a high-level synthesis tool, and as shown in fig. 1, the method is a flowchart of the fast fourier algorithm optimization method of the embodiment.
The fast Fourier algorithm optimization method based on the high-level comprehensive tool provided by the embodiment comprises the following steps:
s1, constructing a fast Fourier algorithm model according to the preset target function, wherein the fast Fourier algorithm model comprises a twiddle factor.
In this embodiment, an expected fast fourier algorithm function is analyzed, and then a fast fourier algorithm model is constructed using a high-level language to implement a preset target function. The twiddle factor in the embodiment is set in the fast fourier algorithm model in the form of an euler formula, and the expression formula is as follows:
in the formula, N represents the number of sampling points set by the fast fourier algorithm model.
And S2, optimally designing the twiddle factors in the fast Fourier algorithm model.
In this embodiment, the step of optimally designing the twiddle factors in the fast fourier algorithm model includes: and pre-calculating a cosine value item and a sine value item in the twiddle factors.
Specifically, the embodiment combines with euler formula eixAnd (4) calculating a cosine value item and a sine value item in the twiddle factors in advance, and inputting the corresponding twiddle factors serving as array elements into the fast Fourier algorithm model to obtain the optimized fast Fourier algorithm model.
In a specific implementation, MATLAB may be used to pre-compute cosine and sine values of the rotation factor.
Further, in order to verify the feasibility of the currently constructed fast fourier algorithm model and ensure that the fast fourier algorithm model can accurately realize the preset target function, the following steps are optionally performed:
and constructing an algorithm analysis model, inputting the optimally designed fast Fourier algorithm model into the algorithm detection model for feasibility analysis, executing the step S3 when an output analysis result is feasible, and otherwise, executing the step S1.
The algorithm analysis model is used for verifying whether the currently constructed fast Fourier algorithm model can realize a preset target function. For example, the visual studio is used to verify the function of the fast Fourier algorithm model constructed in the high-level language, and when the simulation effect is the same as the preset target function, the analysis result is output as feasible.
And S3, converting the fast Fourier algorithm model into a fast Fourier algorithm model based on a hardware description language by adopting a high-level comprehensive tool, and burning the fast Fourier algorithm model into an FPGA chip for simulation.
In this embodiment, a high-level synthesis tool is used to convert the fast fourier algorithm model into a fast fourier algorithm model based on a hardware description language, where the hardware description language includes RTL, Verilog, or VHDL code.
S4, judging the resource consumption of the FPGA chip: when the resource consumption is greater than or equal to a preset threshold value, skipping to execute the step S2; and when the resource consumption is less than a preset threshold value, finishing the optimization of the fast Fourier algorithm.
In this embodiment, the resource consumption includes a lookup table consumption, a trigger consumption, a digital signal processing amount, and a random access memory consumption.
In the specific implementation process, the model of the FPGA used is xc7z020clg484-1 of Xilinx. As shown in fig. 2 and 3, the results of the operations of the fast fourier algorithm models before and after optimization on Visual Studio are respectively obtained.
It can be known from the figure that, in the case that certain errors are allowed in the fast fourier algorithm models before and after the optimization is performed, the results of the two models are the same, the small error is the value of pi, that is, the fast fourier algorithm models before and after the optimization can both realize the preset target function, and the optimization operation does not affect the function of the fast fourier algorithm model.
And respectively converting the fast Fourier algorithm model obtained in the step S1 and the optimized fast Fourier algorithm model in the step S2 into RTL code representation by adopting a high-level synthesis tool, and logically synthesizing and comparing the fast Fourier algorithm models before and after optimization represented by the RTL code by utilizing Xilinx Vivado. As shown in fig. 4 and 5, the results of the fast fourier algorithm model before and after optimization and expressed in RTL code in Xilinx Vivado are shown respectively.
It can be known from the figure that, compared with the fast fourier algorithm model converted into the RTL code, the fast fourier algorithm model constructed in the high-level language before optimization has the same result under the condition of allowing a certain error, and the slight error also lies in the value of pi, and compared with the fast fourier algorithm model converted into the RTL code, the fast fourier algorithm model constructed in the high-level language after optimization has the same operation result. Therefore, the operation result after the fast fourier algorithm optimization of the embodiment is controllable and accurate.
Further, the resource consumption of the FPGA before and after the optimization is compared, and as shown in table 1 below, the resource consumption of the fast fourier algorithm model before and after the optimization on the FPGA chip is respectively used.
Table 1 resource consumption of fast Fourier algorithm models before and after optimization for FPGA chips
| FF | LUT | BRAMs | URAM | DSP | |
| Before optimization | 5437 | 6709 | 4.50 | 0 | 112 |
| After optimization | 1520 | 2005 | 5.50 | 0 | 14 |
As can be seen from the above Table, the LUT (Look-Up-Table) consumption, FF (flip flop) consumption, and DSP (Digital Signal processing) consumption that are comprehensively consumed after algorithm optimization are far less than those before optimization. Only the BRAMs (Block RAM, Block random access memory) consume a little more, and because BRAMs are on-chip SRAM, the reason for the consumption increase is to store the twiddle factor required by the FFT algorithm, which is equivalent to the consumption of a little BRAMs, and simultaneously, the consumption of LUT, FF and DSP resources is greatly reduced. In addition, the time sequence of the fast Fourier algorithm is not affected by the fast Fourier algorithm optimization method provided by the embodiment.
In the fast fourier algorithm optimization method provided by this embodiment, resource consumption of the FFT algorithm on the FPGA is reduced by optimally designing the twiddle factors in the fast fourier algorithm model. In addition, in this embodiment, errors caused by the optimization design are also considered, which may cause an unsatisfactory optimization effect actually generated by the optimized fast fourier algorithm model, and whether the fast fourier algorithm model needs to be further optimized is further determined by the resource consumption condition of the FPGA chip, so that the optimization effect of the fast fourier algorithm model is ensured. Furthermore, in the embodiment, a fast fourier algorithm model is constructed in a high-level language, and after the algorithm function is determined through feasibility detection, the algorithm function is recorded to the FPGA chip, so that the correctness of the algorithm can be effectively ensured, and the resource loss is reduced.
Example 2
The embodiment provides a fast fourier algorithm optimization system based on a high-level comprehensive tool, which is applied to the fast fourier algorithm optimization method provided in embodiment 1. Fig. 6 is a diagram illustrating the architecture of the high-level synthesis tool-based fast fourier algorithm optimization system according to this embodiment.
The fast fourier algorithm optimization system based on the high-level synthesis tool provided by this embodiment includes:
the algorithm model building module 1 is used for building a fast Fourier algorithm model according to a preset target function;
the optimization module 2 is used for optimally designing the twiddle factors in the fast Fourier algorithm model;
the model conversion module 3 is used for converting the fast Fourier algorithm model into a fast Fourier algorithm model based on a hardware description language by adopting a high-level comprehensive tool;
the FPGA chip 4 is used for executing the fast Fourier algorithm model;
and the judging module 5 is used for judging the resource consumption of the FPGA chip 4.
In this embodiment, the optimization module 2 includes a cosine value item calculation unit and a sine value item calculation unit, which are respectively used for performing pre-calculation on a cosine value item and a sine value item in a rotation factor in the fast fourier algorithm model.
In this embodiment, the determining module 5 includes a lookup table consumption detecting unit, a trigger consumption detecting unit, a digital signal processing amount detecting unit, a random access memory consumption detecting unit, and a determining unit, where the lookup table consumption detecting unit, the trigger consumption detecting unit, the digital signal processing amount detecting unit, and the random access memory consumption detecting unit are respectively configured to detect a lookup table consumption, a trigger consumption, a digital signal processing amount, and a random access memory consumption, and respectively input the lookup table consumption, the trigger consumption, the digital signal processing amount, and the random access memory consumption into the determining unit; the judging unit judges the consumption of the lookup table, the consumption of the trigger, the digital signal processing capacity and the consumption of the random access memory which are obtained by detection according to a preset threshold value, and returns a working signal to the optimizing module 2 when the resource consumption is larger than or equal to the preset threshold value.
The FPGA chip 4 in the embodiment adopts an XC7Z020-1CLG484 type chip of Xilinx.
Further, the fast fourier algorithm optimization system of this embodiment further includes an algorithm analysis module, an input end of the algorithm analysis module is connected to an output end of the optimization module 2; the algorithm analysis module receives the optimized fast Fourier algorithm model and then conducts feasibility analysis, and when the output analysis result is feasible, a working signal is sent to the model conversion module 3; and when the output analysis result is not feasible, sending a working signal to the algorithm model building module 1.
In the specific implementation process, firstly, the algorithm model building module 1 builds a fast Fourier algorithm model by using a high-level language according to a preset target function, and the algorithm model building module 1 transmits the built fast Fourier algorithm model to the optimization module 2;
the optimization module 2 performs optimization design on the received twiddle factors in the fast Fourier algorithm model, and specifically, the optimization module 2 performs pre-calculation on cosine value items and sine value items in the twiddle factors in the fast Fourier algorithm model by respectively adopting a cosine value item calculation unit and a sine value item calculation unit to obtain an optimized fast Fourier algorithm model, and then transmits the optimized fast Fourier algorithm model to an algorithm analysis module for feasibility analysis;
the algorithm analysis module performs feasibility analysis on the received optimized fast Fourier algorithm model, and when the output analysis result is feasible, the optimized fast Fourier algorithm model is sent to the model conversion module 3;
the model conversion module 3 converts the optimized fast Fourier algorithm model into a fast Fourier algorithm model based on a hardware description language by adopting a high-level comprehensive tool, and then burns the model into the FPGA chip 4, and the FPGA chip 4 executes the optimized fast Fourier algorithm model to realize simulation;
after the FPGA chip 4 finishes the simulation of the fast Fourier algorithm model, the judging module 5 judges the resource consumption of the FPGA chip 4, specifically, a lookup table consumption detecting unit, a trigger consumption detecting unit, a digital signal processing quantity detecting unit and a random memory consumption detecting unit are adopted to respectively detect the lookup table consumption, the trigger consumption, the digital signal processing quantity and the random memory consumption of the FPGA chip 4, then the lookup table consumption, the trigger consumption, the digital signal processing quantity and the random memory consumption are transmitted to a judging unit for logic judgment, when the resource consumption is more than or equal to a preset threshold value, a working signal is returned to the optimizing module 2, and the optimizing module 2 carries out optimization design on the fast Fourier algorithm model again; and when the resource consumption is less than a preset threshold value, the optimization of the fast Fourier algorithm is finished.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A fast Fourier algorithm optimization method based on a high-level comprehensive tool is characterized by comprising the following steps:
s1, constructing a fast Fourier algorithm model according to a preset target function, wherein the fast Fourier algorithm model comprises a twiddle factor;
s2, optimally designing a twiddle factor in the fast Fourier algorithm model;
s3, converting the fast Fourier algorithm model into a fast Fourier algorithm model based on a hardware description language by adopting a high-level comprehensive tool, and burning the model into an FPGA chip for simulation;
s4, judging the resource consumption of the FPGA chip: when the resource consumption is greater than or equal to a preset threshold value, skipping to execute the step S2; and when the resource consumption is less than a preset threshold value, finishing the optimization of the fast Fourier algorithm.
2. The method for optimizing a fast fourier algorithm based on a high-level synthesis tool according to claim 1, wherein the twiddle factor is set in the fast fourier algorithm model in the form of euler formula, and the expression formula is as follows:
in the formula, N represents the number of sampling points set by the fast fourier algorithm model.
3. The method for optimizing a fast fourier algorithm based on a high-level synthesis tool according to claim 2, wherein in the step S2, the step of optimally designing the twiddle factors in the fast fourier algorithm model comprises: and pre-calculating a cosine value item and a sine value item in the twiddle factors.
4. The method for optimizing a fast fourier algorithm based on a high-level synthesis tool according to claim 1, wherein the step of S2 further comprises the steps of: and constructing an algorithm analysis model, inputting the optimally designed fast Fourier algorithm model into the algorithm detection model for feasibility analysis, executing the step S3 when an output analysis result is feasible, and otherwise, executing the step S1.
5. The high-level synthesis tool-based fast Fourier algorithm optimization method according to any one of claims 1 to 4, wherein in the step S4, the resource consumption comprises a look-up table consumption, a trigger consumption, a digital signal processing amount and a random access memory consumption.
6. A fast Fourier algorithm optimization system based on a high-level synthesis tool is characterized by comprising the following steps:
the algorithm model construction module is used for constructing a fast Fourier algorithm model according to a preset target function;
the optimization module is used for optimally designing the twiddle factors in the fast Fourier algorithm model;
the model conversion module is used for converting the fast Fourier algorithm model into a fast Fourier algorithm model based on a hardware description language by adopting a high-level comprehensive tool;
the FPGA chip is used for executing the fast Fourier algorithm model;
and the judging module is used for judging the resource consumption of the FPGA chip.
7. The high-level synthesis tool-based fast Fourier algorithm optimization system of claim 6, wherein the optimization module comprises a cosine value item calculation unit and a sine value item calculation unit for pre-calculating a cosine value item and a sine value item respectively in a rotation factor in the fast Fourier algorithm model.
8. The high-level synthesis tool-based fast Fourier algorithm optimization system according to claim 6, wherein the discrimination module comprises a look-up table consumption detection unit, a trigger consumption detection unit, a digital signal processing amount detection unit, a random access memory consumption detection unit, and a judgment unit, wherein the look-up table consumption detection unit, the trigger consumption detection unit, the digital signal processing amount detection unit, and the random access memory consumption detection unit are respectively used for detecting look-up table consumption, trigger consumption, digital signal processing amount, and random access memory consumption, and respectively input into the judgment unit; and the judging unit judges the consumption of the lookup table, the consumption of the trigger, the digital signal processing capacity and the consumption of the random access memory which are obtained by detection according to a preset threshold value, and returns a working signal to the optimizing module when the resource consumption is greater than or equal to the preset threshold value.
9. The high-level synthesis tool based fast Fourier algorithm optimization system of claim 6, further comprising an algorithm analysis module, wherein an input of the algorithm analysis module is connected to an output of the optimization module; the algorithm analysis module receives the optimized fast Fourier algorithm model and then conducts feasibility analysis, and when the output analysis result is feasible, a working signal is sent to the model conversion module; and when the output analysis result is not feasible, sending a working signal to the algorithm model building module.
10. The high-level synthesis tool-based fast Fourier algorithm optimization system of claim 6, wherein the FPGA chip is Xilinx XC7Z020-1CLG484 model chip.
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