CN112216609B - Method for reducing wafer warpage and wafer bonding method - Google Patents
Method for reducing wafer warpage and wafer bonding method Download PDFInfo
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- CN112216609B CN112216609B CN202011001472.0A CN202011001472A CN112216609B CN 112216609 B CN112216609 B CN 112216609B CN 202011001472 A CN202011001472 A CN 202011001472A CN 112216609 B CN112216609 B CN 112216609B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/81048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
Abstract
The invention provides a method for reducing wafer warpage and a wafer bonding method. For example, the wafer is annealed in one direction, or annealed at different annealing temperatures set in different directions. By the different annealing strategies, the stress of the wafer in different directions is adjusted, the warping degree of the wafer in different directions is compensated, the shape of the wafer tends to be flat, and the requirements of processing and devices are finally met. In addition, the method can be realized by APC, can be realized by only adjusting the annealing strategy, does not need to add extra steps or processing time, can realize mass production, and is beneficial to reducing the production of finished products.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a method for reducing wafer warpage and a wafer bonding method.
Background
In the fabrication of semiconductor devices, many wafer processes and film deposition processes are involved, and these films are usually layers of different materials, such as various materials including nitride, oxide, metal, polysilicon, etc. The film layers of different materials all have the property of stretching and shrinking. Deposition of layers or other processes in the manufacture of semiconductor devices is often accompanied by thermal processes, after which layers of different materials often exhibit different stresses, some exhibiting tensile stress and some exhibiting compressive stress. These different stress manifestations cause the wafer to assume different curved or warped shapes. In addition, due to the layout design of the device formed by the wafer, the wafer can generate different curvatures in different directions, so that the wafer is correspondingly deformed. In severe cases, the wafer may exhibit a disk or saddle shape with a greater degree of curvature.
Due to the limitation of the semiconductor processing machine, if the wafer is bent or warped too much or the difference in warpage in different directions will cause the limitation of wafer processing or even make the wafer unable to be processed on the same machine, thereby increasing the device manufacturing cost.
It is common to deposit a dielectric film on the top or back of the wafer, and anneal the dielectric film at a high temperature to neutralize or offset the stress of the wafer. However, since the dielectric layer is uniformly deposited, the change of stress in each direction is the same, and the requirement of adjusting the stress in different directions cannot be satisfied.
In view of the above disadvantages, it is necessary to provide a technique for adjusting the stress in different directions of the wafer so that the wafer can meet the processing requirements.
Disclosure of Invention
In view of the foregoing disadvantages and drawbacks of the prior art, an object of the present invention is to provide a method for reducing wafer warpage and a wafer bonding method, which determine warpage of a wafer in different directions by measuring a warpage value, determine an annealing strategy, and anneal the wafer in different directions by using different annealing strategies, so as to adjust stresses of the wafer in different directions and compensate for curvatures of the wafer in different directions, so that the wafer meets processing requirements.
To achieve the above and other related objects, the present invention provides a method for reducing wafer warpage, comprising the steps of:
providing a wafer with warping degree difference in different directions;
determining the warping degrees of the wafer in different directions;
and annealing the wafer along different directions or in different areas of the wafer by adopting different annealing strategies according to the warping values in different directions.
Optionally, annealing the wafer along different directions or in different regions of the wafer by using different annealing strategies, further comprising the following steps:
and setting different annealing temperatures in different directions according to the warping degrees in different directions for annealing.
Optionally, annealing the wafer along different directions or in different regions of the wafer by using different annealing strategies, further comprising the following steps:
and selecting the region to be annealed according to the warping degrees in different directions.
Optionally, annealing is performed in selected regions where annealing is required, and the remaining regions are not annealed.
Optionally, the different directions include directions perpendicular to each other in a radial direction of the wafer.
Optionally, the wafer is spike annealed.
Optionally, the wafer includes a substrate, and a plurality of film layers formed on the substrate.
Another embodiment of the present invention further provides a wafer bonding method, including the steps of:
providing a wafer to be bonded;
determining the warping degrees of the wafer in different directions;
and annealing the wafer along different directions or in different areas of the wafer by adopting different annealing strategies according to the warping values in different directions.
Optionally, setting different annealing strategies to anneal the wafer in different directions, further comprising:
and setting different annealing temperatures in different directions according to the warping degrees in different directions for annealing.
Optionally, setting different annealing strategies to anneal the wafer in different directions, further comprising:
and selecting the region to be annealed according to the warping degrees in different directions.
Optionally, annealing is performed in selected regions where annealing is desired, and the remaining regions are not annealed.
Optionally, the different directions include directions perpendicular to each other in a radial direction of the wafer.
Optionally, the wafer is spike annealed.
Optionally, the wafer includes a substrate, a semiconductor device formed on the substrate, and a bonding layer formed over the semiconductor device.
Optionally, the wafer bonding method further includes:
etching the bonding layer to form a bonding pad for wafer bonding;
and bonding different wafers to be bonded through the bonding pad.
As described above, the method for reducing wafer warpage and the wafer bonding method provided by the present invention have at least the following beneficial effects:
the method comprises the steps of determining the warping degrees of the wafers in different directions for the wafers with different warping degrees in different directions; and setting different annealing strategies to anneal the wafer in different directions according to the warpage values in different directions. For example, the wafer is annealed in one direction, or annealed at different annealing temperatures set in different directions. By the different annealing strategies, the stress of the wafer in different directions is adjusted, the warping degree of the wafer in different directions is compensated, the shape of the wafer tends to be flat, and the requirements of processing and devices are finally met.
In addition, the method can be realized by Advanced Process Control (APC), can be realized by only adjusting the annealing strategy, does not need to add extra steps or processing time, can realize mass production, and is favorable for reducing the production of finished products.
Drawings
Fig. 1 and fig. 2 are schematic views showing a warp shape of a wafer due to uneven stress distribution.
Fig. 3 is a schematic view of the wafer shown in fig. 1 in the thickness direction.
Fig. 4 is a schematic diagram illustrating a dielectric layer film deposited on the back side of a wafer for improving the warpage of the wafer shown in fig. 1 in the prior art.
Fig. 5 is a schematic view showing a warp shape of the wafer shown in fig. 4.
Fig. 6 is a flowchart illustrating a method for reducing wafer warpage according to an embodiment of the present invention.
Fig. 7 is a schematic diagram illustrating annealing of the wafer shown in fig. 1.
Fig. 8 is a schematic diagram illustrating annealing of the wafer shown in fig. 2.
Fig. 9 is a schematic view showing the shape of the wafer after the annealing shown in fig. 8.
Fig. 10 is a schematic flowchart illustrating a wafer bonding method according to a second embodiment of the invention.
Fig. 11 is a schematic view of a device structure of a wafer to be bonded.
Fig. 12 is a schematic view showing a warp shape of the wafer to be bonded shown in fig. 11.
Fig. 13 is a schematic view illustrating annealing of the wafer shown in fig. 12.
Fig. 14 is a schematic diagram showing the shape of the wafer after the bonding pad etching is performed on the wafer shown in fig. 13.
Detailed Description
The following embodiments of the present invention are provided by specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure of the present invention. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity, position relationship and proportion of the components in actual implementation can be changed freely on the premise of implementing the technical solution of the present invention, and the layout form of the components may be more complicated.
Example one
In the fabrication of semiconductor devices, numerous substrate processes, as well as film deposition and processing procedures, are designed, which are largely accompanied by thermal processes. For example, for a memory, along with the demand for smaller memory size and larger storage capacity, a 3D NAND memory is receiving more and more attention. In the 3D NAND manufacturing process, deposition, etching, annealing and other heat tracing processes of different film layers are accompanied. Different films have different coefficients of thermal expansion and have expansion and contraction characteristics, so that different films behave differently in the same thermal process. Some of the films exhibit tensile stress and some of the films exhibit compressive stress, eventually resulting in varying degrees of wafer bow or warpage. In addition, due to the layout design of devices above the wafer, the warpage values of the wafer in different directions have great difference, and only the wafer generates corresponding deformation. As shown in fig. 1 and 2, when the stresses of the wafer in all directions are matched, the wafer will bend towards the same direction (towards the front side or the back side of the wafer), so that the wafer takes the shape of a disk or a bowl as shown in fig. 1. As shown in fig. 1, the wafers 100 are all curved toward the back side of the wafer in directions X, Y that are perpendicular to each other in the radial direction, and the degree of curvature is almost the same, assuming a disk shape. If the stresses in the wafer are not matched in all directions, resulting in different wafer bending directions and different degrees of bending, the wafer may take on the saddle shape shown in fig. 2. As shown in fig. 2, the wafer 200 is curved toward the front side of the wafer in the radial direction X, curved toward the back side of the wafer in the radial direction Y perpendicular to the X direction, and curved in the direction X, Y to the same extent, and the wafer is saddle-shaped.
In the prior art, in order to balance the stress distribution of a wafer, a dielectric layer film is usually deposited on the front side of the wafer or the back side of the wafer, and then the stress of the wafer is balanced through high temperature annealing. Fig. 1 shows a view of the wafer 100 along the thickness direction of the wafer. Depositing a dielectric layer film 101 on the back surface of the wafer, and then annealing the wafer, wherein the stress in each direction of the wafer is balanced and compensated, and the wafer bending is relieved, as shown in fig. 5, the bending is reduced. However, since the deposited dielectric layer film 101 is uniformly deposited, the stress change of the dielectric layer film 101 in each direction after annealing is the same, for example, in the saddle-shaped wafer shown in fig. 2, even though the dielectric layer film is deposited and annealed, the processing requirement is difficult to meet, and a desired product cannot be obtained.
In this regard, the present embodiment provides a method for reducing wafer warpage, as shown in fig. 6, the method includes the following steps:
step S001: providing a wafer with warping degree difference in different directions;
in this embodiment, the material of the wafer may be single crystal Silicon, Germanium (Ge), Silicon Germanium (SiGe), Silicon-on-Insulator (SOI), Germanium-on-Insulator (GOI), or the like. In this embodiment, a single crystal silicon wafer is taken as an example. The wafer may also include various film layers deposited over the wafer. Such as sacrificial layers and insulating layers used to form a 3D NAND stack structure. The wafers provided in this embodiment include the wafer 100 having a disk or bowl shape as shown in fig. 1, and the wafer 200 having a saddle shape as shown in fig. 2.
Step S002: determining the warping degrees of the wafer in different directions;
with respect to the provided wafer, the heights of a plurality of points of the wafer are measured in different directions, respectively, by a flatness tester, thereby measuring the warp of the wafer in different directions, preferably, in two directions perpendicular to each other in a radial direction of the wafer. As shown by warpage in the direction X, Y in fig. 1 and 2. The warp measurement determines the warp direction of the wafer and the difference in warp in different directions, thereby determining whether the wafer belongs to the disk or bowl type wafer shown in fig. 1 or the saddle type wafer shown in fig. 2.
Step S003: and annealing the wafer along different directions or in different areas of the wafer by adopting different annealing strategies according to the warping values in different directions.
And setting different annealing strategies according to the bending type of the wafer determined in the step S002, and annealing the wafer. In this embodiment, the wafer is annealed by using a spike annealing (LSA). The peak temperature and the peak temperature residence time of the temperature curve of the spike annealing are convenient to Control, the customization is high, and the Control can be realized through APC (Advanced Process Control). Compared with the traditional annealing mode of the concentric heating tube, the line-by-line scanning type annealing can be realized, so that different temperature zones can be designed, different areas of the wafer can be improved by different stresses, and the controllable degree is high and more accurate. Meanwhile, the spike annealing does not cause damage or harm to other regions during annealing. For example, LSA has been widely used after the 40nm node, and during the annealing process, the laser can act on the device surface for a short time without causing damage to the device components that are not high temperature resistant (such as NiSix).
In a preferred embodiment of the present invention, for the wafer 100 in the disk shape shown in fig. 1, as shown in fig. 7, the spike annealing is performed at a first temperature 110 in the peripheral region of the wafer with a larger warpage, and the spike annealing is performed at a second temperature 120 in the region close to the center of the wafer with a smaller warpage. The first temperature 110 is different from the second temperature 120, for example, the first temperature 110 is about the second temperature 120, so that the wafer has an annealing temperature difference between the peripheral region and the middle region, and thus the stress compensation effect generated in different regions is different. Finally, the stress of different areas is adjusted, so that the wafer is converged into a disc shape which tends to be in a plane shape or is slightly bent. After the annealing process, the warping degree of the wafer is obviously reduced, so that the flatness of the wafer meets the requirement of a processing machine.
In another preferred embodiment of this embodiment, for the saddle-shaped wafer shown in fig. 2, since the wafer is bent in different directions X, Y, the degree of bending may be different, so that if the annealing strategy shown in fig. 7 is adopted to perform annealing, the improvement of the wafer shape cannot be achieved. To this end, in the preferred embodiment, wafers are annealed in the X, Y direction using different annealing strategies tailored to the X, Y direction in which the wafers exhibit different bend directions and degrees of bending, respectively. In the preferred embodiment, the Y direction is spike annealed as required by conventional processing of wafers or semiconductor devices, and the X direction is spike annealed line by line along a third temperature 201, as shown in fig. 8. For example, for a 40nm process, annealing is performed at a conventional temperature of about 850 ℃ in the Y direction, while a third temperature is adjusted in the X direction to be lower than the annealing temperature in the Y direction, e.g., 20 ℃ lower than the temperature in the Y direction, for line-by-line spike annealing. Annealing the wafer 200 in the X, Y direction at different annealing temperatures with temperature differences can effectively compensate the stress of the wafer in the X, Y direction, and improve the warpage difference of the wafer in the X, Y direction, so that the wafer 200 finally takes a planar shape or a disk shape with a small warpage degree and a consistent warpage direction in the X, Y direction as shown in fig. 9. The annealed wafer 200 can meet the requirements of subsequent processing and processing machines.
As described above, in the method of this embodiment, for the warped wafer, annealing is performed in different regions or in different directions by using different annealing strategies, and an annealing temperature difference is generated in different directions or in different regions. Different annealing temperatures can achieve different stress compensation or improvement effects, so that the bending or warping of the wafer can be effectively improved, and the wafer finally tends to be planar or disc-shaped with the same bending direction in all directions and the bending degree is obviously reduced. The wafer after the annealing treatment can meet the requirements of a processing machine. The method can be realized by adjusting the annealing strategy without adding extra steps or manufacturing procedures, is easy to realize mass production and does not increase the cost.
Example two
The present embodiment provides a wafer bonding method, as shown in fig. 10, the method includes the following steps:
step S101: providing a wafer to be bonded;
in the present embodiment, referring to fig. 11 and 12, a wafer 300 is provided that includes a substrate 301 and a semiconductor device formed over the substrate 301, a bonding layer 306 formed over the semiconductor device. In the present embodiment, the substrate 301 may include a Silicon, Germanium (Ge), Silicon Germanium (SiGe) substrate, SOI (Silicon-on-Insulator) or GOI (Germanium-on-Insulator) or the like. The semiconductor device may be a 3D NAND memory structure formed over the substrate 301, or may be a CMOS or other device. In this embodiment, the substrate 301 is a silicon substrate for example, and the semiconductor device is described by taking a 3D NAND memory structure as an example.
In a preferred embodiment of the present embodiment, as shown in fig. 11, the substrate 301 is a silicon substrate, and the semiconductor device formed on the silicon substrate 301 includes a stacked structure 302, a memory cell 303 formed through the stacked structure 302, a common source 304, and the like. As shown in fig. 11, the stacked structure 302 includes an insulating layer 3021 and a word line layer 3022 alternately stacked, and the memory cell 303 includes a charge blocking layer, a charge trapping layer, a tunneling layer, a channel layer, and a dielectric layer sequentially formed in a channel hole. A contact layer is also formed between the semiconductor device and the bonding layer 306, the contact layer including contacts 305 respectively contacting the word line layer, the substrate, the channel layer of the memory cell, and the common source, the contacts 305 forming an interconnect structure with the bonding layer. In a semiconductor device, an interconnection structure formed by a contact portion and a bonding layer is generally formed by using a metal material with good electrical conductivity, and the metal material and a semiconductor material forming the semiconductor device have a large difference in thermal expansion coefficient, which causes different degrees of bending or warping of a wafer when the interconnection structure is formed and a pad is formed subsequently.
Step S102: determining the warping degrees of the wafer in different directions;
the warp of the wafer to be bonded in different directions is measured, preferably, the warp in two directions perpendicular to each other in the radial direction of the wafer is measured. The warpage measurement is performed to determine the warpage direction of the wafer and the difference of warpage in different directions, for example, in the preferred embodiment of the present embodiment, it is measured that the wafer 300 has a saddle shape as shown in fig. 12, in which the bending direction is different, even the bending degree is different, in the direction X, Y. In other embodiments, the wafer 300 may take the shape of a disk as shown in FIG. 1. In this embodiment, a warp shape of the wafer 300 shown in fig. 12 is taken as an example for explanation.
Step S103: and according to the warpage values in different directions, annealing the wafer along different directions or in different areas of the wafer by adopting different annealing strategies.
And setting different annealing strategies according to the bending type of the wafer 300 to be bonded, which is determined in the step S102, and annealing the wafer. In this embodiment, the wafer is annealed using spike annealing. The peak temperature and the peak temperature residence time of the temperature curve of the spike annealing are convenient to Control, the customization is high, and the Control can be realized through APC (Advanced Process Control).
For the saddle-shaped wafer shown in fig. 12, since the wafer has different bending directions in the X, Y direction and may have different bending degrees, the wafer is annealed along the X, Y direction respectively by customizing different annealing strategies in the X, Y direction in which the wafer has different bending directions and bending degrees. As shown in fig. 13, in the preferred embodiment, the wafer is spike annealed at a fourth temperature 301 in the X-direction in a line-by-line scan, and at a fifth temperature 320 in the Y-direction. Annealing the wafer 300 at different annealing temperatures with a temperature difference in the X, Y direction can effectively compensate the stress of the wafer in the X, Y direction, and improve the warpage difference of the wafer in the X, Y direction, so that the wafer 300 finally takes the shape of a flat surface or a disk with a small warpage and a uniform warpage direction in the X, Y direction as shown in fig. 14. The wafer 300 after the annealing process can meet the requirements of subsequent processing and the requirements of processing machines.
In this embodiment, after annealing the wafer, etching the bonding layer 306 of the annealed wafer 300 to form a bonding pad for wafer bonding, and bonding different wafers to be bonded through the bonding pad.
As described above, after the annealing treatment, the curvature of the wafer to be bonded can meet the requirements of subsequent etching, bonding and other processes, and the method is easy to realize mass production and does not increase the cost additionally.
As described above, the method for reducing wafer warpage and the wafer bonding method provided by the present invention have at least the following beneficial effects:
the method comprises the steps of determining the warping degrees of the wafers in different directions for the wafers with different warping degrees in different directions; and setting different annealing strategies to anneal the wafer in different directions according to the warpage values in different directions. For example, the wafer is annealed in one direction, or annealed at different annealing temperatures set in different directions. By the different annealing strategies, the stress of the wafer in different directions is adjusted, the warping degree of the wafer in different directions is compensated, the shape of the wafer tends to be flat, and the requirements of processing and devices are finally met.
In addition, the method can be realized by Advanced Process Control (APC), can be realized by only adjusting the annealing strategy, does not need to add extra steps or processing time, can realize mass production, and is favorable for reducing the production of finished products.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (15)
1. A method for reducing wafer warpage, comprising the steps of:
providing a wafer with warping degree difference in different directions;
determining the warping degrees of the wafer in different directions;
according to the warping degrees in different directions, annealing the wafer by adopting different annealing strategies along different directions presenting different bending directions and bending degrees or in areas with different bending degrees of the wafer, carrying out peak annealing on the wafer presenting a disc shape at a first temperature in the peripheral area of the wafer with larger warping degree, and carrying out peak annealing at a second temperature in the area which has smaller warping degree and is close to the center of the wafer, wherein the first temperature is different from the second temperature; for the saddle-shaped wafer, the wafer has different bending directions and different bending degrees in the X, Y direction, and the wafer is annealed at a temperature of about 850 ℃ in the Y direction, and is subjected to line-by-line scanning type spike annealing at a third temperature which is 20 ℃ lower than the annealing temperature in the Y direction in the X direction.
2. A method of reducing wafer warpage as recited in claim 1, wherein the wafer is annealed using different annealing strategies in different directions exhibiting different directions and degrees of curvature, or in regions of the wafer having different degrees of curvature, further comprising the steps of:
and setting different annealing temperatures in different directions according to the warping degrees in different directions for annealing.
3. A method of reducing wafer warpage as recited in claim 1, wherein the wafer is annealed in different directions exhibiting different bending directions and degrees of bending or in regions of the wafer having different degrees of bending using different annealing strategies, further comprising the steps of:
and selecting the region to be annealed according to the warping degrees in different directions.
4. A method for reducing wafer warpage as recited in claim 3, wherein annealing is performed in selected areas where annealing is desired, and the remaining areas are not annealed.
5. A method for reducing wafer warpage as recited in claim 1, wherein the different directions include mutually perpendicular directions along a radial direction of the wafer.
6. A method for reducing wafer warpage as recited in claim 4 or claim 5, wherein the wafer is subjected to a spike anneal.
7. The method for reducing wafer warpage as recited in claim 1, wherein the wafer includes a substrate, a multi-layer film layer formed on the substrate.
8. A wafer bonding method is characterized by comprising the following steps:
providing a wafer to be bonded;
determining the warping degrees of the wafer in different directions;
according to the warping degrees in different directions, annealing the wafer along different directions presenting different bending directions and bending degrees or in different regions of the wafer with different bending degrees by adopting different annealing strategies, carrying out peak annealing on the wafer presenting a disc shape at a first temperature in the peripheral region of the wafer with larger warping degree, and carrying out peak annealing at a second temperature in the region with smaller warping degree and close to the center of the wafer, wherein the first temperature is different from the second temperature; the saddle-shaped wafer is subjected to annealing at a temperature of about 850 ℃ in the Y direction and to line-by-line spike annealing at a third temperature 20 ℃ lower than the annealing temperature in the Y direction, the wafer being subjected to different bending directions and different bending degrees in the X, Y direction.
9. The wafer bonding method of claim 8, wherein the wafer is annealed in different directions exhibiting different bending directions and bending degrees or in regions of the wafer having different bending degrees using different annealing strategies, further comprising the steps of:
and setting different annealing temperatures in different directions according to the warping degrees in different directions for annealing.
10. The wafer bonding method of claim 8, wherein the wafer is annealed in different directions exhibiting different bending directions and bending degrees or in regions of the wafer having different bending degrees using different annealing strategies, further comprising the steps of:
and selecting the region to be annealed according to the warping degrees in different directions.
11. The wafer bonding method according to claim 10, wherein annealing is performed in selected regions where annealing is required, and the remaining regions are not annealed.
12. The wafer bonding method according to claim 8, wherein the different directions include directions perpendicular to each other in a radial direction of the wafer.
13. The wafer bonding method according to claim 11 or 12, characterized in that the wafer is spike annealed.
14. The wafer bonding method according to claim 8, wherein the wafer comprises a substrate, a semiconductor device formed on the substrate, and a bonding layer formed over the semiconductor device.
15. The wafer bonding method of claim 14, further comprising:
etching the bonding layer to form a bonding pad for wafer bonding;
and bonding different wafers to be bonded through the bonding pad.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127288A (en) * | 1996-03-25 | 2000-10-03 | Sumitomo Electric Industries, Ltd. | Method of thermally processing semiconductor wafer |
| KR20040086867A (en) * | 2003-03-22 | 2004-10-13 | 삼성전자주식회사 | Loadlock chamber with device for detecting wafer deformation |
| CN107731667A (en) * | 2017-08-28 | 2018-02-23 | 长江存储科技有限责任公司 | Possess the hybrid bonded method of metal connecting line and hybrid bonded structure |
| CN108649021A (en) * | 2018-07-19 | 2018-10-12 | 长江存储科技有限责任公司 | Silicon wafer warpage adjusts structure and forming method thereof |
| CN110098140A (en) * | 2019-05-16 | 2019-08-06 | 芯盟科技有限公司 | Low-temperature wafer Direct Bonding board and wafer bonding method |
| CN110620040A (en) * | 2019-09-12 | 2019-12-27 | 长江存储科技有限责任公司 | Method for improving process stability in production |
| CN110690113A (en) * | 2019-09-12 | 2020-01-14 | 长江存储科技有限责任公司 | Wafer warping degree adjusting method and equipment |
| CN111383914A (en) * | 2018-12-28 | 2020-07-07 | 中国科学院上海微系统与信息技术研究所 | Adjustment method and post-processing method for warpage of heterogeneous bonding structure |
-
2020
- 2020-09-22 CN CN202011001472.0A patent/CN112216609B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127288A (en) * | 1996-03-25 | 2000-10-03 | Sumitomo Electric Industries, Ltd. | Method of thermally processing semiconductor wafer |
| KR20040086867A (en) * | 2003-03-22 | 2004-10-13 | 삼성전자주식회사 | Loadlock chamber with device for detecting wafer deformation |
| CN107731667A (en) * | 2017-08-28 | 2018-02-23 | 长江存储科技有限责任公司 | Possess the hybrid bonded method of metal connecting line and hybrid bonded structure |
| CN108649021A (en) * | 2018-07-19 | 2018-10-12 | 长江存储科技有限责任公司 | Silicon wafer warpage adjusts structure and forming method thereof |
| CN111383914A (en) * | 2018-12-28 | 2020-07-07 | 中国科学院上海微系统与信息技术研究所 | Adjustment method and post-processing method for warpage of heterogeneous bonding structure |
| CN110098140A (en) * | 2019-05-16 | 2019-08-06 | 芯盟科技有限公司 | Low-temperature wafer Direct Bonding board and wafer bonding method |
| CN110620040A (en) * | 2019-09-12 | 2019-12-27 | 长江存储科技有限责任公司 | Method for improving process stability in production |
| CN110690113A (en) * | 2019-09-12 | 2020-01-14 | 长江存储科技有限责任公司 | Wafer warping degree adjusting method and equipment |
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