CN112214964A - Dynamic layout change method, electronic equipment and computer readable storage medium - Google Patents
Dynamic layout change method, electronic equipment and computer readable storage medium Download PDFInfo
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- G06F30/30—Circuit design
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- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
A method of dynamically changing a layout, comprising the steps of: establishing a standard unit pin access and a rectangle corresponding to the standard unit pin access; sequencing the standard units, finding out a pin access rectangle of each standard unit, and checking a design rule to obtain a state violating the design rule; and constructing a directed weighted graph according to the state of violating the design rule, turning the standard unit and finishing pin wiring of the standard unit. The dynamic change layout method, the electronic equipment and the computer readable storage medium can repair the problematic standard unit layout in the early stage, so that the pins of the standard unit can be smoothly wired and connected, and the design flow is accelerated.
Description
Technical Field
The invention relates to the technical field of physical design of a very large scale integrated circuit, in particular to layout and wiring in a physical design process of the very large scale integrated circuit.
Background
With the advance of ultra-large scale integrated circuits to deep submicron and nanometer, the scale of the integrated circuits is larger and larger, and the system is also larger and more complex, which brings many new problems for Electronic Design Automation (EDA) tools, and especially brings more challenges to the layout and wiring links. Layout and wiring are two important links of the physical design of the integrated circuit, and are a universal method for solving the problem of realizing modern complex physical design. The layout is to determine the position and direction of the standard cell in the design layout, and to give the constraint and optimization goal of the solution. Some standard cells may have fixed positions while others are not. The placement of the variable standard cells plays a decisive role in the quality of the subsequent routing. The placement needs to be completed before routing, and the specific routing conditions in the routing stage cannot be accurately known in the placement stage, so that the placement is evaluated and optimized for the distribution density of standard cells, the distribution density of pins (pins) and the Manhattan paths among the pins so as to reduce the least influence on the routing. However, detailed design rules cannot be considered in the layout, and it may still happen that standard cells placed in the same row are too close together, a router cannot separately signal pins (Pin) in two adjacent standard cells, or the placement of a given standard cell is not an optimal minimum wire length placement. Adding a check of detailed design rules in the layout is an unrealistic problem.
Disclosure of Invention
In order to solve the defects in the prior art, the present invention provides a method for dynamically changing layout, an electronic device, and a computer-readable storage medium, which can perform early repair on the layout of a standard cell with problems, so that pins of the standard cell can be smoothly wired and connected, and the design process is accelerated.
In order to achieve the above object, the present invention provides a method for dynamically changing a layout, comprising the following steps:
establishing a standard unit pin access and a rectangle corresponding to the standard unit pin access;
sequencing the standard units, finding out a pin access rectangle of each standard unit, and checking a design rule to obtain a state violating the design rule;
and constructing a directed weighted graph according to the state of violating the design rule, turning the standard unit and finishing pin wiring of the standard unit.
Further, the step of creating standard cell pin access and its corresponding rectangle further comprises,
defining a rectangle on each standard unit as a pin access point;
respectively creating a rectangle on the layer where the standard unit pin is located and the upper layer;
a rectangle is created on the via layer between the layer where the standard cell pin is located and the previous layer at the intersection of the two rectangles.
Further, the step of sequencing the standard cells, finding out the pin access rectangle of each standard cell, and checking the design rule to obtain the state violating the design rule further includes the step of checking the design rule including finding the rightmost pin of the left standard cell and the leftmost pin of the right standard cell, checking whether all pins and barriers in each rectangle of the left pin and the right standard cell violate the design rule in the corresponding metal layer or through hole layer, and if not, checking whether the design rule violates between each rectangle of the leftmost pin in the right standard cell and all pins and barriers in the left standard cell.
Further, if the design rule is violated, the left standard cell direction is maintained, the right standard cell direction is reversed, and the design rule is checked to determine whether the design rule is violated.
Further, the step of determining whether the design rule is violated further includes, if the design rule is violated, flipping the direction of the left standard cell and the direction of the right standard cell, and performing design rule check to determine whether the design rule is violated.
Further, the step of determining whether the design rule is violated further includes, if the design rule is violated, flipping the left standard cell direction, keeping the right standard cell direction, performing design rule check, and determining whether the design rule is violated.
Further, the step of constructing a directed weighted graph according to the state violating the design rule, turning over the standard cell and completing wiring of the pins of the standard cell also includes the steps of accumulating the weights of the same edge according to the states violating the design rule of the pins and the pins, completing the construction of the directed weighted graph, and finding the shortest path in the weighted graph according to the shortest path algorithm.
Furthermore, the method also comprises the following steps of,
if the rectangle of the pin access point violates the design rule, allocating a preset weight to the corresponding edge;
if the pins per se violate the design rules, distributing preset weight to the corresponding edges;
and if the design rule is not violated, distributing zero weight to the corresponding edge.
To achieve the above object, the present invention further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the steps of the dynamic layout change method as described above when executing the computer program.
To achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed, performs the steps of the dynamically changing layout method as described above.
The dynamic change layout method, the electronic device and the computer readable storage medium of the invention have the following beneficial effects:
1) the problem of standard cell layout is found in the inspection of Pin Access (Pin Access) to the standard cells in the early stage of wiring, so that the incremental layout is avoided from returning to the layout stage, and the physical design process is accelerated.
2) According to the actual situation of the layout or the standard cell spacing appointed by a user, the problem that the wiring cannot be finished due to the compact layout is solved at one time, meanwhile, the problem of line length optimization is solved, the working efficiency is improved, and the chip design speed is accelerated.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method of dynamically changing a layout according to the present invention;
FIG. 2 is a diagram illustrating standard cell placement and pin access according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a standard cell row layout according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a first design rule check (original layout orientation) according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a second design rule check (A original layout, B flipped) according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating a third design rule check (A flip, B flip) according to the embodiment of the present invention;
FIG. 7 is a diagram illustrating a fourth inspection (A flip, B original layout direction) according to the embodiment of the present invention;
FIG. 8 is a diagram illustrating a structured directional weighting according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart of a dynamic change layout method according to the present invention, and the dynamic change layout method of the present invention will be described in detail with reference to fig. 1.
First, at step 101, pin accesses are created for each standard cell in the design library, creating 3 rectangles for each pin access.
Preferably, the pins are defined on the metal layer, the rectangle in each standard cell instance is a point for pin access, each pin access point is represented by 3 rectangles, which are respectively a vertical rectangle on the metal layer where the pin is located, a horizontal rectangle on a metal layer above the pin, and an intersection of the two rectangles as a via layer between the two metal layers.
In step 102, the standard cells in the layout are sorted, a pin access rectangle of each standard cell is found, whether all pins and barriers in each rectangle and standard cell violate the design rule in the corresponding metal layer or via layer is checked according to the rectangles, and the state of each standard cell violating the design rule is recorded.
Preferably, adjacent standard cells are respectively flipped, and the same checking method is used to obtain a state of violation of the design rule.
Preferably, the rightmost pin of the left standard cell and the leftmost pin of the right standard cell are found. The pins on the left are accessed with 3 rectangles, and all the pins in each rectangle and the standard cells on the right and obstacles in the corresponding metal layer or through hole layer are respectively checked whether the design rules are violated. If not, the 3 rectangles accessed by the leftmost pin in the right standard cell are continuously checked to see if the design rule is violated between the 3 rectangles and all pins and barriers in the left standard cell.
In this embodiment, if a violation of the design rule is found in any one of the checks, it indicates that the two adjacent standard cells need to be flipped to eliminate the problem of the violation of the design rule.
Preferably, the design rule checking status of the adjacent standard cell layout is recorded as Viol _ A _ B [ i ], where i is the index of the standard cell instance corresponding to the standard cell in the row.
In step 103, the state is checked according to the design rule for weight accumulation, a directed weighted graph is constructed, and the shortest path from the source to the target of the weighted graph is found out through a shortest path algorithm.
Preferably, whether the flag state of each standard cell needs to be flipped is reversely tracked according to the shortest path.
In this embodiment, a directed weighted graph is constructed according to the state violating the design rule, the shortest path in the graph is found, and then the flipping flag of the standard cell corresponding to the vertex in each graph is traced backwards to determine whether to flip the standard cell. The original layout problem is solved, and the pin wiring of the standard unit is completed.
The dynamic layout change method of the present invention is further described below with reference to an embodiment.
Fig. 2 is a schematic diagram illustrating a standard cell placement direction and pin access according to an embodiment of the invention.
Standard cell pin access in a standard cell library is first created. There are 8 orientations for any standard cell placement, as shown in FIG. 2, the first row shows 180 degrees, 90 degrees and 270 degrees clockwise rotation in the first direction (north), and the second row is centered with respect to the y-axis for the first row.
FIG. 3 is a diagram illustrating a standard cell row layout according to an embodiment of the invention.
In a particular design, the placer places multiple instances of standard cells in the same row, as shown in FIG. 3. The dot-filled rectangles are standard cell pins (Pin) that are defined on Metal layer M1 (Metal), the dashed-line-sided rectangles in each labeled cell instance are the points that the pins access, each Pin access point is represented by 3 rectangles, respectively a vertical dashed-line rectangle on Metal layer M1 on which the Pin is located, a horizontal dashed-line-sided rectangle on Metal layer M2 (Metal 2) above the Pin, and the intersection of the two rectangles serves as a Via layer V12 (Via 1) between the two Metal layers. The wall-like filled rectangle in fig. 3 is an obstacle. Firstly, sequencing the row standard units according to the x direction, then traversing each example, finding out the leftmost pin, the rightmost pin and 3 rectangles accessed by the corresponding pins from each standard unit example, respectively using the 3 rectangles to check the design rule, and recording the state of each standard unit violating the design rule. Similarly, flipping each standard cell may result in a state of violation of design rules between adjacent standard cell instances for another 3 times. Marking the example of the left standard cell as A, and the example of the left standard cell after being turned over as ATThe example of the right standard cell is B, and the example of the right standard cell after being turned over is BTThus, the 4 checks of the adjacent standard cells are A and B, A and B respectivelyT，ATAnd BTAnd ATAnd B.
FIG. 4 is a diagram illustrating a first design rule check (original layout direction) according to an embodiment of the present invention.
As shown in fig. 4, the first design rule check is the layout of the adjacent standard cells in the original design, finding the rightmost pin of the left standard cell and the leftmost pin of the right standard cell. The pins on the left are accessed with 3 rectangles, and all the pins in each rectangle and the standard cells on the right and obstacles in the corresponding metal layer or through hole layer are respectively checked whether the design rules are violated. If not, the 3 rectangles accessed by the leftmost pin in the right standard cell are continuously checked to see if the design rule is violated between the 3 rectangles and all pins and barriers in the left standard cell. If the design rule is violated in any one check, the two adjacent standard cells need to be subjected to flipping processing to eliminate the problem of violation of the design rule. Recording the design rule checking state of the adjacent standard cell layout as Viol _ A _ B [ i ], wherein i is the index corresponding to the standard cell example in the row of standard cells.
FIG. 5 is a diagram illustrating a second design rule check (A original layout, B flipped) according to an embodiment of the present invention.
As shown in fig. 5, the second design rule check is performed to keep the left standard cell direction unchanged, and the right standard cell direction is reversed, similar to the first design rule check, to check the design rules between the 3 pin access rectangles of the rightmost pin of the left standard cell and the pins and obstacles in the right standard cell, and to check the design rules between the 3 pin access rectangles of the leftmost pin of the right standard cell and the pins and obstacles in the left standard cell, respectively. Recording the design rule checking status of the adjacent standard cell layout as Viol _ A _ BT[i]And i is the index of the standard cell instance corresponding to the standard cell in the row.
FIG. 6 is a diagram illustrating a third design rule check (A flip, B flip) according to an embodiment of the present invention.
As shown in FIG. 6, the third design rule check, the left standard cell direction flip, and the right standard cell direction flip, similar to the previous design rule check, are performed separatelyChecking design rules among the 3 pins of the rightmost pin of the left standard unit, the pins in the right standard unit and the obstacles, and checking design rules among the 3 pins of the leftmost pin of the right standard unit, the pins in the left standard unit and the obstacles. Recording the design rule checking status of the adjacent standard cell layout as Viol _ AT_BT[i]And i is the index of the standard cell instance corresponding to the standard cell in the row.
FIG. 7 is a diagram illustrating a fourth design rule check (A flip, B primitive layout direction) according to the embodiment of the invention.
As shown in fig. 7, the fourth design rule check, which turns the left standard cell direction and keeps the original direction of the right standard cell unchanged, is similar to the previous design rule check, and checks the design rules between the 3 pin access rectangles of the rightmost pin of the left standard cell and the pins and obstacles in the right standard cell, and checks the design rules between the 3 pin access rectangles of the leftmost pin of the right standard cell and the pins and obstacles in the left standard cell, respectively. Recording the design rule checking status of the adjacent standard cell layout as Viol _ AT_B[i]And i is the index of the standard cell instance corresponding to the standard cell in the row.
FIG. 8 is a diagram illustrating a structured directional weighting according to an embodiment of the present invention.
As shown in fig. 8, a directed weighted graph is constructed, and the edges in the graph are subjected to weight accumulation according to the state under 4 design rule checks, so as to complete the construction of the directed weighted graph. Through a shortest path algorithm, the shortest path from the source to the destination of the graph is found.
In this embodiment, the method for weighting the edges of the directed weighted graph includes, if the rectangle of the pin access point violates the design rule, assigning a larger weight to the corresponding edge, if the pin itself violates the design rule, the corresponding edge has a smaller weight, and if the pin itself does not violate the design rule, assigning a minimum weight or a zero weight to the weight of the corresponding edge.
In this embodiment, when the rectangles of all the pin access points violate the design rule, the corresponding edges all use the same weight value, which is a number, and the weight value is reflected in the current standard cell layout direction, and is the weight value of the corresponding edge in the directed graph, for example, 20. The value is chosen arbitrarily, and as long as the pin access point rectangle violates such a design rule, the weight value is used fixedly, and is larger than the smaller weight value assigned if the pin itself violates the design rule. A smaller weight value may be less than the larger weight value selected if the pin access point rectangle violates a design rule, such as 10. Therefore, each edge in the directed graph has a heuristic weighted value, and the shortest path is obtained by applying a shortest path search algorithm to the directed weighted graph.
In this embodiment, after the shortest path is found, each vertex on the path may know the flag indicating whether the standard cell is flipped, and determine whether flipping is required according to the flag comparing the state of the standard cell in the cell layout.
The invention provides a method for checking standard cell pins in a layout before wiring, which is characterized in that a layout result is considered before wiring or in the wiring process, the whole layout is scanned, the condition that a router cannot connect the pins or the layout is changed to reach the minimum wire length due to too close standard cells is checked, in fact, the method is a part for searching standard cell Pin Access (Pin Access) in the wiring process, on the basis of the part, if the standard cells are checked to violate a design rule, the standard cells are turned over, so that the problem that the standard cell pins cannot be wired due to the layout problem can be solved, the problem that complex constraint is added to re-layout in the layout stage is avoided, and the design flow is accelerated. According to the actual situation of the layout or the standard cell distance appointed by a user, the problem that wiring cannot be completed due to compact layout is solved at one time, meanwhile, the problem of line length optimization is solved, the working efficiency is improved, and the chip design speed is accelerated.
In an embodiment of the present invention, there is also provided an electronic device, including a memory and a processor, where the memory stores a computer program running on the processor, and the processor executes the steps of the dynamic layout change method as described above when executing the computer program.
In an embodiment of the present invention, there is also provided a computer readable storage medium having stored thereon a computer program which, when run, performs the steps of the method of dynamically changing a layout as described above.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for dynamically changing a layout, comprising the steps of:
establishing a standard unit pin access and a rectangle corresponding to the standard unit pin access;
sequencing the standard units, finding out a pin access rectangle of each standard unit, and checking a design rule to obtain a state violating the design rule;
and constructing a directed weighted graph according to the state of violating the design rule, turning the standard unit and finishing pin wiring of the standard unit.
2. The method of dynamically changing layout of claim 1 wherein the step of creating standard cell pin accesses and their corresponding rectangles further comprises,
defining a rectangle on each standard unit as a pin access point;
respectively creating a rectangle on the layer where the standard unit pin is located and the upper layer;
a rectangle is created on the via layer between the layer where the standard cell pin is located and the previous layer at the intersection of the two rectangles.
3. The method of claim 1, wherein the step of sorting the standard cells to find the pin access rectangles of each standard cell and checking the design rules to obtain the state violating the design rules further comprises the step of checking the design rules including finding the rightmost pin of the left standard cell and the leftmost pin of the right standard cell, checking whether all pins and barriers in each rectangle of the left pin and the right standard cell violate the design rules in the corresponding metal layer or via layer, and if not, checking whether the design rules are violated between each rectangle of the leftmost pin in the right standard cell and all pins and barriers in the left standard cell.
4. The method of claim 3, further comprising, if the design rule is violated, keeping the direction of the left standard cell, flipping the direction of the right standard cell, checking the design rule, and determining whether the design rule is violated.
5. The method of claim 4, wherein the step of determining whether the design rule is violated further comprises, if the design rule is violated, flipping the direction of the left standard cell and the direction of the right standard cell, checking the design rule, and determining whether the design rule is violated.
6. The method of claim 5, wherein the step of determining whether the design rule is violated further comprises, if the design rule is violated, flipping the left cell direction, keeping the right cell direction, checking the design rule, and determining whether the design rule is violated.
7. The method of claim 1, wherein the step of constructing a weighted graph according to the state violating the design rule, flipping the standard cell and completing the wiring of the pins of the standard cell further comprises the steps of accumulating the weights of the same edge according to the states violating the design rule of the pins and the pins themselves, completing the construction of the weighted graph, and finding the shortest path in the weighted graph according to a shortest path algorithm.
8. The dynamically changing layout method of claim 7 further comprising,
if the rectangle of the pin access point violates the design rule, allocating a preset weight to the corresponding edge;
if the pins per se violate the design rules, distributing preset weight to the corresponding edges;
and if the design rule is not violated, distributing zero weight to the corresponding edge.
9. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the method of dynamically changing a layout according to any one of claims 1 to 8.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program executes the steps of the method for dynamically changing a layout of a device according to any of claims 1 to 8.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023122911A1 (en) * | 2021-12-27 | 2023-07-06 | 华为技术有限公司 | Method, apparatus and device for laying out standard cells, and storage medium and program product |
| CN117371382A (en) * | 2023-10-24 | 2024-01-09 | 深圳市合芯数字科技有限公司 | Standard cell layout processing method, device and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0174236A1 (en) * | 1984-08-07 | 1986-03-12 | Fujitsu Limited | Semiconductor integrated circuit device having a test circuit |
| CN104063559A (en) * | 2014-07-08 | 2014-09-24 | 领佰思自动化科技(上海)有限公司 | Layout legalization method and system for distributed computing of large-scale integrated circuit |
| CN107068670A (en) * | 2015-09-18 | 2017-08-18 | 台湾积体电路制造股份有限公司 | Cell layout, cell layout storehouse and its synthetic method of semiconductor devices |
| CN109817614A (en) * | 2017-11-21 | 2019-05-28 | 台湾积体电路制造股份有限公司 | The method of standard unit structure and placement and line standard cellular construction |
| CN111539166A (en) * | 2020-04-23 | 2020-08-14 | 福州立芯科技有限公司 | Mixed high standard cell circuit legalization method considering advanced process constraint |
-
2020
- 2020-12-10 CN CN202011432870.8A patent/CN112214964B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0174236A1 (en) * | 1984-08-07 | 1986-03-12 | Fujitsu Limited | Semiconductor integrated circuit device having a test circuit |
| CN104063559A (en) * | 2014-07-08 | 2014-09-24 | 领佰思自动化科技(上海)有限公司 | Layout legalization method and system for distributed computing of large-scale integrated circuit |
| CN107068670A (en) * | 2015-09-18 | 2017-08-18 | 台湾积体电路制造股份有限公司 | Cell layout, cell layout storehouse and its synthetic method of semiconductor devices |
| CN109817614A (en) * | 2017-11-21 | 2019-05-28 | 台湾积体电路制造股份有限公司 | The method of standard unit structure and placement and line standard cellular construction |
| CN111539166A (en) * | 2020-04-23 | 2020-08-14 | 福州立芯科技有限公司 | Mixed high standard cell circuit legalization method considering advanced process constraint |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023122911A1 (en) * | 2021-12-27 | 2023-07-06 | 华为技术有限公司 | Method, apparatus and device for laying out standard cells, and storage medium and program product |
| CN117371382A (en) * | 2023-10-24 | 2024-01-09 | 深圳市合芯数字科技有限公司 | Standard cell layout processing method, device and storage medium |
| CN117371382B (en) * | 2023-10-24 | 2024-05-28 | 深圳市合芯数字科技有限公司 | Standard cell layout processing method, device and storage medium |
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