CN113591430B - Method for detecting layout wiring net violation - Google Patents
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- CN113591430B CN113591430B CN202110891156.3A CN202110891156A CN113591430B CN 113591430 B CN113591430 B CN 113591430B CN 202110891156 A CN202110891156 A CN 202110891156A CN 113591430 B CN113591430 B CN 113591430B
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The method for detecting the violation of the layout wiring net comprises the following steps: 1) traversing all wiring data on the wiring layers in a layering manner to obtain a rectangular array corresponding to the wiring data; 2) processing the wiring data, and extending each rectangle in the rectangle array by a first distance; 3) sorting all rectangles on the wiring layer which is currently processed; 4) sequentially processing the sorted rectangles to determine intersecting rectangles; 5) and determining violation information according to the first distance and the net attributes. The invention can detect the detailed wiring result, ensure the correctness of the wiring result, and can return the detected violation area and net information to the router when a short circuit occurs or a rectangle violating the minimum spacing constraint occurs, so as to guide the router to re-route the related net.
Description
Technical Field
The invention relates to the technical field of EDA (electronic design automation) design, in particular to a method for detecting layout wiring network violation.
Background
With the increasing demand of ultra-deep submicron technology, the back-end physical design in the integrated circuit design flow becomes more and more complex, so that the application of EDA (electronic design automation) tools becomes an indispensable auxiliary means in the back-end physical design.
In the detailed wiring stage of the VLSI of the very large scale integrated circuit, there are often a plurality of nets that need to be connected, each net has two or more pins waiting for connection, the pins waiting for connection need to be connected in the detailed wiring stage, numerous design rule constraints need to be satisfied while the pins are connected, and increasing process requirements lead to more and more new design constraints being required to be satisfied, which increases the complexity of the wiring stage. Therefore, one of the basic goals of today's mainstream layout routing tools is to automatically and quickly generate net graph connections that meet the requirements of design rules. Among the many design rule requirements, it is the most basic design rule that there are no shorts between different nets and that the minimum spacing constraint is satisfied.
A method for detecting net short circuit in integrated circuit layout detailed wiring is a method for detecting connectivity relation of an EDA tool in a wiring process and judging whether different nets are communicated in error or not. The minimum spacing constraint detection method in the detailed wiring of the integrated circuit layout is a method for checking design rules of an EDA tool in the wiring process and judging whether wiring results of different nets violate the minimum spacing constraint or not. A wiring violation is generally referred to as a wiring violation when a wiring net is shorted and a minimum spacing constraint is violated between the wiring results of different nets. It would be advantageous to provide a method for conveniently and quickly determining whether a wired net is shorted and a minimum spacing constraint is met.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a method for detecting the violation of a layout wiring net, which can be applied to detect the wiring data of all nets and judge whether short-circuit conditions exist among different nets. For nets with no shorts, it is determined whether there is a violation of the minimum spacing constraint between them.
In order to achieve the above object, the method for detecting a violation of a layout wiring net provided by the present invention comprises the following steps:
1) traversing all wiring data on the wiring layers in a layering manner to obtain a rectangular array corresponding to the wiring data;
2) processing the wiring data, and extending each rectangle in the rectangle array by a first distance;
3) sorting all rectangles on the wiring layer which is processed currently;
4) sequentially processing the sorted rectangles to determine intersecting rectangles;
5) and determining violation information according to the first distance and the net attributes.
Further, the routing data includes data of metal lines, vias and pins, and step 1) further includes cutting polygons encountered during traversing the routing data on the routing layer into a plurality of rectangles, and finally, each routing data corresponds to one or more rectangles, and the one or more rectangles are collected and stored in a rectangle array corresponding to the routing layer.
Further, the step 2) further comprises,
making a horizontal sitting mark of a corner point at the lower left corner of the external expansion front rectangle as a first horizontal coordinate at the lower left corner, making a vertical sitting mark of the corner point at the lower left corner of the external expansion front rectangle as a first vertical coordinate at the lower left corner, making a horizontal sitting mark of a corner point at the upper right corner of the external expansion front rectangle as a first horizontal coordinate at the upper right corner, and making a vertical sitting mark of the corner point at the upper right corner of the external expansion front rectangle as a first vertical coordinate at the upper right corner;
making a horizontal sitting mark of a corner point at the lower left corner of the externally expanded rectangle as a second horizontal coordinate at the lower left corner, making a vertical sitting mark of the corner point at the lower left corner of the externally expanded rectangle as a second vertical coordinate at the lower left corner, making a horizontal sitting mark of a corner point at the upper right corner of the externally expanded rectangle as a second horizontal coordinate at the upper right corner, and making a vertical sitting mark of the corner point at the upper right corner of the externally expanded rectangle as a second vertical coordinate at the upper right corner; wherein the content of the first and second substances,
a second horizontal coordinate of the lower left corner is the first horizontal coordinate of the lower left corner-the first distance;
the second ordinate of the lower left corner is the first ordinate of the lower left corner-the first distance;
the second abscissa of the upper right corner is equal to the first abscissa of the upper right corner plus the first distance;
the second ordinate of the upper right corner is the first ordinate of the upper right corner plus the first distance.
Further, the step 3) sorts all rectangles on the wiring layer currently processed according to the sorting priority of the second abscissa at the lower left corner, the second ordinate at the lower left corner, the second abscissa at the upper right corner, and the second ordinate at the upper right corner.
Further, the step 4) further comprises, according to the order of the rectangles sorted in the step 3), sequentially processing the rectangles according to the following steps:
51) storing all rectangles overlapping with the currently processed rectangle in the X direction by using a first set;
52) organizing intervals of the rectangles in the first set in the Y direction by using an interval tree;
53) finding out a rectangle overlapped with the current rectangle in the Y direction through the interval tree;
if any rectangle intersected with the current rectangle cannot be found through interval tree search, processing a rectangle next to the current rectangle in the sequencing result, and updating the contents in the first set and the interval tree.
Further, the first distance is equal to zero, and when the intersected rectangles belong to the same wire net, the current wire net is judged not to cause short circuit; and when the intersected rectangles belong to different nets, judging that a short circuit exists between the two nets, recording information of a short circuit area and a short circuit net, and adding one to the number of the short circuits.
Further, the first distance is the minimum spacing constraint value of the current wiring layer, and if the intersected rectangles belong to the same wire net, skipping is carried out; if the intersected rectangles belong to different nets, the actual distance between the two intersected rectangles is calculated and compared with the minimum distance constraint value, and whether the minimum distance constraint is violated is judged.
Further, it is determined that the wiring violates the minimum pitch constraint if one of the following three conditions is satisfied:
(a)Δx<x_spacing；
(b)Δy<y_spacing；
(c)Δx2+Δy2<diagonal_spacing2；
wherein, Δ x is the distance between the center points of the two intersecting rectangles along the x-axis direction; delta y is the distance between the center points of the two intersected rectangles along the y-axis direction; x _ spacing is the minimum spacing constraint value of the wiring layer in the x direction; y _ spacing is a minimum spacing constraint value of the routing layer in the y direction; diagonalspacing is a diagonal minimum spacing constraint value of the routing layer;
if the intersecting rectangles are judged to violate the minimum spacing constraint, then the region and net information violating the constraint are recorded, and the number of violations is increased by one.
In order to achieve the above object, the present invention further provides an electronic device, which includes a memory and a processor, where the memory stores a program running on the processor, and the processor executes the steps of the method for detecting the violation of the layout wiring net when running the program.
To achieve the above object, the present invention further provides a computer readable storage medium, on which computer instructions are stored, and when the computer instructions are executed, the steps of the method for detecting a violation of a layout wiring net described above are executed.
Compared with the prior art, the method for detecting the violation of the layout wiring net has the following beneficial effects: the invention can detect the detailed wiring result, ensure the correctness of the wiring result, and can return the detected violation area and net information to the router when a short circuit occurs or a rectangle violating the minimum spacing constraint occurs, so as to guide the router to re-route the related net.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for detecting a violation of a layout wiring net according to the present invention;
FIG. 2 is a schematic diagram of a rectangle expanding the minimum pitch of the wiring layer on which it is located;
FIG. 3 is a diagram of sorted rectangular data on a wire mesh;
FIG. 4 is a layout of a short circuit to be detected;
FIG. 5 is a diagram illustrating the short circuit detection effect according to the present invention;
FIG. 6 is a layout of minimum spacing constraints to be detected;
FIG. 7 is a diagram of the effect of minimum spacing constraint detection according to the present invention;
FIG. 8 is a diagram illustrating a calculation of center point distances for a pair of rectangles and a determination of whether a minimum spacing constraint is violated;
FIG. 9 is a diagram illustrating the calculation of the edge distance of a pair of rectangles and the determination of whether the minimum distance constraint is violated.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart of a method for detecting a violation of a layout wiring net according to the present invention, and the method for detecting a violation of a layout wiring net according to the present invention will be described in detail with reference to fig. 1.
In step 101, all the routing data on the routing layer are traversed hierarchically, and a rectangular array corresponding to the routing data is obtained.
In the step, all wiring data including metal wire, through hole and pin data on each wiring layer in the current layout need to be traversed in a layered mode, polygons encountered in the process can be cut into a plurality of rectangles, finally, each wiring data corresponds to one or more rectangles, and the rectangles are collected and stored in a rectangle array corresponding to the wiring layer.
At step 102, the routing data is processed to expand each rectangle in the rectangular array.
In this step, the wiring data collected in step 101 is preprocessed to spread out each rectangle by a certain distance. Assuming that the coordinates of the original rectangle are (xl, yb, xr, yt) and the extension distance is s, the coordinates of the new rectangle after extension are (xl-s, yb-s, xr + s, yt + s), where (xl, yb) is the coordinates of the corner point at the lower left corner of the rectangle and (xr, yt) is the coordinates of the corner point at the upper right corner of the rectangle.
When the detection target is short-circuited, s is 0; when the detection target is the minimum spacing data constraint, s is the minimum spacing constraint value of the routing layer.
Fig. 2 is a schematic diagram of the minimum pitch of the routing layer where the rectangles are extended, where minSpacing is the minimum pitch constraint value of the current routing layer, and each rectangle in the rectangle array is extended according to the value.
At step 103, all rectangles on the currently processed routing layer are sorted.
In this step, all rectangles on the currently processed routing layer are sorted, and the priority of the sort key (sort key) is xl, yb, xr, yt, that is, the rectangles are sorted in ascending order according to the abscissa of the vertex at the lower left corner, and when the abscissas of the vertex at the lower left corner are equal, the rectangles are sorted in ascending order according to the ordinate of the vertex at the lower left corner, and so on. FIG. 3 is a diagram of sorted rectangular data on a net.
And step 104, sequentially processing the sorted rectangles to determine intersecting rectangles.
The intersection of a pair of rectangles after being extended according to the method in step 102 is a necessary condition that a short circuit exists between the two rectangles or a minimum spacing constraint is violated, so that each time a routing layer is checked, all intersected rectangle pairs on the current layer need to be obtained.
In the sorted rectangle order, one rectangle is processed at a time, and all rectangles overlapping with the currently processed rectangle in the X direction are stored with one set. And organizing the intervals of the rectangles in the set in the Y direction by using an interval tree, and quickly finding out the rectangles overlapped with the current rectangles in the Y direction through the interval tree.
If the interval tree can not find out any rectangle intersected with the current rectangle, processing the next rectangle of the current rectangle in the sequencing result, and updating the content in the set and the interval tree so as to reduce the calculation amount for acquiring the intersected rectangle pair.
And 105, determining violation information according to a short-circuit principle and a minimum distance constraint principle.
If a pair of intersecting rectangles is obtained from step 104, then step 105 is performed. In this step 105, different violation information is recorded according to the detection target, specifically:
when the detection target is a short circuit, judging whether the two intersected rectangles belong to the same wire network: if the two rectangles belong to the same net, short circuit is not caused enough; on the contrary, if the two rectangles belong to different nets, a short circuit exists between the two nets, at the moment, information of a short circuit area and the short circuit net is recorded, and the number of the short circuits is increased by one. Fig. 4 is a layout of a short circuit to be detected, and when the short circuit is detected, the detection effect shown in fig. 5 is obtained.
When the detection target is the minimum spacing constraint, if the two rectangles belong to the same wire network, skipping because the minimum spacing constraint is the constraint between different wire networks; on the contrary, if the two rectangles belong to different nets, the two rectangles may violate the minimum distance constraint, and at this time, the actual distances of the two rectangles are calculated and compared with the minimum distance constraint value, and whether the minimum distance constraint is violated is judged. FIG. 6 is a layout of minimum pitch constraints to be detected, and the interface shown in FIG. 6 can be obtained by reading layout data information through an EDA tool and displaying the layout data information on a GUI interface. When the minimum spacing constraint detection is performed on the minimum spacing constraint detection result, a minimum spacing constraint detection command is started to start detection, and a minimum spacing constraint detection effect graph shown in fig. 7 is obtained.
Specific judgment calculation criteria, as shown in fig. 8 and 9, fig. 8 detects the distance between the center points of two rectangles, and fig. 9 detects the distance between the sides of two rectangles, and it can be seen from fig. 8 and 9 that if one of the following three conditions is satisfied, the wiring violates the minimum pitch constraint:
(a)Δx<x_spacing；
(b)Δy<y_spacing；
(c)Δx2+Δy2<diagonal_spacing2。
wherein, Δ x is the distance between the center points of the two intersecting rectangles along the x-axis direction; delta y is the distance between the center points of the two intersected rectangles along the y-axis direction; x _ spacing is the minimum spacing constraint value of the wiring layer in the x direction; y _ spacing is a minimum spacing constraint value of the routing layer in the y direction; diagnonal _ spacing is the diagonal minimum spacing constraint value for a routing layer.
If the pair of rectangles does violate the minimum spacing constraint, then the area and net information violating the constraint is recorded, while the number of violations is increased by one.
After all the wiring layers are processed and traversed, when the detection target is short-circuited, returning all the short-circuited areas, the short-circuited line network information and the short-circuited number; and when the detection target is the minimum distance constraint, returning all the areas, net information and violation quantity violating the minimum distance constraint.
The invention also provides electronic equipment which comprises a memory and a processor, wherein the memory is stored with a program running on the processor, and the processor executes the steps of the method for detecting the violation of the layout wiring net when running the program.
The invention further provides a computer-readable storage medium, wherein computer instructions are stored thereon, and when the computer instructions are executed, the steps of the method for detecting the violation of the layout wiring net are executed.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method for detecting a violation of a layout wiring net is characterized by comprising the following steps:
1) traversing all wiring data on the wiring layers in a layering manner to obtain a rectangular array corresponding to the wiring data;
2) processing the wiring data, and extending each rectangle in the rectangle array by a first distance;
3) sorting all rectangles on the wiring layer which is currently processed;
4) sequentially processing the sorted rectangles to determine intersecting rectangles;
5) determining violation information according to the first distance and the net attribute;
the first distance is equal to zero, and when the intersected rectangles belong to the same wire net, the current wire net is judged not to cause short circuit; when the intersected rectangles belong to different nets, judging that a short circuit exists between the two nets, recording information of a short circuit area and a short circuit net, and adding one to the number of the short circuits;
the first distance is the minimum spacing constraint value of the current wiring layer, and if the intersected rectangles belong to the same wire net, skipping is carried out; if the intersected rectangles belong to different nets, the actual distance between the two intersected rectangles is calculated and compared with the minimum distance constraint value, and whether the minimum distance constraint is violated is judged.
2. The method according to claim 1, wherein the routing data includes metal line, via and pin data, the step 1) further includes cutting polygons encountered during traversing the routing data on the routing layer into a plurality of rectangles, and finally each routing data corresponds to one or more rectangles, and the one or more rectangles are collected and stored in the rectangle array corresponding to the routing layer.
3. The method according to claim 1, wherein said step 2) further comprises,
making a horizontal sitting mark of a corner point at the lower left corner of the external expansion front rectangle as a first horizontal coordinate at the lower left corner, making a vertical sitting mark of the corner point at the lower left corner of the external expansion front rectangle as a first vertical coordinate at the lower left corner, making a horizontal sitting mark of a corner point at the upper right corner of the external expansion front rectangle as a first horizontal coordinate at the upper right corner, and making a vertical sitting mark of the corner point at the upper right corner of the external expansion front rectangle as a first vertical coordinate at the upper right corner;
making a horizontal sitting mark of a corner point at the lower left corner of the externally expanded rectangle as a second horizontal coordinate at the lower left corner, making a vertical sitting mark of the corner point at the lower left corner of the externally expanded rectangle as a second vertical coordinate at the lower left corner, making a horizontal sitting mark of a corner point at the upper right corner of the externally expanded rectangle as a second horizontal coordinate at the upper right corner, and making a vertical sitting mark of the corner point at the upper right corner of the externally expanded rectangle as a second vertical coordinate at the upper right corner; wherein, the first and the second end of the pipe are connected with each other,
a second horizontal coordinate of the lower left corner is the first horizontal coordinate of the lower left corner-the first distance;
the second ordinate of the lower left corner is the first ordinate of the lower left corner-the first distance;
the second abscissa of the upper right corner is equal to the first abscissa of the upper right corner plus the first distance;
the second ordinate of the upper right corner is the first ordinate of the upper right corner plus the first distance.
4. The method according to claim 3, wherein said step 3) sorts all rectangles on the currently processed wiring layer according to the sorting priority of the second abscissa at the lower left corner, the second ordinate at the lower left corner, the second abscissa at the upper right corner, and the second ordinate at the upper right corner.
5. The method for detecting layout wiring net violation according to claim 4, wherein the step 4) further comprises, according to the sorted rectangles in the step 3), sequentially processing the rectangles according to the following steps:
51) storing all rectangles overlapping with the currently processed rectangle in the X direction by using a first set;
52) organizing intervals of the rectangles in the first set in the Y direction by using an interval tree;
53) finding out a rectangle overlapped with the current rectangle in the Y direction through the interval tree;
if any rectangle intersected with the current rectangle cannot be found through interval tree search, processing a rectangle next to the current rectangle in the sequencing result, and updating the contents in the first set and the interval tree.
6. The method according to claim 1, further comprising determining that the wiring violates the minimum-distance constraint if one of the following three conditions is satisfied:
(a)Δx<x_spacing；
(b)Δy<y_spacing；
(c)Δx2+Δy2<diagonal_spacing2；
wherein, Δ x is the distance between the center points of the two intersecting rectangles along the x-axis direction; delta y is the distance between the center points of the two intersected rectangles along the y-axis direction; x _ spacing is the minimum spacing constraint value of the wiring layer in the x direction; y _ spacing is a minimum spacing constraint value of the routing layer in the y direction; diagonalspacing is a diagonal minimum spacing constraint value of the routing layer;
if the intersecting rectangles are judged to violate the minimum spacing constraint, then the region and net information violating the constraint are recorded, and the number of violations is increased by one.
7. An electronic device, comprising a memory and a processor, wherein the memory stores a program running on the processor, and the processor executes the program to perform the steps of the method for detecting violations of layout wiring net according to any of claims 1-6.
8. A computer-readable storage medium having stored thereon computer instructions, wherein the computer instructions, when executed, perform the steps of the method of detecting a violation of a layout wiring net of any of claims 1-6.
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| CN116070575B (en) * | 2023-01-12 | 2023-08-15 | 广东工业大学 | Chip wiring optimization method and software system |
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