CN114815494B - Optical proximity correction method and system, mask plate, equipment and storage medium - Google Patents
Optical proximity correction method and system, mask plate, equipment and storage medium Download PDFInfo
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- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
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Abstract
The invention provides an optical proximity correction method and system, a mask, equipment and a storage medium, wherein the optical proximity correction method comprises the following steps: the invention provides a method for an optical proximity correction model, an optical proximity correction system and a mask plate, wherein the optical proximity correction method comprises the following steps: providing an optical proximity correction model, wherein the optical proximity correction model adopts a standard test pattern database to carry out simulation, selects part of test patterns in the test pattern database as basic test patterns, and selects real chip patterns in the real chip pattern database; calculating the multistage difference between the basic test pattern and the real chip pattern feature vector; and sorting the standby test patterns based on the multi-level difference from small to large, and adding the standby test patterns which are sorted and smaller than the preset rank into the basic test patterns.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to an optical proximity correction method and system, a mask, equipment and a storage medium.
Background
As feature sizes continue to decrease and graphics complexity becomes higher, optical proximity correction (Optical Proximity Correction, OPC) techniques have been widely used in mask designs for critical levels. The most widely used OPC method at present is the model-based OPC correction method, specifically, by modeling some type of physical model to simulate the interaction of light sources, optical components, light propagation and light substances, predicting the pattern profile and feature size on the wafer as accurately as possible.
A typical OPC model generally contains three sub-models: optical model, mask three-dimensional effect model (DDM) model, and photoresist model. The optical model simulates an image projected onto the resist, the DDM model simulates light waves in the mask, and the resist model simulates the developed resist profile. To accurately train these models, we need to first provide the model with seed parameters as standard real data (ground truth). The model will then adjust its internal parameters so that the simulation results more closely resemble standard real data. These seed parameters are test patterns based on design rules, which may generally represent actual chips in the production process. It is often difficult to define standard values for the test patterns and evaluate how well the test patterns may represent a real chip in the future.
Disclosure of Invention
The invention solves the problem of providing an optical proximity correction method, an optical proximity correction system and a mask plate, and optimizing an optical proximity correction effect.
In order to solve the above problems, the present invention provides an optical proximity correction method, an optical proximity correction system, and a mask plate, where the method includes:
Optionally, the step of extracting feature vectors of the basic test pattern and the real chip pattern includes:
and selecting key feature data of the part of test patterns and the real chip patterns, and representing the key feature data as feature vectors.
Optionally, the step of selecting the key feature data of the partial test pattern and the real chip pattern includes: extracting key feature data by taking the whole of each part of test patterns and the whole of the real chip patterns as a reference; or extracting key characteristic data by taking key fragments in each of the partial test patterns and the real chip patterns as references.
Optionally, the key segment is a graphic feature size measurement location.
Optionally, the test pattern is a symmetrical pattern, and the key segment is an edge bit line in a middle portion of the symmetrical pattern.
Optionally, the test pattern includes a plurality of line patterns arranged in parallel, and the key segment is an edge bit line located in the middle line pattern.
Optionally, the step of selecting the key feature data of the partial test pattern and the real chip pattern includes: and calculating the importance nominal value of each parameter in the feature vector according to the input data by adopting a random forest classifier.
Optionally, the step of selecting the key feature data of the part of the test pattern and the real chip pattern further includes: before calculating the importance nominal value of each parameter in the feature vector, calling a test pattern from a test pattern library and calling a real chip pattern from a real chip pattern database; recording key characteristic data values of each test pattern or real chip pattern as a group of key characteristic data; each group of key feature data is expressed as a feature vector, and a label is added to each feature vector; and taking each feature vector and the corresponding label as training data of the random forest classifier.
Optionally, the step of adding a tag to each feature vector includes: for each feature vector, calculating the model error of each parameter of the feature vector, marking the label of the feature vector as 0 if the model error is smaller than a threshold value T, and marking the label of the feature vector as 1 if the model error is larger than or equal to the threshold value T.
Optionally, the step of adding a tag to each feature vector includes: for each feature vector, calculating the model error of each parameter of the feature vector, and directly marking the model error value as a label of the corresponding feature vector.
Optionally, the step of calculating a multi-level difference between the partial test pattern and the real chip pattern feature vector includes: and calculating the Euclidean distance between the partial test graph and the real chip graph feature vector, and taking the Euclidean distance as a multi-level difference.
Optionally, the step of calculating the euclidean distance between the partial test pattern and the real chip pattern feature vector includes: the selected part of the test patterns is set to be a first group of patterns, the selected real chip patterns are set to be a second group of patterns, the feature vectors of the part of the test patterns are set to be a first group of feature vectors, the feature vectors of the real chip patterns are set to be a second group of feature vectors, the Euclidean distance is D kij＝(Aki-Bkj)2, wherein Aki is the value of the kth parameter of the ith test pattern in the first group of feature vectors, bkj is the value of the kth parameter of the jth real chip pattern in the second group of feature vectors, and Dkij is the Euclidean distance between the test pattern Ai and the real chip pattern Bj based on the kth parameter.
Optionally, if the first set of feature vectors includes m test patterns, the second set of feature vectors includes n real chip patterns, each feature vector includes l parameters, and if the importance nominal value of the kth parameter is Ik, the Euclidean distance between each test pattern Ai and the real chip pattern Bj is The Euclidean distance between the whole first group of feature vectors and each real chip pattern Bj is/>The average Euclidean distance between the first set of feature vectors and the second set of feature vectors is/>
Optionally, the step of evaluating the coverage degree of the test pattern on the real chip pattern includes: a first threshold T i is defined for D Aj, a second threshold T a is defined for D AB, and if D AB≤Ta and all D Aj≤Ti, the first set of graphics have ideal model coverage for the second set of graphics.
Optionally, if D Aj>Ti, classifying all the second set of patterns of D Aj>Ti as uncovered patterns, defining all the uncovered patterns as a third set of patterns, and re-selecting a part of the standby test patterns in the test pattern library as a fourth set of patterns; and calculating Euclidean distance between the third group of patterns and each fourth group of patterns, recording Euclidean distance D Cp between the third group of patterns and the p-th pattern in the fourth group of patterns, and adding the first q test patterns with the minimum Euclidean distance D Cp in the fourth group of patterns into the first group of patterns to serve as basic test patterns.
Optionally, after adding the top q ordered standby test patterns to the base test pattern, the following steps are performed again:
Extracting feature vectors of the basic test pattern and the real chip pattern, and calculating multistage differences between the feature vectors of the partial test pattern and the real chip pattern;
updating ideal coverage, evaluating the coverage degree of the test pattern on the real chip pattern according to the multi-level difference, and taking the real chip pattern with the coverage degree lower than the ideal coverage degree as an uncovered pattern;
And re-selecting part of standby test patterns in the test pattern library according to the evaluation result, calculating the multi-level difference between the part of standby test patterns and the feature vector of the uncovered pattern, sequencing the re-selected standby test patterns according to the multi-level difference from small to large, and adding the first q sequenced standby test patterns into the basic test patterns.
The invention also provides an optical proximity correction system, comprising: the model building unit is used for building an optical proximity correction model, wherein the optical proximity correction model is used for optical proximity correction, and the optical proximity correction model adopts a standard test pattern database for analog simulation; and the optimization unit optimizes the standard test pattern database based on the key characteristic data of the test patterns and the real chip patterns so as to improve the coverage rate of the test patterns to the real chip patterns.
Optionally, the optimizing unit includes: the basic database module comprises a test graphic database and a real chip graphic database; the data extraction module is used for selecting part of test patterns in the test pattern library as basic test patterns, selecting real chip patterns in the real chip pattern database, taking the rest test patterns in the test pattern library as standby test patterns, and extracting feature vectors of the basic test patterns and the real chip patterns, wherein the feature vectors represent key feature data of the test patterns and the real chip patterns; the coverage evaluation module is used for calculating the multistage difference between the basic test pattern and the real chip pattern feature vector, evaluating the coverage degree of the basic test pattern on the real chip pattern according to the multistage difference, and taking the real chip pattern with the actual coverage degree lower than the preset coverage degree as an uncovered pattern; and the feedback module is used for selecting part of standby test patterns in the test pattern library according to the evaluation result, calculating the multistage difference between the part of standby test patterns and the feature vector of the uncovered pattern, sequencing the standby test patterns from small to large based on the multistage difference, and adding the standby test patterns which are sequenced and are smaller than the preset ranking into the basic test patterns so as to update the standard test pattern database of the optical proximity correction model.
The invention also provides a mask plate, and the graph on the mask plate is obtained by the optical proximity correction system.
The present invention also provides an apparatus comprising: at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executable by the processor to implement the method of optical proximity correction provided by the present invention.
The invention also provides a storage medium storing one or more computer instructions for implementing the optical proximity correction method provided by the invention.
Compared with the prior art, the technical scheme of the invention has the following advantages: the method for evaluating the coverage degree of the test pattern on the real chip pattern is provided, and test patterns with higher coverage degree on the real chip pattern can be screened and put into a standard test pattern library. The specific content comprises the steps of evaluating the coverage degree of the test pattern on the real chip pattern, and taking the real chip pattern with the coverage degree lower than the ideal coverage degree as an uncovered pattern; according to the evaluation result, re-selecting part of standby test patterns in the test pattern library, and adding the test patterns with ideal coverage into the basic test patterns; according to the basic test pattern obtained by the technical scheme, the standard test pattern database of the optical proximity correction model is updated, so that the coverage rate of the standard test pattern database to the real chip pattern can be improved, the correction effect of optical proximity correction is improved, the optical proximity correction efficiency is improved, and the yield of chip production is further improved.
In an alternative scheme of the invention, the feature vectors of the basic test pattern and the real chip pattern are extracted, and the feature vectors represent key feature data of the test pattern and the real chip pattern. The step of extracting feature vectors of the test pattern and the real chip pattern includes: the method for selecting the key feature data of the partial test patterns and the real chip patterns, and the key feature data are expressed as feature vectors, and the step of selecting the key feature data of the partial test patterns and the real chip patterns comprises the following steps: and calculating the importance nominal value of each parameter in the feature vector according to the input data by adopting a random forest classifier. The random forest classifier is an advanced machine learning training method, can accurately measure the importance of each parameter, and can further effectively improve the effect of correcting the local abnormal problem of the characteristic dimension of the graph.
In an alternative aspect of the present invention, the step of calculating the multi-level difference between the partial test pattern and the real chip pattern feature vector includes: and calculating the Euclidean distance between the feature vectors, wherein the Euclidean distance is used as a multi-level difference, namely, after various key feature data of the test pattern and the real chip pattern are extracted as the feature vectors, the distance of corresponding parameters in the feature vectors between the test pattern and the real chip pattern is calculated, and the distances are summarized into the Euclidean distance by referring to the weight of each parameter. Specifically, the test patterns are set as A-group patterns, the real chip patterns are set as B-group patterns, euclidean distances between each test pattern and each real chip pattern are calculated respectively, euclidean distances between each A-group pattern and all B-group patterns are calculated, and Euclidean distances between all A-group patterns and all B-group patterns are calculated. Therefore, the coverage degree of the current test pattern on the single real chip pattern and all the real chip patterns can be completely represented, and the subsequent selection of the test pattern with higher coverage degree on the real chip patterns is facilitated.
Drawings
FIG. 1 is a schematic diagram of a prior art class of test patterns;
FIG. 2 is a step diagram of an embodiment of an optical proximity correction method of the present invention;
FIG. 3 is a graph showing the relationship between an optical proximity correction model and a test pattern library according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of extracting key feature data on a test pattern according to an embodiment of the invention;
FIG. 5 is a schematic diagram of an embodiment of an optical proximity correction system of the present invention.
Detailed Description
The optical proximity correction model in the prior art has the problem of low optical proximity correction precision. The cause of the problems described above is analyzed in connection with prior art solutions.
Currently, the method of designing test patterns is based on test rules. For example, if the step size is 10nm in the design rule, the reference size of the pattern is defined to be 40nm to 200nm, and the feature size is selected from 20nm, 25nm and 30 nm. To better verify the reality of the pattern, the pattern reference size range of the test pattern is generally designed to be from 30nm to 240nm, i.e., the value is less than 30% of the minimum value of the pattern reference size range and more than 20% of the maximum value of the pattern reference size range, based on the design rule. As shown in fig. 1, which is a prior art type of test pattern, for the purpose of measuring feature sizes, such test patterns are symmetrical patterns, each symmetrical pattern including a plurality of stripe patterns parallel to each other, three different sizes of test patterns are shown in fig. 1. Taking the intermediate test pattern as an example, when collecting pattern size data, collecting the sum P1 of the line width and the distance of the intermediate strip pattern as a pattern reference size, and the line width C1 of the intermediate strip pattern as a characteristic size, wherein the characteristic size of the intermediate strip pattern is used as a seed parameter when the actual measurement of the patterns after wafer etching is carried out.
However, the current test pattern design method has the following disadvantages that a large number of asymmetric patterns exist in patterns on a real chip, standard real data obtained from the test patterns are difficult to completely represent real conditions, in addition, the current test method needs to generate a large number of test patterns, but an OPC model can only perform simulation tests of a limited number of models, so that the test patterns need to be screened, and no proper method proves that the screened test patterns can verify all conditions in the real chip, therefore, the OPC model obtained by training with seed parameters may not perform well in a certain way, and thus the problem that the result of optical proximity correction output is easy to fail exists in the current method.
Therefore, the method for correcting the optical proximity optimizes the standard test pattern database in the optical proximity correction model, improves the coverage rate of the test patterns in the standard test pattern database on the real chip patterns, improves the accuracy of the optical proximity correction, and further improves the yield of chip production.
Referring to fig. 2, a step diagram of an optical proximity correction method according to an embodiment of the invention is shown. In this embodiment, the optical proximity correction method includes the steps of:
step S1, an optical proximity correction model is provided, wherein the optical proximity correction model adopts a standard test pattern database to carry out simulation, and the standard test pattern database comprises the following components: a test graphic library and a real chip graphic database;
S2, selecting part of test patterns in the test pattern library as basic test patterns, using the rest test patterns in the test pattern library as standby test patterns, and selecting the real chip patterns in the real chip pattern database;
Step S3, extracting feature vectors of the basic test pattern and the real chip pattern, expressing key feature data of the basic test pattern and the real chip pattern by the feature vectors, and calculating multistage differences between the feature vectors of the basic test pattern and the real chip pattern;
S4, evaluating the actual coverage of the basic test pattern to the real chip pattern according to the multi-level difference, and taking the real chip pattern with the actual coverage degree lower than the preset coverage degree as an uncovered pattern;
And S5, selecting part of standby test patterns in the test pattern library according to the evaluation result, calculating the multistage difference between the part of standby test patterns and the feature vector of the uncovered pattern, sequencing the standby test patterns from small to large based on the multistage difference, and adding the standby test patterns which are sequenced and are smaller than the preset ranking into the basic test patterns so as to update the standard test pattern database of the optical proximity correction model.
In order to make the above objects, features and advantages of the present invention more comprehensible, the following describes the method for correcting the optical proximity correction model according to the present embodiment with reference to the accompanying drawings.
Referring to fig. 3, a graph of the relationship between an optical proximity correction model and a test pattern library according to an embodiment of the present invention is shown. First, step S1 is performed to provide an optical proximity correction model 10, where the optical proximity correction model 10 performs simulation using a standard test pattern database 11, and the standard test pattern database 11 includes: a test pattern library 12 and a real chip pattern database 13.
The test pattern library 12 includes a plurality of data of test patterns based on design rules, including both dimension data and design parameters such as exposure intensity. In this embodiment, most of the test patterns are symmetrical patterns. The data in the real chip graphic database 13 includes: scanning electron microscope (scanning electron microscope, SEM) data collected from the actual on-chip pattern, and process parameter data such as exposure intensity during chip fabrication.
Step S2 is executed, as shown in fig. 3, in which a part of the test patterns in the test pattern library 12 is selected as a basic test pattern, the remaining test patterns in the test pattern library are used as standby test patterns, and the real chip patterns in the real chip pattern database are selected.
Specifically, the test patterns in the test pattern library 12 are distinguished, with one portion being a basic test pattern and the other portion being a standby test pattern. The real chip pattern data does not need to be distinguished and is used as a reference for performing difference comparison with the basic test pattern. And step S3, extracting feature vectors of the basic test pattern and the real chip pattern, expressing key feature data of the basic test pattern and the real chip pattern by the feature vectors, and calculating multistage differences between the feature vectors of the basic test pattern and the real chip pattern.
Specifically, in this embodiment, the step of extracting the feature vectors of the basic test pattern and the real chip pattern includes: and selecting key feature data of the basic test pattern and the real chip pattern, and representing the key feature data as feature vectors. The critical feature data is a series of parameters including critical feature dimensions.
The key characteristic data of the basic test pattern and the real chip pattern are selected in two modes: extracting key feature data by taking each basic test pattern and each real chip pattern as a reference; or extracting key characteristic data by taking key fragments in each basic test pattern and real chip pattern as a reference.
Here, extracting the key feature data with each of the basic test pattern and the real chip pattern as a reference refers to extracting the key feature data with the entire pattern as a reference. Extracting key feature data by taking key fragments in each basic test pattern and real chip pattern as a reference refers to extracting key feature data by taking the key fragments in the patterns instead of taking the whole pattern as the reference. For example, the key segments are graphic feature size measurement locations.
The key segments in each basic test graph and each real chip graph are used as a reference to extract key feature data, so that parameters contained in the key feature data can be more centralized, namely, focused data is more focused on features near the key segments, and therefore, the coverage between the current design and the local features focused in the process and the test graph and the real chip graph can be more embodied.
Therefore, in the present embodiment, the key feature data is extracted with the key segment in each of the basic test pattern and the real chip pattern as a reference, but in other embodiments, the key feature data may be extracted with each of the basic test pattern and the real chip pattern as a reference in combination with consideration of processing efficiency and data fidelity.
Referring to fig. 4, a schematic diagram of extracting key feature data on the test pattern in step S3 in fig. 2 is shown. In this embodiment, the test pattern 100 is a symmetrical pattern, and includes 5 symmetrical line patterns arranged in parallel, wherein the middle of the 5 lines is named as a first line pattern 101, and the key segment is a pattern feature size measurement position of the test pattern 100, that is, an edge bit line 103 of the first line pattern 101. The edge bit line 103 is a mark for positioning measurement after the test pattern is formed on the wafer, so that the edge bit line 103 is only a line without a width, and the width of the edge bit line 103 in this embodiment is only schematic. In this embodiment, the edge bit line 103 is located at the left edge of the first line pattern 101.
In this embodiment, the parameters of the feature vector, that is, the key feature data, include the line length, the line width, the line spacing, the density, the light intensity, the first derivative of the light intensity, the second derivative of the light intensity, the line end type, and the line length, the line width, the line spacing on the left side of the key segment, the line length, the line width, the line spacing on the right side of the key segment, and the like. The key feature data may influence the degree of change of the pattern after exposure and etching in the production process, so the parameters are all parameters required to be considered by the optical proximity correction model, and the range of the key feature data can be enlarged in order to better improve the coverage of the test pattern to the real chip pattern.
Accordingly, in this embodiment, the feature vector may be expressed as: (line length at key segment location, line width at key segment location, line spacing at key segment location, density at key segment location, light intensity first derivative at key segment location, light intensity second derivative at key segment location, line end type at key segment location, line length at key segment left, line width at key segment left, line spacing at key segment left and line length at key segment right, line width at key segment right).
In order to better describe the details of the above partial parameters, fig. 4 shows the partial parameters with the edge bit line 103 as a measurement reference, which mainly includes a line length L1 of the first line pattern 101 where the edge bit line 103 is located, a line width W1 of the first line pattern 101, a distance S1 between the first line pattern 101 and the adjacent second line pattern 102, a light intensity at a position where the edge bit line 103 is located, a first derivative of the light intensity, a second derivative of the light intensity, and a line end type of the first line pattern 101 where the edge bit line 103 is located.
The line end types comprise a middle line end, a line end and two line ends. The middle line end indicates that the key segment is positioned in the middle of a certain line, and the line extends beyond the two ends of the key segment; one line end indicates that the key segment is located at one end of a certain line, the line extends at the other end of the key segment, and two line ends indicate that the key segment covers two ends of the certain line, and the first line graph 101 line end type is two line ends as shown in fig. 4.
As described above, the parameters further include the size parameters of other lines adjacent to the first line pattern 101, and for the sake of brevity and clarity of this embodiment, the partial parameters of the second line pattern 102 on the left side of the first line pattern 101 are shown in fig. 4, including the line length L2 of the second line pattern 102, the line width W2 of the second line pattern 102, and the space S2 between the second line pattern 102 and the line pattern adjacent to the left side, where the above parameters may be respectively referred to as length_left, width_left, and space_left in the feature vector.
It should be noted that, in this embodiment, the edge bit line 103 is located at the left side of the first line pattern 101, and the selected position of the edge bit line 103 affects the measurement of the relevant dimension parameter and also affects the parameter values such as the light intensity, so that the benefit of locating the edge bit line 103 at the left side of the first line pattern 101 is the same as the conventional position of the measurement of the actual chip pattern, so that the simulation result is more accurate. However, the present invention does not limit the location of the edge bit line 103, and in other embodiments, the edge bit line 103 may be located on the right side of the first line pattern 101, where the extracted data such as the light intensity is slightly changed. In this embodiment, the density of the key segment in the parameters of the feature vector is a line density within a rated radius centered on the key segment, and the rated radius has a value ranging from 1 to 10 micrometers.
Correspondingly, in the embodiment, various parameters of the real chip pattern are extracted, and key segments in the real chip pattern are also taken as references to extract key feature data, but the invention is not limited to this.
The key segments are used as the reference to extract key feature data, so that the embodiment focuses on various parameters near the middle of the test pattern 100 and various parameters near the middle of the corresponding real chip pattern, and for simulating the real chip pattern, the reference meaning of various parameters near the middle of the test pattern is larger, the simulation effect is more concentrated, and the simulation of the local features of the real chip pattern is more accurate.
And extracting key feature data by taking each basic test pattern and the real chip pattern as a reference, namely extracting key feature data by taking the whole basic test pattern as a reference, wherein the extracted data is the average value of certain data of the test pattern, for example, extracting line width data by taking the whole test pattern 100 as a reference, the extracted line width data is the average line width of five line patterns in the test pattern 100, and the data extracted from the real chip pattern is the average line width in the real chip pattern by the same process.
In other embodiments, the key feature data may also be extracted for the test pattern with the key segments as references; for a real chip graph, extracting key feature data by taking the whole real chip graph as a reference; or extracting key feature data of the test pattern by taking the whole test pattern as a reference; and extracting key characteristic data of the real chip graph by taking the key fragments as a reference.
In order to further reduce the number of parameters in the feature vector, the embodiment removes parameters having less influence on the simulation effect, thereby calculating the importance nominal value of each parameter in the feature vector. In other embodiments, all of the parameters described above may be included in the feature vector.
In this embodiment, a machine learning method is used to calculate the nominal value of importance for each parameter in the feature vector. Specifically, a random forest classifier is adopted to train various parameters of a large number of test patterns as seed data, and the training steps comprise:
calling a test pattern from a test pattern library, calling a real chip pattern from a real chip pattern database, recording key feature data values of each test pattern or real chip pattern as a group of key feature data, wherein each group of key feature data comprises all parameters, each group of key feature data is represented as a feature vector, a label is added to each feature vector, and each feature vector and a label corresponding to each feature vector are used as training data of a random forest classifier.
As shown in table 1, each line in the X columns is a feature vector, that is, key feature data of a certain parameter graph, and each feature vector includes n parameters.
TABLE 1
The method for adding the label to the feature vector comprises two methods:
The first method for adding the tag comprises the following steps: and calculating model errors of parameters of each feature vector for each feature vector, wherein the model errors are error values of corresponding key feature data of the test pattern and the real chip pattern. If the model error is less than a threshold T, the label of the feature vector is marked as 0, and if the model error is greater than or equal to the threshold T, the label of the feature vector is marked as 1. For example, the threshold T for model error in table 1 is 1.
The tag adding method has the advantage that the obtained tag value is discrete, so that the random forest training efficiency is high. The results of this method are shown in Table 1 at column Y1.
Another method of tagging the feature vector is: for each feature vector, calculating the model error of each parameter of the feature vector, and directly marking the model error value as a label of the feature vector. The model error value is used as the label, so that the obtained label value is continuous, and the training method is a continuous regression method, so that the accuracy of random forest training is higher, and the obtained importance ranking is more accurate. The results of this method are shown in Table 1 in column Y2.
The first method of adding labels is adopted in this embodiment. It should be noted that, in this embodiment, for the hot spot obtained by the wafer verification, that is, some bad spots that are formed on the wafer and are easy to generate bad spots due to heat, the labels of the feature vectors of the test patterns may be all marked as 1.
And calculating the importance nominal value of each parameter in the feature vector according to the training data by adopting a random forest-based classifier. Specifically, based on model error data of a large number of corresponding key feature data of the test patterns and the real chip patterns, a random forest classifier is adopted, so that coefficients of influence of each parameter on the model error in the feature vector can be obtained, and the importance nominal value of each parameter in the feature vector is obtained.
Table 2 shows one result of random forest classifier training, with 10 parameters listed in table 2 as the nominal importance values, with parameter P6 being the highest importance. If the parameters with the highest 5 importance nominal values are selected as the parameters included in the feature vectors of the basic test pattern and the real chip pattern in step S3, the feature vectors may be expressed as (P6, P10, P5, P4, P8).
TABLE 2
In this embodiment, the number of parameters in the feature vector is reduced by obtaining the importance nominal value of each parameter in the feature vector according to the random forest classifier.
Next, a multi-level difference between the partial test pattern and the real chip pattern feature vector is calculated.
Specifically, in the present embodiment, the euclidean distance between the partial test pattern and the true chip pattern feature vector is calculated as a multi-level difference.
The step of calculating the euclidean distance between the partial test pattern and the true chip pattern feature vector comprises: setting the selected part of the test patterns as a first group of patterns, the selected real chip patterns as a second group of patterns, the feature vectors of the part of the test patterns as a first group of feature vectors, and the feature vectors of the real chip patterns as a second group of feature vectors, wherein Aki is the value of the kth parameter of the ith test pattern in the first group of feature vectors, bkj is the value of the kth parameter of the jth real chip pattern in the B group of feature vectors, dkij is the Euclidean distance between the test pattern Ai and the real chip pattern Bj based on the kth parameter, dkij can be expressed as
Dkij＝(Aki-Bkj)2
Euclidean distance Dkij represents the difference between the kth parameter of the ith test pattern in the first set of feature vectors and the kth parameter of the jth real chip pattern in the second set of feature vectors, the smaller this difference is, the higher the coverage of the ith test pattern in the first set of patterns to the jth real chip pattern in the second set of patterns is on the kth parameter.
The first group of feature vectors is provided to comprise m test patterns, the second group of feature vectors comprises n real chip patterns, each feature vector comprises l parameters, and if the importance nominal value of the kth parameter is set as lk, the Euclidean distance between each test pattern Ai and the real chip pattern Bj is as follows
The Euclidean distance between the first group of feature vectors and each real chip graph Bj isThe average Euclidean distance between the first set of feature vectors and the second set of feature vectors is/>
Therefore, the euclidean distance Dij can reflect the coverage of the test pattern Ai to the real chip pattern Bj, the euclidean distance DAj can reflect the coverage of the whole first group of test patterns to the real chip pattern Bj, and the average euclidean distance DAB can reflect the coverage of the whole first group of test patterns to the whole second group of test patterns.
And S4, evaluating the actual coverage of the basic test pattern to the real chip pattern according to the multi-level difference, and taking the real chip pattern with the actual coverage degree lower than the preset coverage degree as an uncovered pattern.
The step of evaluating the coverage degree of the test pattern on the real chip pattern comprises the following steps: a first threshold T i is defined for D Aj, a second threshold T a is defined for D AB, and coverage is characterized by the relationship of euclidean distance to the first and second thresholds T i and T a. Wherein the first threshold T i and the second threshold T a are threshold values of euclidean distance obtained based on a preset coverage (ideal coverage).
If D AB≤Ta and D Aj≤Ti, which represent smaller Euclidean distances, the differences are smaller, and accordingly the first set of patterns has ideal model coverage for the second set of patterns. For this case, the first set of patterns has ideal model coverage for the second set of patterns, and the first set of patterns can be directly added in its entirety to the underlying test pattern.
If D Aj>Ti, representing a larger Euclidean distance, is more diverse and, correspondingly, less covered, then all the second set of graphics of D Aj>Ti are classified as uncovered graphics.
And S5, selecting part of standby test patterns in the test pattern library according to the evaluation result, calculating the multistage difference between the part of standby test patterns and the feature vector of the uncovered pattern, sequencing the standby test patterns from small to large based on the multistage difference, and adding the standby test patterns which are sequenced and less than the preset ranking (for example, the first q) into the basic test patterns to realize the updating of the basic test patterns.
Specifically, if D Aj>Ti, classifying all the second set of graphics of D Aj>Ti as uncovered graphics, defining all the uncovered graphics as a third set of graphics, and re-selecting a part of the standby test graphics in the test graphics library as a fourth set of graphics. And calculating Euclidean distance between the third group of patterns and each fourth group of patterns, recording Euclidean distance D Cp between the third group of patterns and the p-th pattern in the fourth group of patterns, and adding the first q test patterns with the minimum Euclidean distance D Cp in the fourth group of patterns into the first group of patterns to serve as basic test patterns.
Therefore, according to the optimization method of the embodiment, the test pattern with better coverage for the real chip pattern can be added into the basic test pattern, and the accuracy of optical proximity correction is improved.
It should be noted that, in order to further improve the coverage of the test patterns on the real chip patterns, in this embodiment, after adding the top q standby test patterns after sorting to the basic test patterns, the following steps are performed again:
and S3, extracting feature vectors of the basic test pattern and the real chip pattern, and calculating multistage differences between the feature vectors of the partial test pattern and the real chip pattern.
And updating the preset coverage (ideal coverage), evaluating the actual coverage of the test pattern on the real chip pattern according to the multi-level difference, and taking the real chip pattern with the coverage degree lower than the ideal coverage as an uncovered pattern. Specifically, the standard of improving the ideal coverage is that in this embodiment, the first threshold T i and the second threshold T a are reduced, so that the range of the uncovered pattern is further enlarged, and a higher requirement is placed on the test pattern.
And re-selecting part of standby test patterns in the test pattern library according to the evaluation result, calculating the multistage difference between the part of standby test patterns and the feature vector of the uncovered pattern, sequencing the re-selected standby test patterns according to the multistage difference from small to large, and adding the top q standby test patterns which are sequenced and are smaller than the preset ranking into the basic test patterns.
And updating a standard test pattern database of the optical proximity correction model according to the basic test pattern. Namely, the test pattern with higher coverage obtained by the steps is added to a standard test pattern database of the optical proximity correction model. The standard test pattern database updated by the embodiment has higher coverage to the real chip pattern, and can improve the accuracy of optical proximity correction.
Through the repeated steps, the coverage of the screened test patterns on the real chip patterns is higher, and if the coverage is further improved, the steps can be repeated again.
The invention also provides an optical proximity correction system, which is characterized by comprising:
The model building unit 200 is configured to build an optical proximity correction model, where the optical proximity correction model is used for performing optical proximity correction, and the optical proximity correction model uses the standard test pattern database 201 to perform simulation.
And an optimizing unit 210, wherein the correcting unit optimizes the standard test pattern database based on the key feature data of the test pattern and the real chip pattern, so as to improve the coverage rate of the test pattern to the real chip pattern.
In this embodiment, the optimizing unit 210 includes:
The basic database module 211 includes a test pattern database and a real chip pattern database.
The data extraction module 212 is configured to select a part of the test patterns in the test pattern library as basic test patterns, select real chip patterns in the real chip pattern database, use the remaining test patterns in the test pattern library as standby test patterns, and extract feature vectors of the basic test patterns and the real chip patterns, where the feature vectors represent key feature data of the test patterns and the real chip patterns.
And the coverage evaluation module 213 is configured to calculate a multi-level difference between the feature vectors of the partial test pattern and the real chip pattern, evaluate the coverage degree of the basic test pattern on the real chip pattern according to the multi-level difference, and take the real chip pattern with the actual coverage degree lower than the preset coverage degree as the uncovered pattern.
And the feedback module 214 is configured to reselect a part of the standby test patterns in the test pattern library according to the evaluation result, calculate a multi-level difference between the part of the standby test patterns and the feature vector of the uncovered pattern, sort the reselected standby test patterns according to the multi-level difference from small to large, add the top q standby test patterns after sorting to sort the standby test patterns based on the multi-level difference from small to large, and add the standby test patterns after sorting smaller than a preset ranking to the basic test pattern so as to update the standard test pattern database of the optical proximity correction model.
Therefore, through the optimization of the optical proximity correction system, the test pattern with better coverage on the real chip pattern can be added into the standard test pattern database, and the accuracy of optical proximity correction is improved.
Therefore, the optical proximity correction system can improve the correction effect of the optical proximity correction, improve the efficiency of the optical proximity correction, and further improve the yield of chip production.
The embodiment of the invention also provides a mask plate, and the graph on the mask plate is obtained by the optical proximity correction system or the optical proximity correction method, so that the chip manufactured by the mask plate has higher yield.
The embodiment of the invention also provides equipment which can realize the optical proximity correction method provided by the embodiment of the invention by loading the optical proximity correction method in a program form.
An optional hardware structure provided by the device of the embodiment of the present invention includes: at least one memory and at least one processor. The memory stores one or more computer instructions.
The processor and memory may communicate via one or more of a communication bus or a communication module interface.
The processor may be a Central Processing Unit (CPU), or an Application-specific integrated Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.
The memory may comprise high-speed RAM memory or may further comprise non-volatile memory, such as at least one disk memory.
The memory stores one or more computer instructions that are executed by the processor to implement the optical proximity correction method provided by the embodiment of the invention.
It should be noted that, the implementation terminal device may further include other devices (not shown) that may not be necessary for the disclosure of the embodiment of the present invention; embodiments of the present invention will not be described in detail herein, as such other devices may not be necessary to an understanding of the present disclosure.
The embodiment of the invention also provides a storage medium which stores one or more computer instructions for realizing the optical proximity correction method provided by the embodiment of the invention.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (20)
1. An optical proximity correction method, comprising:
Providing an optical proximity correction model, wherein the optical proximity correction model adopts a standard test pattern database to carry out simulation, and the standard test pattern database comprises the following components: a test graphic library and a real chip graphic database;
Selecting part of test patterns in the test pattern library as basic test patterns, taking the rest test patterns in the test pattern library as standby test patterns, and selecting the real chip patterns in the real chip pattern database;
Extracting feature vectors of the basic test pattern and the real chip pattern, expressing key feature data of the basic test pattern and the real chip pattern by the feature vectors, and calculating multistage differences between the feature vectors of the basic test pattern and the real chip pattern;
According to the multi-level difference, evaluating the actual coverage of the basic test pattern on the real chip pattern, and taking the real chip pattern with the actual coverage lower than the preset coverage as an uncovered pattern, wherein the smaller the multi-level difference is, the higher the actual coverage is represented;
And selecting part of standby test patterns in the test pattern library according to the evaluation result, calculating the multistage difference between the part of standby test patterns and the uncovered pattern feature vector, sequencing the standby test patterns from small to large based on the multistage difference, and adding the standby test patterns which are sequenced and are smaller than the preset ranking into the basic test patterns so as to update the standard test pattern database of the optical proximity correction model.
2. The method of claim 1, wherein extracting feature vectors of the base test pattern and the real chip pattern comprises:
and selecting key feature data of the part of test patterns and the real chip patterns, and representing the key feature data as feature vectors.
3. The method of claim 2, wherein the step of selecting key feature data for the portion of the test pattern and the real chip pattern comprises: extracting key feature data by taking the whole of each part of test patterns and the whole of the real chip patterns as a reference; or extracting key characteristic data by taking key fragments in each of the partial test patterns and the real chip patterns as references.
4. The method of claim 3, wherein the key segment is a graphic feature size measurement location.
5. The method of claim 4, wherein the test pattern is a symmetrical pattern and the critical section is an edge bit line of a middle portion of the symmetrical pattern.
6. The method of claim 4, wherein the test pattern comprises a plurality of line patterns arranged in parallel, and the key segment is an edge bit line located in a middle line pattern.
7. The method of claim 6, wherein the step of selecting key feature data for the portion of the test pattern and the real chip pattern comprises: and calculating the importance nominal value of each parameter in the feature vector according to the input data by adopting a random forest classifier.
8. The method of claim 7, wherein the step of selecting key feature data for the portion of the test pattern and the real chip pattern further comprises: before calculating the importance nominal value of each parameter in the feature vector, calling a test pattern from a test pattern library and calling a real chip pattern from a real chip pattern database; recording key characteristic data values of each test pattern or real chip pattern as a group of key characteristic data; each group of key feature data is expressed as a feature vector, and a label is added to each feature vector; and taking each feature vector and the corresponding label as training data of the random forest classifier.
9. The method of claim 8, wherein the step of tagging each feature vector comprises: for each feature vector, calculating the model error of each parameter of the feature vector, marking the label of the feature vector as 0 if the model error is smaller than a threshold value T, and marking the label of the feature vector as 1 if the model error is larger than or equal to the threshold value T.
10. The method of claim 8, wherein the step of tagging each feature vector comprises: for each feature vector, calculating the model error of each parameter of the feature vector, and directly marking the model error value as a label of the corresponding feature vector.
11. The method of claim 1, wherein the step of calculating a multi-level difference between the partial test pattern and the true chip pattern feature vector comprises: and calculating the Euclidean distance between the partial test graph and the real chip graph feature vector, and taking the Euclidean distance as a multi-level difference.
12. The method of claim 11, wherein the step of calculating the euclidean distance between the partial test pattern and the true chip pattern feature vector comprises: setting the selected part of the test patterns as a first group of patterns, the selected real chip patterns as a second group of patterns, the feature vector set of the part of the test patterns as a first group of feature vectors, the feature vector set of the real chip patterns as a second group of feature vectors, and the Euclidean distance as D kij＝(Aki-Bkj)2, wherein A ki is the value of the kth parameter of the ith test pattern in the first group of feature vectors, B kj is the value of the kth parameter of the jth real chip pattern in the second group of feature vectors, and D kij is the Euclidean distance between the test pattern A i and the real chip pattern B j based on the kth parameter.
13. The method of claim 12, wherein the first set of feature vectors includes m test patterns, the second set of feature vectors includes n real chip patterns, each feature vector includes l parameters, and the Euclidean distance between each test pattern Ai and a real chip pattern Bj is given by k parameter's importance nominal value IkThe Euclidean distance between the whole first group of feature vectors and each real chip pattern Bj is/>The average Euclidean distance between the first set of feature vectors and the second set of feature vectors is/>
14. The method of claim 13, wherein the step of evaluating the degree of coverage of the real chip pattern by the test pattern comprises: a first threshold T i is defined for D Aj, a second threshold T a is defined for D AB, and if D AB≤Ta and all D Aj≤Ti, the first set of graphics have ideal model coverage for the second set of graphics.
15. The method of claim 13, wherein if D Aj>Ti, classifying all of the second set of patterns of D Aj>Ti as uncovered patterns, and defining all of the uncovered patterns as a third set of patterns, and re-selecting a portion of the spare test patterns in the test pattern library as a fourth set of patterns; and calculating Euclidean distance between the third group of patterns and each fourth group of patterns, recording Euclidean distance D Cp between the third group of patterns and the p-th pattern in the fourth group of patterns, and adding the first q test patterns with the minimum Euclidean distance D Cp in the fourth group of patterns into the first group of patterns to serve as basic test patterns.
16. The method of claim 1, wherein after adding the top q ordered standby test patterns to the base test pattern, the steps of:
Extracting feature vectors of the basic test pattern and the real chip pattern, and calculating multistage differences between the feature vectors of the partial test pattern and the real chip pattern;
updating ideal coverage, evaluating the coverage degree of the test pattern on the real chip pattern according to the multi-level difference, and taking the real chip pattern with the coverage degree lower than the ideal coverage degree as an uncovered pattern;
And re-selecting part of standby test patterns in the test pattern library according to the evaluation result, calculating the multi-level difference between the part of standby test patterns and the feature vector of the uncovered pattern, sequencing the re-selected standby test patterns according to the multi-level difference from small to large, and adding the first q sequenced standby test patterns into the basic test patterns.
17. An optical proximity correction system, comprising:
The model building unit is used for building an optical proximity correction model, wherein the optical proximity correction model is used for optical proximity correction, and the optical proximity correction model adopts a standard test pattern database for analog simulation;
The optimizing unit optimizes the standard test pattern database based on the key feature data of the test patterns and the real chip patterns so as to improve the coverage rate of the test patterns to the real chip patterns;
Wherein the optimizing unit includes:
The basic database module comprises a test graphic database and a real chip graphic database;
The data extraction module is used for selecting part of test patterns in the test pattern library as basic test patterns, selecting real chip patterns in the real chip pattern database, taking the rest test patterns in the test pattern library as standby test patterns, and extracting feature vectors of the basic test patterns and the real chip patterns, wherein the feature vectors represent key feature data of the test patterns and the real chip patterns;
The coverage evaluation module is used for calculating the multi-level difference between the basic test pattern and the real chip pattern feature vector, evaluating the coverage degree of the basic test pattern on the real chip pattern according to the multi-level difference, and taking the real chip pattern with the actual coverage lower than the preset coverage as an uncovered pattern, wherein the smaller the multi-level difference is, the higher the actual coverage is represented;
And the feedback module is used for selecting part of standby test patterns in the test pattern library according to the evaluation result, calculating the multistage difference between the part of standby test patterns and the feature vector of the uncovered pattern, sequencing the standby test patterns from small to large based on the multistage difference, and adding the standby test patterns which are sequenced and are smaller than the preset ranking into the basic test patterns so as to update the standard test pattern database of the optical proximity correction model.
18. A mask, wherein the pattern on the mask is obtained by the optical proximity correction system of claim 17.
19. An apparatus, comprising:
At least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executable by the processor to implement the optical proximity correction method of any one of claims 1-16.
20. A storage medium storing one or more computer instructions for implementing the optical proximity correction method of any one of claims 1-16.
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