CN114815494A - Optical proximity correction method and system, mask, equipment and storage medium - Google Patents
Optical proximity correction method and system, mask, equipment and storage medium Download PDFInfo
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Abstract
The invention provides an optical proximity correction method and system, a mask, equipment and a storage medium, wherein the optical proximity correction method comprises the following steps: the invention provides an optical proximity correction model method, an optical proximity correction system and a mask plate, wherein the optical proximity correction method comprises the following steps: providing an optical proximity correction model, wherein the optical proximity correction model adopts a standard test pattern database to carry out analog simulation, selects part of test patterns in the test pattern database as basic test patterns, and selects real chip patterns in the real chip pattern database; calculating the multi-level difference between the basic test pattern and the real chip pattern feature vector; and sequencing the standby test patterns from small to large based on the multi-level difference, and adding the standby test patterns which are sequenced and are smaller than the preset rank into the basic test pattern.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to an optical proximity correction method and system, a mask, equipment and a storage medium.
Background
With the continuous reduction of feature size and the increasing complexity of patterns, Optical Proximity Correction (OPC) technology has been widely applied to mask design at each critical level. The OPC method, which is currently most widely used, is a model-based OPC correction method, specifically, by building some type of physical model to simulate the interaction of light sources, optical components, light propagation, and optical matter, predicting the pattern profile and feature size on the wafer as accurately as possible.
A typical OPC model usually contains three sub-models: an optical model, a mask three-dimensional effect model (DDM) model, and a photoresist model. The optical model simulates the image projected onto the resist, the DDM model simulates the light waves in the mask, and the resist model simulates the developed resist profile. To accurately train these models, we need to first provide the model with seed parameters as the standard true data (ground true). Then the model adjusts the internal parameters thereof, so that the simulation result is closer to the standard real data. These seed parameters are test patterns based on design rules, which can usually represent the actual chips in the production process. However, it is often difficult to define the standard values of the test patterns and to evaluate the extent to which the test patterns can represent real chips in the future.
Disclosure of Invention
The invention aims to provide an optical proximity correction method, an optical proximity correction system and a mask plate, and optimize an optical proximity correction effect.
In order to solve the above problems, the present invention provides an optical proximity correction method, an optical proximity correction system, and a mask, where the method includes:
optionally, the step of extracting the feature vectors of the basic test pattern and the real chip pattern includes:
and selecting key characteristic data of the partial test pattern and the real chip pattern, and expressing the key characteristic data as a characteristic vector.
Optionally, the step of selecting the key feature data of the partial test pattern and the real chip pattern includes: extracting key characteristic data by taking each part of test graph and the whole real chip graph as a reference; or, extracting key feature data by taking the key segments in each part of the test pattern and the real chip pattern as a reference.
Optionally, the key segment is a graphic feature size measurement location.
Optionally, the test pattern is a symmetric pattern, and the key segment is an edge bit line in the middle of the symmetric pattern.
Optionally, the test pattern includes a plurality of line patterns arranged in parallel, and the key segment is an edge bit line located in a middle line pattern.
Optionally, the step of selecting the key feature data of the partial test pattern and the real chip pattern includes: and calculating the importance nominal value of each parameter in the feature vector according to the input data by adopting a random forest classifier.
Optionally, the step of selecting the key feature data of the partial test pattern and the real chip pattern further includes: before calculating the importance nominal value of each parameter in the feature vector, calling a test graph from a test graph library, and calling a real chip graph from a real chip graph database; recording the key characteristic data value of each test pattern or real chip pattern as a group of key characteristic data; each group of key feature data is expressed as a feature vector, and a label is added to each feature vector; and taking each feature vector and the corresponding label thereof as training data of the random forest classifier.
Optionally, the step of adding a label to each feature vector includes: and calculating the model error of each parameter of each feature vector, if the model error is less than a threshold value T, marking the label of the feature vector as 0, and if the model error is more than or equal to the threshold value T, marking the label of the feature vector as 1.
Optionally, the step of adding a label to each feature vector includes: for each feature vector, calculating the model error of each parameter of the feature vector, and directly marking the model error value as the label of the corresponding feature vector.
Optionally, the step of calculating the multi-level difference between the partial test pattern and the feature vector of the real chip pattern includes: and calculating the Euclidean distance between the part of test patterns and the feature vectors of the real chip patterns, and taking the Euclidean distance as the multi-level difference.
Optionally, the step of calculating the euclidean distance between the partial test pattern and the feature vector of the real chip pattern includes: setting the selected part of test patterns as a first group of patterns, setting the selected real chip patterns as a second group of patterns, collecting the feature vectors of the part of test patterns as a first group of feature vectors, collecting the feature vectors of the real chip patterns as a second group of feature vectors, and setting the Euclidean distance as D kij ＝(A ki -B kj ) 2 Where Aki is the value of the kth parameter of the ith test pattern in the first set of feature vectors, BKj is the value of the kth parameter of the jth real chip pattern in the second set of feature vectors, and Dkij is the Euclidean distance between the test pattern Ai and the real chip pattern Bj based on the kth parameter.
Optionally, the first group of feature vectors includes m test patterns, the second group of feature vectors includes n real chip patterns, each feature vector includes l parameters, and the importance nominal value of the kth parameter is Ik, so that the euclidean distance between each test pattern Ai and the real chip pattern Bj is
The Euclidean distance between the whole first group of feature vectors and each real chip graph Bj is
The average Euclidean distance between the whole first set of feature vectors and the whole second set of feature vectors is
Optionally, the step of evaluating the coverage degree of the test pattern on the real chip pattern includes: is D Aj Defining a first threshold value T i Is D of AB Defining a second threshold value T a If D is AB ≤T a And all D Aj ≤T i Then the first set of graphics has ideal model coverage for the second set of graphics.
Alternatively, if D Aj >T i Then D will be Aj >T i Classifying all the second group of graphs into uncovered graphs, defining all the uncovered graphs as a third group of graphs, and reselecting part of standby test graphs in the test graph library to serve as a fourth group of graphs; calculating Euclidean distance between the third group of graphs and each fourth group of graphs, and recording Euclidean distance D between the third group of graphs and the p-th graph in the fourth group of graphs Cp The Euclidean distance D in the graph of the fourth group Cp The smallest first q test patterns are added to the first set of patterns as base test patterns.
Optionally, after the sorted first q spare test patterns are added to the base test pattern, the following steps are performed again:
extracting the characteristic vectors of the basic test pattern and the real chip pattern, and calculating the multi-level difference between the characteristic vectors of the partial test pattern and the real chip pattern;
updating the ideal coverage, evaluating the coverage degree of the test pattern on the real chip pattern according to the multi-level difference, and taking the real chip pattern with the coverage degree lower than the ideal coverage as an uncovered pattern;
and according to the evaluation result, reselecting part of the standby test patterns in the test pattern library, calculating the multi-level difference between the part of the standby test patterns and the uncovered pattern feature vectors, sequencing the reselected standby test patterns according to the multi-level difference from small to large, and adding the top q standby test patterns after sequencing into the basic test pattern.
The present invention also provides an optical proximity correction system, comprising: the model establishing unit is used for establishing an optical proximity correction model, the optical proximity correction model is used for performing optical proximity correction, and the optical proximity correction model adopts a standard test pattern database for analog simulation; and the correcting unit optimizes the standard test pattern database based on the key characteristic data of the test pattern and the real chip pattern so as to improve the coverage rate of the test pattern on the real chip pattern.
Optionally, the optimizing unit includes: the basic database module comprises a test graph library and a real chip graph database; the data extraction module is used for selecting part of test patterns in the test pattern library as basic test patterns, selecting real chip patterns in the real chip pattern database, using the rest test patterns in the test pattern library as standby test patterns, and extracting the characteristic vectors of the basic test patterns and the real chip patterns, wherein the characteristic vectors represent key characteristic data of the test patterns and the real chip patterns; the coverage evaluation module is used for calculating the multi-level difference between the basic test graph and the characteristic vector of the real chip graph, evaluating the coverage degree of the basic test graph on the real chip graph according to the multi-level difference, and taking the real chip graph with the actual coverage degree lower than the preset coverage degree as an uncovered graph; and the feedback module is used for selecting part of the standby test patterns in the test pattern library according to the evaluation result, calculating the multi-level difference between the part of the standby test patterns and the uncovered pattern feature vectors, sequencing the standby test patterns from small to large based on the multi-level difference, and adding the standby test patterns which are sequenced and are smaller than the preset rank into the basic test patterns so as to update the standard test pattern database of the optical proximity correction model.
The invention also provides a mask plate, and the graph on the mask plate is obtained by the optical proximity correction system provided by the invention.
The present invention also provides an apparatus comprising: the optical proximity correction system comprises at least one memory and at least one processor, wherein the memory stores one or more computer instructions, and the one or more computer instructions are executed by the processor to realize the optical proximity correction method provided by the invention.
The present invention also provides a storage medium storing one or more computer instructions for implementing the optical proximity correction method provided by the present invention.
Compared with the prior art, the technical scheme of the invention has the following advantages: the method for the optical proximity correction model provided by the invention provides a method for evaluating the coverage degree of the test pattern on the real chip pattern, and the test pattern with higher coverage degree on the real chip pattern can be screened out and put into a standard test pattern library. The specific content comprises the steps of evaluating the coverage degree of the test graph on the real chip graph, and taking the real chip graph with the coverage degree lower than the ideal coverage degree as an uncovered graph; according to the evaluation result, part of the standby test patterns in the test pattern library are reselected, and the test patterns with ideal coverage are added into the basic test patterns; according to the basic test pattern obtained by the technical scheme, the standard test pattern database of the optical proximity correction model is updated, so that the coverage rate of the standard test pattern database on the real chip pattern can be increased, the correction effect of optical proximity correction is improved, the optical proximity correction efficiency is improved, and the yield of chip production is improved.
In an alternative of the invention, feature vectors of the basic test pattern and the real chip pattern are extracted, the feature vectors representing key feature data of the test pattern and the real chip pattern. The step of extracting the feature vectors of the test pattern and the real chip pattern comprises the following steps: selecting key characteristic data of a part of test patterns and real chip patterns, expressing the key characteristic data as characteristic vectors, and adopting the key characteristic data of the part of test patterns and the real chip patterns, wherein the steps comprise: and calculating the importance nominal value of each parameter in the feature vector according to the input data by adopting a random forest classifier. The random forest classifier is an advanced machine learning training method, can accurately measure the importance of each parameter, and can further effectively improve the effect of correcting the local abnormal problem of the characteristic dimension of the graph.
In an alternative aspect of the present invention, the step of calculating the multi-level difference between the partial test pattern and the real chip pattern feature vector includes: and calculating Euclidean distance between the feature vectors, wherein the Euclidean distance is used as a multi-level difference, namely after various key feature data of the test pattern and the real chip pattern are extracted as the feature vectors, the Euclidean distance between the test pattern and the real chip pattern is calculated according to corresponding parameters in the feature vectors, and the Euclidean distance is summarized into the Euclidean distance by referring to the weight of each parameter. Specifically, the test patterns are set as a group A patterns, the real chip patterns are set as a group B patterns, and the Euclidean distance between each test pattern and each real chip pattern, the Euclidean distance between each group A pattern and the whole group B patterns, and the Euclidean distance between the whole group A patterns and the whole group B patterns are respectively calculated. Therefore, the coverage degree of the current test pattern on a single real chip pattern and all real chip patterns can be completely expressed, and the test pattern with higher coverage degree on the real chip patterns can be conveniently selected subsequently.
Drawings
FIG. 1 is a schematic illustration of a test pattern of the prior art type;
FIG. 2 is a block diagram illustrating the steps of an embodiment of the optical proximity correction method of the present invention;
FIG. 3 is a diagram of a library of test patterns associated with an optical proximity correction model in accordance with one embodiment of the present invention;
FIG. 4 is a diagram illustrating key feature data extraction on a test pattern according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an embodiment of an optical proximity correction system of the present invention.
Detailed Description
The optical proximity correction model in the prior art has the problem of low optical proximity correction precision. The reasons for the above problems are analyzed in conjunction with prior art solutions.
Currently, methods of designing test patterns are based on test rules. By taking a one-dimensional graph as an example, if the step length is 10nm in the design rule, the standard dimension of the graph is defined to be from 40nm to 200nm, and the characteristic dimension takes values from 20nm, 25nm and 30 nm. In order to better verify the actual condition of the pattern, the pattern reference size range of the test pattern is generally designed to be from 30nm to 240nm based on the design rule, i.e., a value less than 30% of the minimum value of the pattern reference size range and greater than 20% of the maximum value of the pattern reference size range. As shown in fig. 1, it is a kind of test pattern in the prior art, in order to measure the feature size, the kind of test pattern is a symmetrical pattern, each symmetrical pattern includes a plurality of mutually parallel strip patterns, and fig. 1 shows three kinds of test patterns with different sizes. Taking the middle test pattern as an example, when collecting pattern size data, collecting the sum P1 of the line width and the pitch of the middle strip pattern as a pattern reference size, and the line width C1 of the middle strip pattern as a characteristic size, wherein the characteristic size of the middle strip pattern is used as a seed parameter when actually measuring the etched wafer.
However, the current design method of test patterns has the following disadvantages that a large number of asymmetric patterns exist in the patterns on a real chip, and the standard real data obtained from the test patterns are difficult to completely represent the real situation, in addition, the current test method needs to generate a large number of test patterns, but the OPC model can only perform simulation tests on a limited number of models, so the test patterns need to be screened, and an appropriate method is not available to prove that the screened test patterns can verify all situations in the real chip, therefore, the OPC model obtained by adopting seed parameter training may not perform well in a certain way, so that the current method has the problem that the result of optical proximity correction output is easy to fail.
Therefore, the invention provides an optical proximity correction method, which optimizes a standard test pattern database in an optical proximity correction model, improves the coverage rate of test patterns in the standard test pattern database on real chip patterns, improves the precision of optical proximity correction and further improves the yield of chip production.
Please refer to fig. 2, which is a flowchart illustrating an optical proximity correction method according to an embodiment of the present invention. In this embodiment, the optical proximity correction method includes the steps of:
step S1, providing an optical proximity correction model, wherein the optical proximity correction model adopts a standard test pattern database for simulation, and the standard test pattern database comprises: a test graph library and a real chip graph database;
step S2, selecting part of the test patterns in the test pattern library as basic test patterns, using the rest test patterns in the test pattern library as standby test patterns, and selecting real chip patterns in the real chip pattern database;
step S3, extracting the characteristic vectors of the basic test pattern and the real chip pattern, representing the key characteristic data of the basic test pattern and the real chip pattern by the characteristic vectors, and calculating the multi-level difference between the characteristic vectors of the basic test pattern and the real chip pattern;
step S4, according to the multi-level difference, evaluating the actual coverage of the basic test pattern to the real chip pattern, and taking the real chip pattern with the actual coverage lower than the preset coverage as an uncovered pattern;
and step S5, selecting part of the standby test patterns in the test pattern library according to the evaluation result, calculating the multi-level difference between the feature vectors of the part of the standby test patterns and the uncovered patterns, sequencing the standby test patterns from small to large based on the multi-level difference, and adding the standby test patterns which are sequenced and are smaller than the preset rank into the basic test patterns so as to update the standard test pattern database of the optical proximity correction model.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, a method of an OPC model is further described below with reference to the accompanying drawings.
Referring to FIG. 3, a diagram of an optical proximity correction model in relation to a library of test patterns according to an embodiment of the present invention is shown. First, step S1 is executed to provide an optical proximity correction model 10, where the optical proximity correction model 10 is simulated by using a standard test pattern database 11, and the standard test pattern database 11 includes: a test pattern library 12 and a real chip pattern database 13.
It should be noted that the test pattern library 12 includes a large amount of data of test patterns based on design rules, including both size data and design parameters such as exposure intensity. In this embodiment, most of the test patterns are symmetrical patterns. The data in the real chip graphics database 13 includes: scanning Electron Microscope (SEM) data collected from real on-chip patterns, and process parameter data such as exposure intensity during chip manufacturing.
Step S2 is executed, as shown in fig. 3, a part of the test patterns in the test pattern library 12 is selected as basic test patterns, the remaining test patterns in the test pattern library are used as standby test patterns, and the real chip patterns in the real chip pattern database are selected.
Specifically, the test patterns in the test pattern library 12 are distinguished, one part is used as a basic test pattern, and the other part is used as a spare test pattern. The real chip graphic data does not need to be distinguished and is used as a reference for carrying out difference comparison with the basic test graphic. And step S3 is executed, the feature vectors of the basic test pattern and the real chip pattern are extracted, the key feature data of the basic test pattern and the real chip pattern are represented by the feature vectors, and the multi-level difference between the feature vectors of the basic test pattern and the real chip pattern is calculated.
Specifically, in this embodiment, the step of extracting the feature vectors of the basic test pattern and the real chip pattern includes: and selecting key characteristic data of the basic test pattern and the real chip pattern, and expressing the key characteristic data as a characteristic vector. The critical feature data is a series of parameters including critical feature dimensions.
The key characteristic data of the basic test pattern and the real chip pattern are selected in two modes: extracting key characteristic data by taking each basic test pattern and each real chip pattern as a reference; or extracting key feature data by taking the key segments in each basic test pattern and the real chip pattern as a reference.
Here, extracting the key feature data with each of the basic test pattern and the real chip pattern as a reference means extracting the key feature data with the entire pattern as a reference. Extracting the key feature data by taking the key segments in each basic test pattern and each real chip pattern as a reference means that the key feature data is extracted by taking the key segments in the patterns as the reference instead of taking the whole patterns as the reference. For example, the key segment is a feature size measurement location.
The key feature data are extracted by taking the key segments in each basic test pattern and each real chip pattern as a reference, so that parameters contained in the key feature data can be more centralized, namely, concerned data are more concentrated on features near the key segments, and therefore, the coverage between the concerned local features in the current design and process and the test patterns and the real chip patterns can be more reflected.
Therefore, in the present embodiment, the key feature data is extracted with the key segment in each of the basic test pattern and the real chip pattern as a reference, but in other embodiments, the key feature data may be extracted with each of the basic test pattern and the real chip pattern as a reference in consideration of processing efficiency and data fidelity.
Referring to fig. 4, a schematic diagram of extracting key feature data on the test pattern in step S3 in fig. 2 is shown. In this embodiment, the test pattern 100 is a symmetric pattern, and includes 5 symmetric line patterns arranged in parallel, wherein the middle of the 5 line patterns is named as a first line pattern 101, and the critical segment is a pattern feature measurement position of the test pattern 100, i.e. an edge bit line 103 of the first line pattern 101. The edge bit line 103 is a mark for positioning measurement after a test pattern is formed on a wafer, so the edge bit line 103 is only a line without width, and the width of the edge bit line 103 in the figure is only an illustration. In the present embodiment, the edge bit line 103 is located at the left edge of the first line pattern 101.
In this embodiment, the parameters of the feature vector, that is, the critical feature data, include line length, line width, line spacing, density, light intensity, first derivative of light intensity, second derivative of light intensity, line end type at the position of the critical segment, and line length, line width, line spacing at the left side of the critical segment, and line length, line width, line spacing at the right side of the critical segment. The key characteristic data may affect the variation degree of the pattern after exposure and etching in the production process, so that the parameters are all parameters required to be considered by the optical proximity correction model, and the range of the key characteristic data can be expanded in order to better improve the coverage of the test pattern on the real chip pattern.
Accordingly, in this embodiment, the feature vector may be expressed as: (line length at the position of the key segment, line width at the position of the key segment, line spacing at the position of the key segment, density at the position of the key segment, light intensity at the position of the key segment, first derivative of light intensity at the position of the key segment, second derivative of light intensity at the position of the key segment, type of line end at the position of the key segment, line length at the left side of the key segment, line width at the left side of the key segment, line spacing at the left side of the key segment and line length at the right side of the key segment, line width at the right side of the key segment, line spacing at the right side of the key segment).
In order to better describe the details of the above partial parameters, fig. 4 shows the partial parameters based on the measurement of the edge bit line 103, which mainly includes a line length L1 of the first line pattern 101 where the edge bit line 103 is located, a line width W1 of the first line pattern 101, a distance S1 between the first line pattern 101 and the adjacent second line pattern 102, a light intensity at a position where the edge bit line 103 is located, a first derivative of the light intensity, a second derivative of the light intensity, and a type of line end of the first line pattern 101 where the edge bit line 103 is located.
The line end types comprise a medium line end, a line end and two line ends. The middle line end indicates that the key segment is positioned in the middle of a certain line, and the line extends beyond the two ends of the key segment; a line end indicates that the key snippet is located at one end of a line, the line extends at the other end of the key snippet, and a line end indicates that the key snippet covers both ends of the line, such as the line end type of the first line graph 101 shown in fig. 4 is a two-line end.
As described above, the parameters further include size parameters of other lines adjacent to the first line pattern 101, and in order to make this embodiment simpler and clearer, fig. 4 shows part of the parameters of the second line pattern 102 on the left side of the first line pattern 101, including the line length L2 of the second line pattern 102, the line width W2 of the second line pattern 102, and the distance S2 between the second line pattern 102 and the left adjacent line pattern, in the feature vector, the parameters may be respectively denoted as length _ left, width _ left, and space _ left.
It should be noted that, in the present embodiment, the edge bit line 103 is located at the left side of the first line pattern 101, the selected location of the edge bit line 103 may affect the measurement of the related dimension parameter and also affect the value of the light intensity isoparametric parameter, and the advantage of the edge bit line 103 located at the left side of the first line pattern 101 is the same as the conventional location for the measurement of the real chip pattern, so that the simulation result is more accurate. However, the present invention does not limit the selected position of the edge bit line 103, and in other embodiments, the edge bit line 103 may also be located at the right side of the first line pattern 101, and the extracted data such as light intensity may be slightly changed. It should be further noted that, in the present embodiment, in the parameters of the feature vector, the density at the key segment is a line density within a rated radius with the key segment as a center, and a numeric range of the rated radius is 1 to 10 micrometers.
Correspondingly, in this embodiment, various parameters of the real chip graph are extracted, and the key feature data is extracted by using the key segment in the real chip graph as a reference, but the present invention is not limited thereto.
The key segments are used as the reference to extract key feature data, so that the embodiment focuses on various parameters near the middle of the test pattern 100 and various parameters near the middle of the corresponding real chip pattern, and for simulating the real chip pattern, the reference significance of various parameters near the middle of the test pattern is larger, the simulation effect is more concentrated, and the simulation of the local features of the real chip pattern is more accurate.
And each basic test pattern and the real chip pattern are taken as a reference to extract key feature data, that is, the whole basic test pattern is taken as a reference to extract the key feature data, the extracted data is an average value of a certain class of data of the test pattern, for example, the whole test pattern 100 is taken as a reference to extract line width data, the extracted line width data is an average line width of five line patterns in the test pattern 100, and similarly, the data extracted for the real chip pattern is also an average line width in the real chip pattern, so that the advantage that the overall simulation of the test pattern on the real chip pattern is stronger, but errors may occur in local features is realized.
In other embodiments, key feature data can be extracted from the test pattern by taking the key segments as a reference; extracting key characteristic data of the real chip graph by taking the whole real chip graph as a reference; or extracting key characteristic data of the test pattern by taking the whole test pattern as a reference; and extracting key characteristic data of the real chip graph by taking the key fragments as a reference.
In order to further reduce the number of parameters in the feature vector, the embodiment removes the parameters that have less influence on the simulation effect, so as to calculate the importance nominal value of each parameter in the feature vector. In other embodiments, all of the above parameters may be included in the feature vector.
In the present embodiment, the importance nominal value of each parameter in the feature vector is calculated using a machine learning method. Specifically, a random forest classifier is adopted to train each parameter of a large number of test patterns as seed data, and the training step comprises the following steps:
calling a test pattern from a test pattern library, calling a real chip pattern from a real chip pattern database, recording key characteristic data values of each test pattern or real chip pattern into a group of key characteristic data, wherein each group of key characteristic data comprises all parameters, representing each group of key characteristic data into a characteristic vector, adding a label to each characteristic vector, and taking each characteristic vector and the corresponding label thereof as training data of a random forest classifier.
As shown in table 1, each row in the X column is a feature vector, i.e., key feature data of a certain parameter graph, and each feature vector includes n parameters.
TABLE 1
The method for adding the label to the feature vector comprises two methods:
the first method for adding the label comprises the following steps: and calculating the model error of each parameter of the feature vector for each feature vector, wherein the model error is the error value of corresponding key feature data of the test pattern and the real chip pattern. If the model error is less than a threshold T, the label of the feature vector is labeled 0, and if the model error is greater than or equal to the threshold T, the label of the feature vector is labeled 1. For example, the threshold T for model error in table 1 is 1.
The advantage of this method of adding labels is that the resulting label values are discrete, making random forest training more efficient. The results of this method are shown in table 1 in column Y1.
Another method for tagging the feature vector is: for each feature vector, calculating the model error of each parameter of the feature vector, and directly marking the model error value as the label of the feature vector. The advantage of using the model error value as the label is that the obtained label value is continuous, so the training method is a continuous regression method, the precision of random forest training is higher, and the obtained importance ranking is more accurate. The results of this method are shown in table 1 in column Y2.
The embodiment adopts the first method of adding labels. It should be noted that, in this embodiment, for hot spots obtained by wafer verification, that is, some bad spots actually formed on the wafer and prone to generating defects due to heat generation, the labels of the feature vectors of such test patterns may all be marked as 1.
And calculating an importance nominal value of each parameter in the feature vector according to the training data by adopting a random forest classifier. Specifically, based on a large number of test patterns and model error data of corresponding key feature data of real chip patterns, a random forest classifier is adopted to obtain coefficients of influence of parameters on model errors in feature vectors, and therefore the importance nominal value of each parameter in the feature vectors is obtained.
Table 2 shows one result of the random forest classifier training, and the nominal importance values of 10 parameters are listed in table 2, wherein the parameter P6 is the most important. If 5 parameters with the highest importance nominal values are selected as the parameters included in the feature vectors of the base test pattern and the real chip pattern extracted in step S3, the feature vectors may be represented as (P6, P10, P5, P4, P8).
TABLE 2
In the embodiment, the importance nominal value of each parameter in the feature vector is obtained according to the random forest classifier, and the number of the parameters in the feature vector is reduced.
Next, a multi-level difference between the partial test pattern and the real chip pattern feature vector is calculated.
Specifically, in the present embodiment, the euclidean distance between the partial test pattern and the feature vector of the real chip pattern is calculated, and the euclidean distance is taken as the multi-level difference.
The step of calculating the Euclidean distance between the part of test patterns and the feature vectors of the real chip patterns comprises the following steps: setting the selected part of test patterns as a first group of patterns, setting the selected real chip patterns as a second group of patterns, collecting the feature vectors of the part of test patterns as a first group of feature vectors, and collecting the feature vectors of the real chip patterns as a second group of feature vectors, wherein Aki is the value of the kth parameter of the ith test pattern in the first group of feature vectors, Bkj is the value of the kth parameter of the jth real chip pattern in the B group of feature vectors, Dkij is the Euclidean distance between the test pattern Ai based on the kth parameter and the real chip pattern Bj, and Dkij can be expressed as
D kij ＝(A ki -B kj ) 2
The Euclidean distance Dkij represents the difference between the kth parameter of the ith test pattern in the first group of feature vectors and the kth parameter of the jth real chip pattern in the second group of feature vectors, and the smaller the difference is, the higher the coverage of the jth real chip pattern in the second group of pattern by the ith test pattern in the first group of pattern on the kth parameter is.
Setting the first group of feature vectors to comprise m test patterns, setting the second group of feature vectors to comprise n real chip patterns, setting the importance nominal value of the kth parameter to be lk, and setting the Euclidean distance between each test pattern Ai and the real chip pattern Bj to be lk
The Euclidean distance between the whole first group of feature vectors and each real chip graph Bj is
The average Euclidean distance between the whole first set of feature vectors and the whole second set of feature vectors is
Therefore, the euclidean distance Dij can reflect the coverage of the test patterns Ai to the real chip patterns Bj, the euclidean distance DAj can reflect the coverage of the whole first group of test patterns to the real chip patterns Bj, and the average euclidean distance DAB can reflect the coverage of the whole first group of test patterns to the whole second group of test patterns.
And step S4 is executed, the actual coverage of the basic test pattern on the real chip pattern is evaluated according to the multi-level difference, and the real chip pattern with the actual coverage degree lower than the preset coverage degree is used as an uncovered pattern.
The step of evaluating the coverage degree of the test pattern on the real chip pattern comprises the following steps: is D Aj Defining a first threshold value T i Is D of AB Defining a second threshold value T a By Euclidean distance and a first threshold value T i And a second threshold value T a The relationship of (c) characterizes coverage. Wherein the first threshold value T i And a second threshold value T a Is a threshold value of euclidean distance obtained based on a preset coverage (ideal coverage).
If D is AB ≤T a And D Aj ≤T i The Euclidean distance is smaller, the difference is smaller, and accordingly the first group of graphs has ideal model coverage rate to the second group of graphs. For this case, the first set of patterns has ideal model coverage for the second set of patterns, and the first set of patterns can be added directly and in their entirety to the base test pattern.
If D is Aj >T i D, if the Euclidean distance is larger and the difference is larger, and the coverage rate is correspondingly lower Aj >T i All of the second set of graphics are classified as uncovered graphics.
And step S5 is executed, a part of spare test patterns in the test pattern library are selected according to the evaluation result, the multi-level difference between the part of spare test patterns and the uncovered pattern feature vectors is calculated, the spare test patterns are sorted from small to large based on the multi-level difference, the sorted spare test patterns smaller than the preset rank (for example, the first q) are added into the basic test patterns, and the basic test patterns are updated.
In particular, if D Aj >T i Then D will be Aj >T i Classifying all the second group of graphs into uncovered graphs, defining all the uncovered graphs as a third group of graphs, and reselecting part of spare test graphs in the test graph library as spare test graphsAnd a fourth set of graphics. Calculating Euclidean distance between the third group of graphs and each fourth group of graphs, and recording Euclidean distance D between the third group of graphs and the p-th graph in the fourth group of graphs Cp The Euclidean distance D in the graph of the fourth group Cp The smallest first q test patterns are added to the first set of patterns as base test patterns.
Therefore, according to the optimization method of the embodiment, the test pattern with better coverage of the real chip pattern can be added into the basic test pattern, and the precision of optical proximity correction is improved.
It should be noted that, in order to further improve the coverage of the test pattern on the real chip pattern, in this embodiment, after the top q sorted standby test patterns are added to the basic test pattern, the following steps are performed again:
and step S3, extracting the characteristic vectors of the basic test pattern and the real chip pattern, and calculating the multi-level difference between the characteristic vectors of the partial test pattern and the real chip pattern.
And updating the preset coverage (ideal coverage), evaluating the actual coverage of the test pattern on the real chip pattern according to the multi-level difference, and taking the real chip pattern with the coverage degree lower than the ideal coverage as an uncovered pattern. Specifically, the criterion of the ideal coverage is raised, and in the present embodiment, the first threshold T is set i And a second threshold value T a And the range of uncovered patterns is further expanded, and higher requirements are put forward on the test patterns.
And according to the evaluation result, re-selecting part of the spare test patterns in the test pattern library, calculating the multi-stage difference between the feature vectors of the part of the spare test patterns and the uncovered patterns, sequencing the re-selected spare test patterns according to the multi-stage difference from small to large, and adding the top q spare test patterns which are less than the preset ranking after sequencing into the basic test pattern.
And updating a standard test pattern database of the optical proximity correction model according to the basic test pattern. That is, the test pattern with higher coverage obtained in the above steps is added to the standard test pattern database of the optical proximity correction model. The standard test pattern database updated by the embodiment has higher coverage on the real chip pattern, and can improve the precision of optical proximity correction.
Through the repeated steps, the coverage of the screened test pattern on the real chip pattern is higher, and if the coverage is further improved, the steps can be repeated again.
The present invention also provides an optical proximity correction system, comprising:
the model establishing unit 200 is configured to establish an optical proximity correction model, where the optical proximity correction model is used for optical proximity correction, and the optical proximity correction model is subjected to analog simulation by using the standard test pattern database 201.
And the optimization unit 210 optimizes the standard test pattern database based on the key feature data of the test pattern and the real chip pattern so as to improve the coverage rate of the test pattern on the real chip pattern.
In this embodiment, the optimizing unit 210 includes:
the basic database module 211 includes a test graphics library and a real chip graphics database.
And the data extraction module 212 is configured to select a part of the test patterns in the test pattern library as basic test patterns, select real chip patterns in the real chip pattern database, use the remaining test patterns in the test pattern library as standby test patterns, and extract feature vectors of the basic test patterns and the real chip patterns, where the feature vectors represent key feature data of the test patterns and the real chip patterns.
The coverage evaluation module 213 is configured to calculate a multi-level difference between the feature vectors of the partial test pattern and the real chip pattern, evaluate a coverage degree of the basic test pattern on the real chip pattern according to the multi-level difference, and take the real chip pattern with an actual coverage degree lower than a preset coverage degree as an uncovered pattern.
And the feedback module 214 is configured to reselect a part of the standby test patterns in the test pattern library according to the evaluation result, calculate a multi-level difference between the part of the standby test patterns and the feature vectors of the uncovered patterns, sort the reselected standby test patterns according to the multi-level difference from small to large, add the top q sorted standby test patterns to the standby test patterns sorted based on the multi-level difference from small to large, add the standby test patterns sorted to be smaller than a preset rank to the basic test pattern, and update the standard test pattern database of the optical proximity correction model.
Therefore, through the optimization of the optical proximity correction system, the test pattern with better coverage of the real chip pattern can be added into the standard test pattern database, and the accuracy of optical proximity correction is improved.
Therefore, the optical proximity correction system can improve the correction effect of optical proximity correction, improve the efficiency of optical proximity correction and further improve the yield of chip production.
The embodiment of the invention also provides a mask plate, and the graph on the mask plate is obtained by the optical proximity correction system or the optical proximity correction method provided by the invention, so that the chip manufactured by the mask plate has higher yield.
The embodiment of the present invention further provides an apparatus, which can implement the optical proximity correction method provided by the embodiment of the present invention by loading the above optical proximity correction method in the form of a program.
An optional hardware structure provided by the device of the embodiment of the present invention includes: at least one memory and at least one processor. The memory stores one or more computer instructions.
The processor and memory may communicate over one or more of a communication bus or a communication module interface.
The processor may be a central processing unit CPU, or an application Specific Integrated circuit asic, or one or more Integrated circuits configured to implement embodiments of the present invention.
The memory may comprise high-speed RAM memory, and may also include non-volatile memory (non-volatile memory), such as at least one disk memory.
Wherein the memory stores one or more computer instructions that are executed by the processor to implement the optical proximity correction method provided by embodiments of the present invention.
It should be noted that the above terminal device may further include other devices (not shown) that may not be necessary for the disclosure of the embodiment of the present invention; these other components may not be necessary to understand the disclosure of embodiments of the present invention, which are not individually described herein.
Embodiments of the present invention also provide a storage medium storing one or more computer instructions for implementing the optical proximity correction method provided by the embodiments of the present invention.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (21)
1. A method of optical proximity correction, comprising:
providing an optical proximity correction model, wherein the optical proximity correction model is subjected to analog simulation by adopting a standard test pattern database, and the standard test pattern database comprises: a test graph library and a real chip graph database;
selecting part of test patterns in the test pattern library as basic test patterns, using the rest test patterns in the test pattern library as standby test patterns, and selecting real chip patterns in the real chip pattern database;
extracting feature vectors of the basic test pattern and the real chip pattern, representing key feature data of the basic test pattern and the real chip pattern by the feature vectors, and calculating the multi-level difference between the feature vectors of the basic test pattern and the real chip pattern;
evaluating the actual coverage of the basic test pattern on the real chip pattern according to the multi-level difference, and taking the real chip pattern with the actual coverage lower than the preset coverage as an uncovered pattern;
and selecting part of the standby test patterns in the test pattern library according to the evaluation result, calculating the multilevel difference between the part of the standby test patterns and the uncovered pattern feature vectors, sequencing the standby test patterns from small to large based on the multilevel difference, and adding the standby test patterns which are less than the preset rank after sequencing into the basic test patterns so as to update the standard test pattern database of the optical proximity correction model.
2. The method of claim 1, wherein the step of extracting feature vectors of the base test pattern and the real chip pattern comprises:
and selecting key characteristic data of the partial test pattern and the real chip pattern, and expressing the key characteristic data as a characteristic vector.
3. The method of claim 2, wherein the step of selecting the key feature data of the portion of the test pattern and the real chip pattern comprises: extracting key characteristic data by taking each part of test graph and the whole real chip graph as a reference; or, extracting key feature data by taking the key segments in each part of the test pattern and the real chip pattern as a reference.
4. The method of claim 3, wherein the key snippets are graphic feature dimension measurement locations.
5. The method of claim 4, wherein the test pattern is a symmetric pattern and the critical segments are edge bit lines in a middle portion of the symmetric pattern.
6. The method of claim 4, wherein the test pattern comprises a plurality of line patterns arranged in parallel, and the critical segments are edge bit lines located in a middle line pattern.
7. The method of claim 6, wherein the step of selecting key feature data of the portion of the test pattern and the real chip pattern comprises: and calculating the importance nominal value of each parameter in the feature vector by adopting a random forest classifier according to input data.
8. The method of claim 7, wherein the step of selecting key feature data of the portion of the test pattern and the real chip pattern further comprises: before calculating the importance nominal value of each parameter in the feature vector, calling a test graph from a test graph library, and calling a real chip graph from a real chip graph database; recording the key characteristic data value of each test pattern or real chip pattern as a group of key characteristic data; each group of key feature data is expressed as a feature vector, and a label is added to each feature vector; and taking each feature vector and the corresponding label thereof as training data of the random forest classifier.
9. The method of claim 8, wherein the step of tagging each feature vector comprises: and calculating the model error of each parameter of each feature vector, if the model error is less than a threshold value T, marking the label of the feature vector as 0, and if the model error is more than or equal to the threshold value T, marking the label of the feature vector as 1.
10. The method of claim 8, wherein the step of tagging each feature vector comprises: for each feature vector, calculating the model error of each parameter of the feature vector, and directly marking the model error value as the label of the corresponding feature vector.
11. The method of claim 1, wherein the step of calculating the multi-level difference between the partial test pattern and the real chip pattern feature vector comprises: and calculating the Euclidean distance between the part of test patterns and the feature vectors of the real chip patterns, and taking the Euclidean distance as the multi-level difference.
12. The method of claim 11, wherein the step of calculating the euclidean distance between the partial test pattern and the real chip pattern feature vectors comprises: setting the selected part of test patterns as a first group of patterns, setting the selected real chip patterns as a second group of patterns, collecting the feature vectors of the part of test patterns as a first group of feature vectors, collecting the feature vectors of the real chip patterns as a second group of feature vectors, and setting the Euclidean distance as D kij ＝(A ki -B kj ) 2 Wherein A is ki Is the value of the kth parameter of the ith test pattern in the first set of feature vectors, B kj Is the value of the kth parameter of the jth real chip graph in the second set of feature vectors, D kij Is based on the test pattern A of the kth parameter i And a real chip pattern B j The euclidean distance between.
13. The method of claim 12, wherein the first set of feature vectors comprises m test patterns, the second set of feature vectors comprises n real chip patterns, each feature vector comprises l parameters, and if the k-th parameter has a nominal importance value of Ik, the euclidean distance between each test pattern Ai and the real chip pattern Bj is defined as
The Euclidean distance between the whole first group of feature vectors and each real chip graph Bj is
The average Euclidean distance between the whole first set of feature vectors and the whole second set of feature vectors is
14. The method of claim 13, wherein the step of evaluating the degree of coverage of the real chip pattern by the test pattern comprises: is D Aj Defining a first threshold value T i Is D of AB Defining a second threshold value T a If D is AB ≤T a And all D Aj ≤T i Then the first set of graphics has ideal model coverage for the second set of graphics.
15. The method of claim 13, wherein if D is true Aj >T i Then D will be Aj >T i Classifying all the second group of graphs into uncovered graphs, defining all the uncovered graphs as a third group of graphs, and reselecting part of standby test graphs in the test graph library to serve as a fourth group of graphs; calculating Euclidean distance between the third group of graphs and each fourth group of graphs, and recording Euclidean distance D between the third group of graphs and the p-th graph in the fourth group of graphs Cp The Euclidean distance D in the graph of the fourth group Cp The smallest first q test patterns are added to the first set of patterns as base test patterns.
16. The method of claim 1, wherein after adding the sorted top q spare test patterns to the base test pattern, the following steps are repeated:
extracting the characteristic vectors of the basic test pattern and the real chip pattern, and calculating the multi-level difference between the characteristic vectors of the partial test pattern and the real chip pattern;
updating the ideal coverage, evaluating the coverage degree of the test pattern on the real chip pattern according to the multi-level difference, and taking the real chip pattern with the coverage degree lower than the ideal coverage as an uncovered pattern;
and according to the evaluation result, reselecting part of the standby test patterns in the test pattern library, calculating the multi-level difference between the part of the standby test patterns and the uncovered pattern feature vectors, sequencing the reselected standby test patterns according to the multi-level difference from small to large, and adding the top q standby test patterns after sequencing into the basic test pattern.
17. An optical proximity correction system, comprising:
the model establishing unit is used for establishing an optical proximity correction model, the optical proximity correction model is used for performing optical proximity correction, and the optical proximity correction model adopts a standard test pattern database for analog simulation;
and the correcting unit optimizes the standard test pattern database based on the key characteristic data of the test pattern and the real chip pattern so as to improve the coverage rate of the test pattern on the real chip pattern.
18. The optical proximity correction system of claim 17, wherein the optimization unit comprises:
the basic database module comprises a test graph library and a real chip graph database;
the data extraction module is used for selecting part of test patterns in the test pattern library as basic test patterns, selecting real chip patterns in the real chip pattern database, using the rest test patterns in the test pattern library as standby test patterns, and extracting the characteristic vectors of the basic test patterns and the real chip patterns, wherein the characteristic vectors represent key characteristic data of the test patterns and the real chip patterns;
the coverage evaluation module is used for calculating the multi-level difference between the basic test graph and the characteristic vector of the real chip graph, evaluating the coverage degree of the basic test graph on the real chip graph according to the multi-level difference, and taking the real chip graph with the actual coverage degree lower than the preset coverage degree as an uncovered graph;
and the feedback module is used for selecting part of the standby test patterns in the test pattern library according to the evaluation result, calculating the multi-level difference between the part of the standby test patterns and the uncovered pattern feature vectors, sequencing the standby test patterns from small to large based on the multi-level difference, and adding the standby test patterns which are sequenced and are smaller than the preset rank into the basic test patterns so as to update the standard test pattern database of the optical proximity correction model.
19. A mask wherein the pattern on the mask is obtained by the optical proximity correction system of claim 17 or 18.
20. An apparatus, comprising:
at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executable by the processor to implement the optical proximity correction method of any one of claims 1-16.
21. A storage medium storing one or more computer instructions for implementing the method of optical proximity correction according to any one of claims 1-16.
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