CN112214955A - Method for extracting power model parameters of very large scale integrated circuit chip - Google Patents
Method for extracting power model parameters of very large scale integrated circuit chip Download PDFInfo
- Publication number
- CN112214955A CN112214955A CN202011090721.8A CN202011090721A CN112214955A CN 112214955 A CN112214955 A CN 112214955A CN 202011090721 A CN202011090721 A CN 202011090721A CN 112214955 A CN112214955 A CN 112214955A
- Authority
- CN
- China
- Prior art keywords
- chip
- power model
- power
- extracting
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a method for extracting power model parameters of a very large scale integrated circuit chip, which comprises the steps of obtaining VCD files of all modules in chip design and extracting an RLC power model meeting design requirements; merging the RLC power supply models of each module into a Spice netlist of a full chip; based on static analysis of the insertion clock delays of all modules, adding the insertion clock delay of each module to a spice netlist of a full chip to obtain a chip-level power model; and constructing a system-level PDN by using the chip-level power supply model. The invention adopts a bottom-up method, firstly extracts the power model parameters of the bottom layer module, then adds the clock delay information when the module power models are combined, and finally obtains the power model of the whole chip. The method can quickly and accurately extract the power model parameters of the whole chip, and solves the problems of inaccurate model caused by slow extraction of the power model parameters of the whole chip and incapability of iteration in the traditional method.
Description
Technical Field
The invention belongs to the field of physical design of a very large scale integrated circuit, and particularly relates to a method for extracting power supply model parameters of a very large scale integrated circuit chip.
Background
As integrated circuit fabrication processes advance, the number of transistors integrated per unit area increases. For very large scale integrated circuit chips such as CPUs, the number of transistors has reached the billion scale. Resources and time consumed by extracting the power model parameters of the full chip on such a scale cannot be borne, and the model cannot be iterated quickly even if problems occur, so that how to extract the power model of the full chip quickly and accurately becomes a problem to be solved urgently. With a Power model of a full chip, a Power distribution Network (Power Delivery Network PDN) model can be built by combining a package and a circuit board Power parameter model, the Power integrity of the whole chip system is analyzed, and a solid foundation is provided for finding the problem of a Power distribution Network as soon as possible. As known by integrated circuit practitioners, a robust power distribution network is the basis for ensuring the normal operation of a chip system, so that the full-chip power model generation method has great engineering significance and economic value.
In the conventional full-chip power model extraction, all units need to be extracted from the hierarchy, and then the top layer is used for extracting the power model. However, in the design of the very large scale integrated circuit, the number of units reaches the level of billions, the resources and time consumed by the way of extracting the power model parameter base of the full chip on such a scale cannot be borne, and the model cannot be rapidly iterated even if the model is in a problem.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the invention provides a method for extracting power model parameters of a very large scale integrated circuit chip. The method can quickly and accurately extract the power model parameters of the whole chip, and solves the problems of inaccurate model caused by slow extraction of the power model parameters of the whole chip and incapability of iteration in the traditional method.
In order to solve the technical problems, the invention adopts the technical scheme that:
a method for extracting power model parameters of a very large scale integrated circuit chip comprises the following steps:
1) obtaining VCD files of all modules in the chip design;
2) extracting an RLC power supply model meeting design requirements according to the VCD files of all the modules;
3) merging the RLC power supply models of each module into a Spice netlist of a full chip;
4) based on static analysis of the insertion clock delays of all modules, adding the insertion clock delay of each module to a spice netlist of a full chip to obtain a chip-level power model;
5) and constructing a system-level PDN by using the chip-level power supply model.
Optionally, the step of step 2) comprises:
2.1) traversing all modules in the chip design to take one module as a current module, if the traversal is successful, skipping to execute the next step, otherwise, determining that the traversal is finished, and skipping to execute the step 3);
2.2) calculating the power consumption of the current module by using the VCD file of the current module, judging whether the power consumption of the current module meets the design requirement, if so, extracting the RLC power model of the current module, and skipping to execute the step 2.1); otherwise, modifying the power supply of the current module, and skipping to execute the step 2.2) to continue to calculate and judge the power consumption of the power supply.
Optionally, the step 2.2) of judging whether the power consumption of the current module meets the design requirement specifically means judging whether a static value, a dynamic value, a peak value, and a mean value of the power consumption of the current module meet the design requirement.
Optionally, the extracting of the RLC power model of the current module specifically refers to extracting parasitic parameters and current models of a resistance parameter R, an inductance parameter L, and a capacitance parameter C of the current module, and generating a power model with the resistance parameter R, the inductance parameter L, and the capacitance parameter C as the RLC power model.
Optionally, the step of step 3) comprises:
3.1) obtaining the information in the top netlist and counting the number of each module;
3.2) instantiating the power model of the module for a plurality of times according to the number of the modules;
3.3) all instantiated power models are connected in series according to the circuit model principle of RLC.
Optionally, the step of analyzing the insertion clock delays of all modules based on the static state in step 4) includes:
4.1) obtaining master clock ports of all modules and corresponding network names in a top layer;
4.2) calculating the insertion delay of the clock network according to the static time sequence analysis environment with the network name at the top layer;
and 4.3) corresponding the calculated clock network insertion delay with the modules, and making a table to obtain the insertion clock delays of all the modules.
Optionally, after the PDN network of the system level is built by using the power model of the chip level in step 5), a step of enabling the power impedance to satisfy the target impedance through cooperative optimization for the PDN network of the system level is further included.
In addition, the invention also provides a system for extracting power model parameters of a very large scale integrated circuit chip, which comprises a computer device, wherein the computer device is programmed or configured to execute the steps of the method for extracting the power model parameters of the very large scale integrated circuit chip.
In addition, the invention also provides a system for extracting the power model parameters of the very large scale integrated circuit chip, which comprises a computer device, wherein a memory of the computer device is stored with a computer program which is programmed or configured to execute the method for extracting the power model parameters of the very large scale integrated circuit chip.
Furthermore, the present invention provides a computer readable storage medium having stored therein a computer program programmed or configured to execute the method for extracting parameters of a power model of a very large scale integrated circuit chip.
Compared with the prior art, the invention has the following advantages:
1. the invention adopts a bottom-up method, firstly extracts the power model parameters of the bottom layer module, then adds the clock delay information when the module power models are combined, and finally obtains the power model of the whole chip. The method can quickly and accurately extract the power model parameters of the whole chip, and solves the problems of inaccurate model caused by slow extraction of the power model parameters of the whole chip and incapability of iteration in the traditional method.
2. The method of the invention has the advantages of less occupied resources, quick model construction, high accuracy, simple design and convenient operation. After a power supply model of the chip is obtained, a system-level power supply distribution network model is established, the target impedance is determined by simulating and analyzing the main frequency band range with concentrated current energy, and meanwhile, the performance of the chip, the packaging performance and the performance of a circuit board are optimized, so that the power supply impedance reaches the standard.
Drawings
FIG. 1 is a schematic diagram of the basic flow of the method of the present invention.
FIG. 2 is a schematic diagram of a chip module and a clock according to the present invention.
FIG. 3 is a schematic diagram of clock delay of the module according to the present invention.
FIG. 4 is a schematic diagram of a power model topology of a full chip according to the present invention.
Fig. 5 is a schematic diagram of a system level PDN network model in the present invention.
Detailed Description
In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments of the present invention is provided in conjunction with the preferred embodiments.
As shown in fig. 1, the method for extracting power model parameters of a very large scale integrated circuit chip of the present embodiment includes:
1) obtaining VCD files of all modules in the chip design;
2) extracting an RLC power supply model meeting design requirements according to the VCD files of all the modules;
3) merging the RLC power supply models of each module into a Spice netlist of a full chip;
4) based on static analysis of the insertion clock delays of all modules, adding the insertion clock delay of each module to a spice netlist of a full chip to obtain a chip-level power model;
5) and constructing a system-level PDN by using the chip-level power supply model.
In the method for extracting parameters of the power model of the very large scale integrated circuit chip according to the embodiment, a back-end design tool is used for performing power analysis on each module, and a clock port and an insertion delay of each module are captured and analyzed, so that a full chip layout (Floorplan) needs to be opened by the back-end design tool in advance for subsequent processing.
In this embodiment, the VCD (value change dump) file is a file format based on ASCII code and used for recording signal information generated by the EDA simulation tool, and the file is an existing format file in the chip design, so the specific format and the obtaining path thereof are not described in detail herein.
In this embodiment, the step 2) includes:
2.1) traversing all modules in the chip design to take one module as a current module, if the traversal is successful, skipping to execute the next step, otherwise, determining that the traversal is finished, and skipping to execute the step 3);
2.2) calculating the power consumption of the current module by using the VCD file of the current module, judging whether the power consumption of the current module meets the design requirement, if so, extracting the RLC power model of the current module, and skipping to execute the step 2.1); otherwise, modifying the power supply of the current module, and skipping to execute the step 2.2) to continue to calculate and judge the power consumption of the power supply.
In this embodiment, the step 2.2) of determining whether the power consumption of the current module meets the design requirement specifically means determining whether the static value, the dynamic value, the peak value, and the mean value of the power consumption of the current module meet the design requirement. In addition, one or more parameters or other types of indexes of power consumption can be selected as the judgment reference according to needs. Needless to say, the embodiment of the method for extracting the power model parameters of the very large scale integrated circuit chip does not depend on a specific judgment reference.
In this embodiment, the extracting of the RLC power model of the current module specifically means extracting parasitic parameters and current models of a resistance parameter R, an inductance parameter L, and a capacitance parameter C of the current module, and generating a power model with the resistance parameter R, the inductance parameter L, and the capacitance parameter C as the RLC power model.
In this embodiment, the step 3) includes:
3.1) obtaining the information in the top netlist and counting the number of each module;
3.2) instantiating the power model of the module for a plurality of times according to the number of the modules;
3.3) all instantiated power models are connected in series according to the circuit model principle of RLC.
In this embodiment, step 3) combines the RLC power MODELs of each module into a Spice netlist (power MODEL topology) of a full chip as shown in fig. 4, where Spice MODELs 1 to Spice MODELs 32 refer to the Spice MODELs 1 to module 32, respectively, and all instantiated power MODELs are connected in series to Spice MODEL TOPs (TOP netlist) according to the RLC circuit MODEL principle to form the Spice netlist (power MODEL topology) of the full chip.
The step of analyzing the inserted clock delays of all modules based on the static state in step 4) of this embodiment includes:
4.1) obtaining master clock ports of all modules and corresponding network names in a top layer;
4.2) calculating the insertion delay of the clock network according to the static time sequence analysis environment with the network name at the top layer;
and 4.3) corresponding the calculated clock network insertion delay with the modules, and making a table to obtain the insertion clock delays of all the modules. Fig. 2 shows an example of clock signal input paths of all modules in the chip design of this embodiment, and fig. 3 shows a schematic diagram of insertion clock delays of all modules, where the abscissa "time" is time, the ordinate "Block _ clock" is the clock of a module, blocks 1 to 32 respectively refer to clock signals of modules 1 to 32, and "Delay" refers to insertion clock delays of modules 1 to 32.
Fig. 5 shows an example of using a chip-level Power model to construct a system-level PDN Network in step 5) of this embodiment, where VRM represents a Power supply, and an output end of the Power supply is sequentially connected to a PCB model, a package Power parameter model, an on-chip capacitor, and an on-chip load (using dotted lines as separation lines, respectively), so as to jointly form a model of a Power Delivery Network PDN. Further, in this embodiment, after the system-level PDN network is built using the chip-level power model, a step of enabling the power impedance to satisfy the target impedance through cooperative optimization for the system-level PDN network is further included. And adding the insertion clock delay of each module into the spice netlist of the full chip to obtain a complete full-chip power model parameter, and constructing a system-level PDN (public data network) by using the full-chip power model to enable the power impedance to meet the target impedance through cooperative optimization.
In summary, the method for extracting parameters of the power model of the very large scale integrated circuit chip in the embodiment realizes the fastest extraction of the power model through the characteristics of module level, small scale, fast convergence and the like, and solves the problem that the power model of the full chip level cannot be extracted due to over scale; on the other hand, the problem that the current peak value is superposed due to the fact that the module-level power supply model jumps at the same moment is solved by analyzing and counting the insertion delay of the main clock of the module and inserting the clock delay into the module-level power supply model, and therefore the accuracy of the power supply model is improved.
In addition, the present embodiment also provides a system for extracting power model parameters of a very large scale integrated circuit chip, which includes a computer device programmed or configured to execute the steps of the aforementioned method for extracting power model parameters of a very large scale integrated circuit chip.
In addition, the present embodiment also provides a system for extracting power model parameters of a very large scale integrated circuit chip, which includes a computer device, wherein a memory of the computer device stores a computer program programmed or configured to execute the method for extracting power model parameters of a very large scale integrated circuit chip.
Furthermore, the present embodiment also provides a computer readable storage medium, in which a computer program is stored, the computer program being programmed or configured to execute the aforementioned method for extracting parameters of a power model of a very large scale integrated circuit chip.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is directed to methods, apparatus (systems), and computer program products according to embodiments of the application wherein instructions, which execute via a flowchart and/or a processor of the computer program product, create means for implementing functions specified in the flowchart and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (10)
1. A method for extracting power model parameters of a very large scale integrated circuit chip is characterized by comprising the following steps:
1) obtaining VCD files of all modules in the chip design;
2) extracting an RLC power supply model meeting design requirements according to the VCD files of all the modules;
3) merging the RLC power supply models of each module into a Spice netlist of a full chip;
4) based on static analysis of the insertion clock delays of all modules, adding the insertion clock delay of each module to a spice netlist of a full chip to obtain a chip-level power model;
5) and constructing a system-level PDN by using the chip-level power supply model.
2. The method of claim 1, wherein the step of step 2) comprises:
2.1) traversing all modules in the chip design to take one module as a current module, if the traversal is successful, skipping to execute the next step, otherwise, determining that the traversal is finished, and skipping to execute the step 3);
2.2) calculating the power consumption of the current module by using the VCD file of the current module, judging whether the power consumption of the current module meets the design requirement, if so, extracting the RLC power model of the current module, and skipping to execute the step 2.1); otherwise, modifying the power supply of the current module, and skipping to execute the step 2.2) to continue to calculate and judge the power consumption of the power supply.
3. The method for extracting power model parameters of very large scale integrated circuit chip according to claim 2, wherein the step 2.2) of determining whether the power consumption of the current module meets the design requirement specifically means determining whether the static value, the dynamic value, the peak value and the mean value of the power consumption of the current module meet the design requirement.
4. The method as claimed in claim 2, wherein the extracting of the RLC power model of the current module specifically refers to extracting parasitic parameters and current models of a resistance parameter R, an inductance parameter L and a capacitance parameter C of the current module, and generating the power model with the resistance parameter R, the inductance parameter L and the capacitance parameter C as the RLC power model.
5. The method of claim 1, wherein the step of step 3) comprises:
3.1) obtaining the information in the top netlist and counting the number of each module;
3.2) instantiating the power model of the module for a plurality of times according to the number of the modules;
3.3) all instantiated power models are connected in series according to the circuit model principle of RLC.
6. The method for extracting power model parameters of very large scale integrated circuit chip as claimed in claim 1, wherein the step of analyzing the inserted clock delays of all modules based on static state in step 4) comprises:
4.1) obtaining master clock ports of all modules and corresponding network names in a top layer;
4.2) calculating the insertion delay of the clock network according to the static time sequence analysis environment with the network name at the top layer;
and 4.3) corresponding the calculated clock network insertion delay with the modules, and making a table to obtain the insertion clock delays of all the modules.
7. The method for extracting power model parameters of very large scale integrated circuit chip according to claim 1, wherein after the step 5) of building a system level PDN network using the chip level power model, the method further comprises a step of making the power impedance meet the target impedance through cooperative optimization for the system level PDN network.
8. A system for extracting power model parameters of a very large scale integrated circuit chip, comprising a computer device, wherein the computer device is programmed or configured to perform the steps of the method for extracting power model parameters of a very large scale integrated circuit chip as claimed in any one of claims 1 to 7.
9. A system for extracting parameters of a power model of a very large scale integrated circuit chip, comprising a computer device, wherein a memory of the computer device stores a computer program programmed or configured to perform the method for extracting parameters of a power model of a very large scale integrated circuit chip as claimed in any one of claims 1 to 7.
10. A computer readable storage medium having stored thereon a computer program programmed or configured to perform the method of extracting power model parameters of a very large scale integrated circuit chip according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011090721.8A CN112214955B (en) | 2020-10-13 | 2020-10-13 | Method for extracting power model parameters of very large scale integrated circuit chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011090721.8A CN112214955B (en) | 2020-10-13 | 2020-10-13 | Method for extracting power model parameters of very large scale integrated circuit chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112214955A true CN112214955A (en) | 2021-01-12 |
| CN112214955B CN112214955B (en) | 2023-03-24 |
Family
ID=74053841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011090721.8A Active CN112214955B (en) | 2020-10-13 | 2020-10-13 | Method for extracting power model parameters of very large scale integrated circuit chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112214955B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080215303A1 (en) * | 2005-05-12 | 2008-09-04 | Nec Corporation | Method, Apparatus and Program for Creating a Power Pin Model of a Semiconductor Integrated Circuit |
| CN101763451A (en) * | 2010-01-01 | 2010-06-30 | 江苏华丽网络工程有限公司 | Method for establishing large-scale network chip verification platform |
| CN102236728A (en) * | 2010-04-30 | 2011-11-09 | 国际商业机器公司 | Integrated circuit design method and design simulation system |
| CN103207941A (en) * | 2013-04-27 | 2013-07-17 | 清华大学 | Transient analysis method and transient analysis system under integrated circuit power supply network full-parameter model |
| CN104376138A (en) * | 2013-08-15 | 2015-02-25 | 龙芯中科技术有限公司 | Time sequence determining method and device of integrated circuit chip |
| CN105807263A (en) * | 2016-03-28 | 2016-07-27 | 北京航空航天大学 | Structure implementing FPGA partial reconfiguration in radar signal processing and implementation method of structure |
| CN106817215A (en) * | 2016-12-07 | 2017-06-09 | 清华大学 | Supply network verification method on a kind of piece for bypass attack |
| CN110619168A (en) * | 2019-09-11 | 2019-12-27 | 上海高性能集成电路设计中心 | Super-large-scale chip information analysis method based on netlist |
-
2020
- 2020-10-13 CN CN202011090721.8A patent/CN112214955B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080215303A1 (en) * | 2005-05-12 | 2008-09-04 | Nec Corporation | Method, Apparatus and Program for Creating a Power Pin Model of a Semiconductor Integrated Circuit |
| CN101763451A (en) * | 2010-01-01 | 2010-06-30 | 江苏华丽网络工程有限公司 | Method for establishing large-scale network chip verification platform |
| CN102236728A (en) * | 2010-04-30 | 2011-11-09 | 国际商业机器公司 | Integrated circuit design method and design simulation system |
| CN103207941A (en) * | 2013-04-27 | 2013-07-17 | 清华大学 | Transient analysis method and transient analysis system under integrated circuit power supply network full-parameter model |
| CN104376138A (en) * | 2013-08-15 | 2015-02-25 | 龙芯中科技术有限公司 | Time sequence determining method and device of integrated circuit chip |
| CN105807263A (en) * | 2016-03-28 | 2016-07-27 | 北京航空航天大学 | Structure implementing FPGA partial reconfiguration in radar signal processing and implementation method of structure |
| CN106817215A (en) * | 2016-12-07 | 2017-06-09 | 清华大学 | Supply network verification method on a kind of piece for bypass attack |
| CN110619168A (en) * | 2019-09-11 | 2019-12-27 | 上海高性能集成电路设计中心 | Super-large-scale chip information analysis method based on netlist |
Non-Patent Citations (1)
| Title |
|---|
| 陈钊等: "《基于VSDP-XcitePI的片上耦合干扰的快速验证方法》", 《微电子技术》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112214955B (en) | 2023-03-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9703921B1 (en) | Naturally connecting mixed-signal power networks in mixed-signal simulations | |
| CN107533576A (en) | The reuse of effect is relied on for the layout of the extraction of the circuit design using master die | |
| US7159202B2 (en) | Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stages | |
| CN101539958A (en) | Method and device for designing standard cell library and integrated circuit | |
| KR102416490B1 (en) | Computer-implemented method and computing system for designing integrated circuit by considering process variations of wire | |
| TWI575394B (en) | Characterizing cell using input waveform geneartion considering different circuit topoloiges | |
| CN106066914A (en) | Consider the Static Timing Analysis Methodology of crosstalk effect | |
| US20070044058A1 (en) | Enabling efficient design reuse in platform ASICs | |
| CN105447215B (en) | Digital circuit design method and relevant system | |
| US6687889B1 (en) | Method and apparatus for hierarchical clock tree analysis | |
| CN107844678B (en) | Spice simulation method containing IP/Memory time sequence path | |
| CN115879406A (en) | Integrated circuit post-simulation method and device, electronic equipment and storage medium | |
| US7003753B2 (en) | Method of generating a physical netlist for a hierarchical integrated circuit design | |
| CN112214955B (en) | Method for extracting power model parameters of very large scale integrated circuit chip | |
| US8091052B2 (en) | Optimization of post-layout arrays of cells for accelerated transistor level simulation | |
| US7036096B1 (en) | Estimating capacitances using information including feature sizes extracted from a netlist | |
| CN107784185A (en) | The extracting method in pseudo- path, device and terminal device in a kind of gate level netlist | |
| US7945882B2 (en) | Asynchronous circuit logical verification method, logical verification apparatus, and computer readable storage medium | |
| US20220327269A1 (en) | Computing device and method for detecting clock domain crossing violation in design of memory device | |
| US20230237228A1 (en) | Computer readable recording medium with stored program and method of extracting parasitic parameters of a 3d ic thereof | |
| US20120304135A1 (en) | Method and apparatus for precision tunable macro-model power analysis | |
| Liu et al. | Wire length prediction-based technology mapping and fanout optimization | |
| Bakeer et al. | Analog, digital and mixed-signal design flows | |
| CN113688587B (en) | Method and device for generating circuit layout, computer equipment and storage medium | |
| US10474778B2 (en) | Systems and methods for top level integrated circuit design |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 300452 Building 5, Xin'an pioneer Plaza, Binhai New Area marine high tech Development Zone, Tianjin Applicant after: Feiteng Information Technology Co.,Ltd. Address before: 300452 Building 5, Xin'an pioneer Plaza, Binhai New Area marine high tech Development Zone, Tianjin Applicant before: TIANJIN FEITENG INFORMATION TECHNOLOGY Co.,Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |