CN112204166A - Permeation device and method for permeating permeable material - Google Patents

Permeation device and method for permeating permeable material Download PDF

Info

Publication number
CN112204166A
CN112204166A CN201980034922.5A CN201980034922A CN112204166A CN 112204166 A CN112204166 A CN 112204166A CN 201980034922 A CN201980034922 A CN 201980034922A CN 112204166 A CN112204166 A CN 112204166A
Authority
CN
China
Prior art keywords
precursor
permeable material
reaction chamber
vapor
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201980034922.5A
Other languages
Chinese (zh)
Other versions
CN112204166B (en
Inventor
K.K.卡切尔
E.费尔姆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASM IP Holding BV
Original Assignee
ASM IP Holding BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ASM IP Holding BV filed Critical ASM IP Holding BV
Publication of CN112204166A publication Critical patent/CN112204166A/en
Application granted granted Critical
Publication of CN112204166B publication Critical patent/CN112204166B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45559Diffusion of reactive gas to substrate
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04Coating on selected surface areas, e.g. using masks
    • C23C16/045Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24Deposition of silicon only
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/32Carbides
    • C23C16/325Silicon carbide
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • C23C16/401Oxides containing silicon
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • C23C16/45527Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers

Abstract

An infiltration apparatus is disclosed. The infiltration apparatus may include: a reaction chamber constructed and arranged to receive at least one substrate having a permeable material thereon; a first precursor source constructed and arranged to provide a vapor of a first precursor comprising a silicon compound; a precursor distribution system and a removal system constructed and arranged to provide vapor of the first precursor from the first precursor source to the reaction chamber and to remove vapor of the first precursor from the reaction chamber; and a sequence controller operably connected to the precursor distribution system and removal system and comprising a memory, the memory being programmed to perform infiltration of the permeable material when run on the sequence controller by; activating the precursor distribution system and removal system to provide the vapor of the first precursor to the permeable material on the substrate in the reaction chamber, thereby causing the permeable material on the substrate in the reaction chamber to be permeated with silicon atoms by reaction of the vapor of the first precursor with the permeable material. Infiltration methods and semiconductor device structures including the infiltrated material are also provided.

Description

Permeation device and method for permeating permeable material
Technical Field
The present disclosure relates generally to an infiltration apparatus, and in particular, to an infiltration apparatus configured for infiltrating a permeable material with silicon atoms. The present disclosure also generally relates to methods of permeating a permeable material.
Background
As the geometry of semiconductor device structures becomes smaller, different patterning techniques have emerged. These techniques include self-aligned multi-patterning, spacer-defined quad patterning, deep ultraviolet lithography (DUV), extreme ultraviolet lithography (EUV), and DUV/EUV combination spacer-defined double patterning. In addition, direct self-assembly (DSA) has been considered as an option for future lithography applications.
The patterning techniques described above may utilize at least one polymer resist disposed on a substrate to enable high resolution patterning of the substrate. To meet both high resolution and low line edge roughness requirements, the polymer resist can typically be a thin layer. However, such thin polymer resists may have several disadvantages. In particular, high resolution polymer resists may have low etch resistance, i.e., high etch rates. This low etch resistance of the polymer resist makes transfer of the patterned resist to the underlying layer more difficult. As advanced high resolution polymer resists require further down-sizing, the problem of low etch resistance becomes greater, as the polymer resists may have even lower etch resistance and etch selectivity.
In some applications, it may be advantageous to transfer the pattern of the polymer resist to a hard mask. A hard mask is a material that is used as an etch mask in semiconductor processing in place of or in addition to a polymer or other organic "soft" resist material. The hard mask material typically has a higher etch resistance and a higher etch selectivity than the polymer resist. However, even a hard mask may have an etch rate that may need to be optimized.
Accordingly, there is a need for polymer resists and hard masks with advanced characteristics, such as improved etch resistance.
Disclosure of Invention
This summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in more detail below in the detailed description of example embodiments of the disclosure. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
In some embodiments, an osmosis apparatus is disclosed. The permeation device can include a reaction chamber constructed and arranged to receive at least one substrate having a permeable material disposed thereon; a first precursor source constructed and arranged to provide a vapor of a first precursor comprising a silicon compound; a precursor distribution system and a removal system constructed and arranged to provide vapor of a first precursor from a first precursor source to the reaction chamber and to remove the vapor of the first precursor from the reaction chamber; and a sequence controller operably connected to the precursor distribution system and the removal system and comprising a memory, the memory being provided with a program to perform infiltration of the permeable material when run on the sequence controller by; the precursor distribution and removal system is activated to provide a vapor of the first precursor to a permeable material on the substrate in the reaction chamber, thereby causing the permeable material on the substrate in the reaction chamber to be permeated with silicon atoms by reaction of the vapor of the first precursor with the permeable material.
In some embodiments, a method of making a porous article is providedA method of permeating a permeable material. The method may comprise: providing a substrate having a permeable material disposed thereon in a reaction chamber; providing a first precursor comprising a silicon compound to a permeable material in a reaction chamber for a first period of time (T)1) Thereby causing permeable material on the substrate in the reaction chamber to be permeated by silicon atoms; and purging the reaction chamber for a second period of time (T)2)。
For the purpose of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
All such embodiments are intended to be within the scope of the disclosed invention. These and other embodiments will become apparent to those skilled in the art from the following detailed description of certain embodiments having reference to the accompanying drawings, the invention not being limited to any particular embodiment disclosed.
Drawings
While the specification concludes with claims particularly pointing out and distinctly claiming what are regarded as embodiments of the present disclosure, the advantages of embodiments of the disclosure may be more readily ascertained from the description of certain examples of embodiments of the disclosure when read in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates a non-limiting exemplary infiltration apparatus according to an embodiment of the present disclosure;
FIG. 2 illustrates a non-limiting exemplary process flow demonstrating a method for infiltrating a permeable material with a first precursor in accordance with embodiments of the present disclosure;
FIG. 3 illustrates an additional non-limiting exemplary process flow demonstrating a method for infiltrating a permeable material with a first precursor and a second precursor in accordance with embodiments of the present disclosure;
FIG. 4 illustrates a non-limiting exemplary process flow demonstrating a method for Sequential Infiltration Synthesis (SIS) in accordance with an embodiment of the present disclosure;
FIG. 5 illustrates additional non-limiting exemplary flow diagrams demonstrating additional methods for sequential osmosis synthesis (SIS) in accordance with embodiments of the present disclosure;
FIG. 6 shows an x-ray photoelectron spectrum (XPS) obtained from an infiltration material according to an embodiment of the present disclosure;
FIG. 7 shows a Secondary Ion Mass Spectrum (SIMS) obtained from an infiltrated material according to an embodiment of the disclosure; and
fig. 8 illustrates a cross-sectional schematic view of a semiconductor device structure including a infiltrated material, in accordance with an embodiment of the present disclosure.
Detailed Description
Although certain embodiments and examples are disclosed below, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments and/or uses of the invention and obvious modifications and equivalents thereof. Therefore, it is intended that the scope of the present disclosure should not be limited by the particular disclosed embodiments described below.
Moreover, the illustrations presented herein are not meant to be actual views of any particular material, structure, or apparatus, but are merely idealized representations which are employed to describe the embodiments of the present disclosure.
As used herein, the term "substrate" may refer to any underlying material or materials that may be used, or upon which a device, circuit, or film may be formed.
As used herein, the term "permeable material" may refer to any material into which additional species (such as atoms, molecules, or ions) may be introduced.
As used herein, the term "semiconductor device structure" may refer to any portion of a processed or partially processed semiconductor structure that is, includes, or defines at least a portion of an active or passive component of a semiconductor device to be formed on or in a semiconductor substrate. For example, semiconductor device structures may include active and passive components of an integrated circuit, such as transistors, memory elements, transducers, capacitors, resistors, conductive lines, conductive vias, and conductive contact pads.
A number of example materials are given throughout the examples of the present disclosure, it is noted that the chemical formulas given for each example material should not be construed as limiting, and that the non-limiting example materials given should not be limited to the example stoichiometry.
The present disclosure includes a infiltration apparatus and infiltration method that may be used to increase the etch resistance of materials (e.g., polymer resists and hard mask materials) used as etch masks in semiconductor device fabrication processes.
Infiltration processes such as Sequential Infiltration Synthesis (SIS) have been demonstrated to improve the etch resistance of various organic materials by modifying the organic materials with inorganic protective components. For example, the SIS process utilizes alternating exposures of a polymeric resist to a vapor phase precursor that permeates the organic resist material to form a protective component within the resist layer. SIS processes and their uses are described in U.S. patent application No. 2012/0241411, and are incorporated herein by reference. Thus, combining the infiltration process with high resolution polymer resist and hardmask patterning may provide benefits not previously seen in previous methods, such as the method described in U.S. patent application No. 2014/0273514.
Previous infiltration processes typically involved the introduction of metal oxides (e.g., alumina (Al)2O3) ) penetrate into the high resolution polymer resist. For example, Trimethylaluminum (TMA) and water (H) are carried out at a substrate temperature of 90 ℃2O) may cause aluminum oxide to penetrate into a high resolution polymer resist disposed on a substrate. However, in some semiconductor device applications, it may not be desirable to utilize metal oxides as a permeation material. For example, using alumina as a percolating material may produce undesirable memory effects in plasma etching equipment, and in addition, the remaining alumina may be difficult to remove. Accordingly, there is a need for infiltration apparatuses and processes that can infiltrate replacement materials/species into high resolution polymer resists and hard mask materials.
Accordingly, in some embodiments of the present disclosure, an osmosis apparatus may be disclosed. In some embodiments, the infiltration apparatus may comprise: a reaction chamber constructed and arranged to receive at least one substrate having a permeable material thereon; a first precursor source constructed and arranged to provide a vapor of a first precursor comprising a silicon compound; a precursor distribution system and a removal system constructed and arranged to provide vapor of a first precursor from a first precursor source to the reaction chamber and to remove the vapor of the first precursor from the reaction chamber; and a sequence controller operably connected to the precursor distribution system and the removal system and comprising a memory, the memory being provided with a program to perform infiltration of the permeable material when run on the sequence controller by; the precursor distribution system and the removal system are activated to provide a vapor of the first precursor to a permeable material on the substrate in the reaction chamber, thereby causing the permeable material on the substrate in the reaction chamber to be permeated with silicon atoms by a reaction of the vapor of the first precursor with the permeable material.
A non-limiting example of an osmosis apparatus of the present disclosure is shown in fig. 1, which contains a schematic diagram of an exemplary osmosis apparatus 100 according to an embodiment of the present disclosure. It should be noted that the permeation device 100 shown in fig. 1 is a simplified schematic version of an exemplary permeation device and does not contain every element, i.e., every valve, gas line, heating element, reactor assembly, etc., such as may be used in the manufacture of the permeation device of the present disclosure. The permeation device as shown in fig. 1 provides key features of the permeation device to provide one of ordinary skill with sufficient disclosure to understand embodiments of the present disclosure.
The exemplary permeation device 100 can include a reaction chamber 102 constructed and arranged to house at least one substrate 104 having a permeable material 106 disposed thereon.
Reaction chambers that can be used to permeate permeable materials can be used for the permeation processes described herein. Such reaction chambers may include reaction chambers configured for Atomic Layer Deposition (ALD) processes, and reaction chambers configured for Chemical Vapor Deposition (CVD) processes. According to some embodiments, a showerhead reaction chamber may be used. According to some embodiments, a cross-flow, batch, mini-batch, or spatial ALD reaction chamber may be used.
In some embodiments of the present disclosure, a batch reaction chamber may be used. In some embodiments, a vertical batch reaction chamber may be used. In other embodiments, the batch reaction chamber comprises a small batch reactor configured to hold 10 or fewer wafers, 8 or fewer wafers, 6 or fewer wafers, 4 or fewer wafers, or 2 or fewer wafers.
The infiltration process described herein may optionally be performed in a reactor or reaction chamber connected to a cluster tool. In a cluster tool, because each reaction chamber is dedicated to one process type, the temperature of the reaction chamber in each module can be kept constant, which will increase throughput compared to a reactor in which the substrate is heated up to the process temperature before each run. In addition, the time to change the chamber pressure to the desired process pressure level between substrates can be reduced in a cluster tool. In some embodiments of the present disclosure, both the infiltration process and the etch process may be performed in a cluster tool comprising a plurality of reaction chambers, wherein each individual reaction chamber may be used to expose the substrate to a separate precursor gas/plasma chemistry, and the substrate may be transferred between different reaction chambers for exposure to multiple precursor gases and/or plasma chemistries, the transfer of the substrate being performed under a controlled environment to prevent oxidation/contamination of the substrate. In some embodiments of the present disclosure, the infiltration process and the etching process may be performed in a cluster tool comprising a plurality of reaction chambers, wherein each individual reaction chamber may be configured to heat the substrate to a different temperature.
A separate infiltration apparatus may be utilized that includes a reaction chamber that may be constructed and arranged to perform only the infiltration process and may be equipped with a load-lock. In this case, there is no need to cool the reaction chamber between each operation.
At least one substrate 104 may be disposed within the reaction chamber 102, with a permeable material 106 disposed thereon, i.e., disposed on an upper surface of the substrate 104. In some embodiments of the present disclosure, the substrate 104 may comprise a planar substrate (as shown in fig. 1) or a patterned substrate. The substrate 104 may comprise one or more materials including, but not limited to, silicon (Si), germanium (Ge), germanium tin (GeSn), silicon germanium (SiGe), silicon germanium tin (SiGeSn), silicon carbide (SiC), or a group III-V semiconductor material, such as gallium arsenide (GaAs), gallium phosphide (GaP), or gallium nitride (GaN). In some embodiments of the present disclosure, the substrate 104 may comprise an engineered substrate in which a surface semiconductor layer is disposed over a bulk support with an intervening Buried Oxide (BOX) disposed therebetween.
The patterned substrate may comprise a substrate that may include semiconductor device structures formed in or on a surface of the substrate, e.g., the patterned substrate may comprise partially fabricated semiconductor device structures such as, for example, transistors and/or memory elements. In some embodiments, the substrate may contain a monocrystalline surface and/or one or more secondary surfaces, which may comprise non-monocrystalline surfaces, such as polycrystalline surfaces and/or amorphous surfaces. The monocrystalline surface may comprise, for example, one or more of the following: silicon (Si), silicon germanium (SiGe), germanium tin (GeSn), or germanium (Ge). The polycrystalline or amorphous surface may comprise a dielectric material such as an oxide, oxynitride or nitride, for example silicon oxide and silicon nitride.
In some embodiments of the present disclosure, the permeable material 106 is disposed on the substrate 104, i.e., the permeable material is disposed on an upper surface of the substrate 104. The permeable material 106 may comprise any material into which additional species may be introduced that, when introduced into the permeable material 106, may increase the etch resistance of the permeable material 106. In some embodiments of the present disclosure, the permeable material 106 may comprise at least one of a polymer resist, such as a photoresist, an Extreme Ultraviolet (EUV) resist, an immersion photoresist, a Chemically Amplified Resist (CAR), or an electron beam resist (e.g., poly (methyl methacrylate) (PMMA)). In some embodiments of the present disclosure, the permeable material 106 may comprise a porous material, such as a microporous and/or nanoporous material, including porous materials such as spin-on-glass (SOG) and spin-on-carbon (Soc). In some embodiments of the present disclosure, the permeable material 106 may comprise one or more hard mask materials including, but not limited to, silicon oxide, silicon nitride, and silicon oxynitride.
The permeable material 106 may comprise a patterned permeable material comprising one or more permeable members that may be transferred into an underlying substrate during a subsequent etching process. The permeable member may comprise any geometric body that may be formed depending on the exposure and related development process, and may include, but is not limited to, wire members, frame members, apertured members, and circular members.
The substrate 104 may be disposed in the reaction chamber 102 and held in place by a pedestal 108 configured to hold at least one substrate thereon. In some embodiments of the present disclosure, the infiltration processes disclosed herein may utilize processes that heat the substrate 104 and associated permeable material 106 to a suitable process temperature. Thus, the pedestal 108 may include one or more heating elements 110 that may be configured to heat the substrate 104 having the permeable material 106 disposed thereon to a temperature greater than approximately 0 ℃, or greater than approximately 100 ℃, or greater than approximately 200 ℃, or greater than approximately 300 ℃, or greater than approximately 400 ℃, or even greater than approximately 450 ℃.
In some embodiments of the present disclosure, an exemplary permeation device 100 may include a gas delivery system 112, which may further include one or more precursor sources 114A and 114B constructed and arranged to provide vapors of multiple precursors and distribute associated vapors to the reaction chamber 102. The gas delivery system 112 may also include a source vessel 116 configured to store and dispense purge gas that may be used in the purge cycle of the exemplary permeation process described herein. The gas delivery system 112 may also include a reactant source vessel 118 configured to contain and distribute reactants to the reaction chamber 102 for use in the exemplary permeation processes described herein. As a non-limiting example, the permeation device 100 can include a first precursor source 114A constructed and arranged to provide a vapor of a first precursor comprising a silicon compound. In some embodiments, the first precursor source 114A can comprise a first precursor vaporizer constructed and arranged to vaporize a first precursor comprising a silicon compound.
In some embodiments, first precursor source 114A may comprise a source vessel configured for storing and containing a first precursor under suitable operating conditions. For example, the first precursor may comprise a solid precursor, a liquid precursor, or a vapor phase precursor, and the source vessel may be configured for storing and containing the solid, liquid, or vapor phase precursor under suitable operating conditions. In some embodiments, the first precursor may comprise a silicon compound in liquid form, and the first precursor source may comprise a first precursor vaporizer, which may comprise one or more controllable heating elements that may heat the first precursor to a suitable operating temperature, thereby controllably vaporizing a portion of the first precursor, the vaporized vapor then being distributed to the reaction chamber 102 via suitable means to permeate the permeable material. In some embodiments, one or more heating elements associated with first precursor source 114A may be configured to control the vapor pressure of the first precursor. Additionally, a flow controller 120A, such as a Mass Flow Controller (MFC), may be further integrated with the first precursor source 114A and may be configured to control the mass flow of the vapor generated by the first precursor source 114A, such as a first precursor vaporizer. In addition to flow controller 120A, a valve 122A, such as a shut-off valve, may also be associated with first precursor source 114A and may be used to decouple first precursor source 114A from reaction chamber 102, i.e., prevent vapor generated by first precursor source 114A from flowing into reaction chamber 102 when valve 122A is in a closed position.
In additional embodiments, the first precursor source 114A may further comprise a carrier gas input (not shown) such that a carrier gas (e.g., nitrogen) may be passed or bubbled through the first precursor such that the first precursor may become entrained in the carrier gas and the carrier gas/first precursor vapor may then be delivered to the reaction chamber 102 by suitable means.
In some embodiments, the first precursor source 114A may be constructed and arranged to provide a vapor of the first precursor comprising a silicon compound. For example, the first precursor source 114A may comprise a first precursor vaporizer constructed and arranged to vaporize a portion of the first precursor, thereby generating a vapor of the first precursor comprising a silicon compound. In some embodiments, the first precursor source 114A may be constructed and arranged to provide a vapor of the substituted silane. In some embodiments, first precursor source 114A may be constructed and arranged to provide a vapor of an aminosilane. In some embodiments, the first precursor source may be constructed and arranged to provide a vapor of a compound comprising 3-aminopropyl and silicon, i.e., a silicon precursor comprising both a 3-aminopropyl component and a silicon component.
In some embodiments, first precursor source 114A may be constructed and arranged to provide a vapor of 3-Aminopropyltriethoxysilane (APTES). For example, the first precursor source 114A may include a first precursor evaporator that may be constructed and arranged to evaporate 3-Aminopropyltriethoxysilane (APTES). For example, APTES may be stored and contained in a suitable source container, and an associated heating element may be used to heat APTES to a temperature greater than 0 ℃ or greater than 90 ℃ or even greater than 230 ℃ in order to vaporize a portion of the APTES, thereby producing a vaporized first precursor suitable for use in permeating a permeable material.
In some embodiments, the first precursor source 114A may be constructed and arranged to provide a vapor of 3-aminopropyl-trimethoxysilane (APTMS). For example, the first precursor source 114A may include a first precursor vaporizer that may be constructed and arranged to vaporize 3-aminopropyl-trimethoxysilane (APTMS). For example, APTMS may be stored and contained in a suitable source vessel and an associated heating element may be used to heat APTMS to a temperature greater than 0 ℃ or greater than 90 ℃ or even greater than 230 ℃ in order to vaporize a portion of APTES, thereby producing a vaporized first precursor suitable for use in permeating a permeable material.
In some embodiments of the present disclosure, the first precursor source 114A may be constructed and arranged to provide a vapor of a silicon precursor that includes an alkoxide ligand and an additional ligand other than the alkoxide ligand. For example, the first precursor source 114A may include a first precursor vaporizer that may be constructed and arranged to vaporize a silicon precursor that includes an alkoxide ligand and additional ligands other than the alkoxide ligand.
In some embodiments, the first precursor source 114A may be constructed and arranged to provide a vapor of a silicon precursor comprising an amino-substituted alkyl group attached to a silicon atom. As non-limiting exemplary embodiments of the present disclosure, the first precursor source 114, e.g., a first precursor vaporizer, may be constructed and arranged to provide a vapor of a silicon precursor having the general formulas (I) - (III);
A-R0-Si-L1-L2-L3 (I)
A-R0-Si-(OR1)(OR2)(OR3) (II)
H2N-R-Si-(OR1)(OR2)(OR3) (III)
in which A is a substituent of the carbon chain, e.g. NH2、NHR、NR2OR OR, and R is a carbon chain backbone, e.g., C1-C5 alkyl, and L is NR2(alkylamines), alkoxides (OR), halogens, OR hydrogen.
In some embodiments of the present disclosure, the first precursor source 114A may be constructed and arranged to provide a vapor of a halide-containing silicon compound (e.g., a silicon halide, a silane halide, or a silane containing a halide). In some embodiments, the silicon compound comprises a chloride, such as Hexachlorodisilane (HCDS), Dichlorosilane (DCS), or silicon tetrachloride (SiCl)4) At least one of (1). As non-limiting exemplary embodiments of the present disclosure, first precursor source 114A may be constructed and arranged to provide a vapor of a silicon precursor having general formulas (IV) - (VI);
SinX2n+2(wherein n is 1 to 4) (IV)
SinX2n+2-wLw(wherein n is 1 to 4 and w is 0 to 4) (V)
SinX2n+2-w-yLwHy(wherein n is 1 to 4, w is 0 to 4-y, and y is 0 to 4-w) (VI)
Wherein X is halogen, such as fluorine (F), chlorine (Cl), bromine (Br) or iodine (I), and L is NR2(alkylamine), alkoxide (OR), halogen OR hydrogen, and H is hydrogen.
In some embodiments of the present disclosure, the first silicon precursor may already be in a vapor state when stored in a suitable source vessel, and the precursor source may be used to control the vapor pressure of the vapor phase silicon precursor by raising and lowering the temperature of the vapor phase silicon precursor in the associated source vessel. Thus, it should be appreciated that the precursor sources of the present disclosure can be used to contain and dispense gas phase reactants as well as solid, liquid, or mixed phase reactants.
In some embodiments of the present disclosure, the exemplary permeation device 100 (fig. 1) may include a precursor distribution and removal system constructed and arranged to provide vapor of the first precursor from the first precursor source 114A to the reaction chamber 102 and to remove the vapor of the first precursor from the reaction chamber 102.
In more detail, the precursor distribution system can include a gas delivery system 112 and one or more gas lines, such as a gas line 124 in fluid communication with the first precursor source 114A, a gas line 126 in fluid communication with the second precursor source 114B, a gas line 128 in fluid communication with the source vessel 116, and a gas line 130 in fluid communication with the reactant source vessel 118. As a non-limiting example, the gas line 124 is fluidly connected to the first precursor source 114A and may be configured to deliver a vapor of the first precursor to the reaction chamber 102.
The precursor distribution system can further include a gas distributor 132 configured to distribute a vapor of the first precursor into the reaction chamber 102 and over the substrate 104 having the permeable material 106 disposed thereon, the gas distributor 132 being in fluid communication with the gas line 124 in addition to the gas lines 126, 128, and 130.
As a non-limiting example embodiment, the gas distributor 132 may comprise a showerhead, as shown in block form in fig. 1. It should be noted that although the showerhead is shown in block form, the showerhead may be a relatively complex structure. In some embodiments, the showerhead may be configured to mix the vapors from the multiple sources prior to distributing the gas mixture to the reaction chamber 102. In alternative embodiments, the showerhead may be configured to maintain separation between multiple vapors introduced to the showerhead that contact each other only near the substrate 104 disposed within the reaction chamber 102. Further, the showerhead may be configured to provide vertical or horizontal gas flow into the reaction chamber 102. Exemplary gas distributors are described in U.S. patent No. 8,152,922, the contents of which are incorporated herein by reference to the extent that such contents are not inconsistent with this disclosure.
As shown in fig. 1, the precursor distribution system can include a gas delivery system 112, at least gas lines 124, 126, 128, and 130, and a gas distributor 132, however, it should be noted that the precursor distribution system can also include additional components not shown in fig. 1, such as additional gas lines, valves, actuators, seals, and heating elements.
In addition to the precursor distribution system, the exemplary permeation device 100 may also include a removal system constructed and arranged to remove gas from the reaction chamber 102. In some embodiments, the removal system may include an exhaust port 134 disposed within a wall of the reaction chamber 102, an exhaust line 136 in fluid communication with the exhaust port 134, and a vacuum pump 138 in fluid communication with the exhaust line 136 and configured to evacuate gas from within the reaction chamber 102. After the gas or gases have been exhausted from the reaction chamber 102 using the vacuum pump 138, they may be conveyed along an additional exhaust line 140 and exit the exemplary permeation device 100 where they may undergo a further abatement process.
To further assist in the removal of precursor gases (i.e., reactive vapors) from within the reaction chamber 102, the removal system may further include a source vessel 116 fluidly connected to a gas distributor 132 by a gas line 128. For example, the source vessel 116 may be configured to contain and store a purge gas, such as argon (Ar), nitrogen (N)2) Or helium (He). The flow controller 120C and valve 122C in conjunction with the source vessel 116 can control the flow, particularly the mass flow of the purge gas delivered to the gas distributor 132 via the gas line 128 and into the reaction chamber 102, wherein the purge gas can assist in removing vapor phase precursor gases, inert gases, and byproducts from within the reaction chamber 102, particularly the purge precursor gases and unreacted byproducts from the exposed surfaces of the permeable material 106. The purge gas (and any associated precursors and byproducts) may exit the reaction chamber 102 through an exhaust port 134 via the use of a vacuum pump 138.
In some embodiments of the present disclosure, the exemplary infiltration apparatus 100 may further comprise a sequence controller operably connected to the precursor distribution system and the removal system, and comprising a memory provided with a program to perform infiltration of the permeable material when run on the sequence controller.
In more detail, the exemplary permeation device 100 can include a sequence controller 142, which can also include control lines 144A, 144B, and 144C that can interface various systems and/or components of the permeation system 100 to the sequence controller 142. For example, the control lines 144A may interface the sequence controller 142 with the gas delivery system 112 and thereby provide control of the precursor distribution system including the gas lines 124, 126, 128, and 130 and the gas distributor 132. Control lines 144B may interface the sequence controller 142 with the reaction chamber 102, thereby providing control over the operation of the reaction chamber, including but not limited to process pressure and pedestal temperature. Control lines 144C may interface the sequence controller 142 with the vacuum pump 138 so that the sequence controller 142 may provide operation and control of the gas removal system.
It should be noted that as shown in fig. 1, the sequence controller 142 includes three control lines 144A, 144B, and 144C, however, it should be appreciated that multiple control lines (i.e., electrically and/or optically connected control lines) may be utilized to interface the desired systems and components comprising the permeation device 100 with the sequence controller 142, thereby providing overall control of the permeation device 100.
In some embodiments of the present disclosure, the sequence controller 142 may contain electronic circuitry to selectively operate valves, heaters, flow controllers, manifolds, pumps, and other equipment included in the exemplary permeation device 100. Such circuitry and components are used to introduce precursor gases and purge gases from the respective precursor sources 114A, 114B, the reactant source vessel 118, and the purge gas source vessel 116. The sequence controller 142 may also control the timing of precursor pulse sequences, the temperature of the substrate and reaction chamber, as well as the pressure of the reaction chamber and various other operations necessary to provide proper operation of the permeation device 100. In some embodiments, the sequence controller 142 may also include control software and electronically or pneumatically controlled valves to control the flow of precursor and purge gases into and out of the reaction chamber 102. In some embodiments of the present disclosure, the sequence controller 142 may include a memory 144 with a program to perform the infiltration of the permeable material when run on the sequence controller. For example, the sequence controller 142 may include modules, such as software or hardware components, such as FPGAs or ASICs, that perform certain infiltration processes. The modules may be configured to reside on the addressable storage media of the sequence controller 142 and may be configured to perform one or more infiltration processes.
In some embodiments of the present disclosure, the memory 144 of the sequence controller 142 may be provided with a program to perform infiltration of the permeable material 106 when running on the sequence controller 142 by; the precursor distribution system and the removal system are activated to provide the vapor of the first precursor to the permeable material 106 on the substrate 104 within the reaction chamber 102, whereby the permeable material 106 on the substrate 104 within the reaction chamber 102 is permeated with silicon atoms by the reaction of the vapor of the first precursor with the permeable material 106.
In some embodiments of the present disclosure, the exemplary permeation device 100 may include a second precursor source 114B, such as a second precursor vaporizer. In more detail, the second precursor source 114B can be constructed and arranged to provide a vapor of a second precursor comprising a silicon compound. For example, the second precursor source 114B may comprise a second precursor vaporizer, which may be constructed and arranged to vaporize a second precursor comprising a silicon compound. In some embodiments, the second precursor source 114B may be the same or substantially the same as the first precursor source 114A, and thus details regarding the second precursor source 114B are omitted for the sake of brevity.
In some embodiments, the precursor distribution system and the removal system may be constructed and arranged to provide vapor of the second precursor from the second precursor source 114B to the reaction chamber 102. For example, the gas line 126 may be fluidly connected to the second precursor source 114B through the flow controller 120B and the valve 122B, and may deliver a vapor of the second precursor from the second precursor source 114B to the gas distributor 132 and then into the reaction chamber 102. In some embodiments, the program in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by; the precursor distribution system and the removal system are activated to provide a vapor of the second precursor to the reaction chamber 102, whereby the permeable material 106 on the substrate 104 is permeable to silicon atoms from the vapor of the second precursor.
In some embodiments of the present disclosure, the second precursor source 114B may be constructed and arranged to provide vapor of any of the silicon precursors (i.e., silicon-containing compounds), as previously described herein with reference to the first precursor source 114A. In some embodiments, second precursor source 114B may be constructed and arranged to provide a vapor of a silicon compound that is different than first precursor source 114A, in other words, second precursor source 114B may be constructed and arranged to provide a vapor of a second silicon precursor that may be different than the vapor of the first silicon precursor provided by first precursor source 114A. By way of non-limiting example, the first precursor source 114A may be constructed and arranged to evaporate APTES and provide a vapor of APTES to the reaction chamber 102, and the second precursor source 114B may be constructed and arranged to evaporate HCDS and provide a vapor of HCDS to the reaction chamber 102.
In some embodiments of the present disclosure, the program in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by; the precursor distribution system and the removal system are activated to simultaneously provide the first precursor and the second precursor, i.e., both the first precursor source 114A and the second precursor source 114B can simultaneously provide the vapor of the second precursor and the vapor of the first precursor into the reaction chamber 102, such that the permeable material 106 disposed on the substrate 104 can be simultaneously permeated by the vapor of the second precursor (i.e., the second silicon compound) and the vapor of the first precursor (i.e., the first silicon compound).
In some embodiments of the present disclosure, the program in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by; the precursor distribution system and the removal system are activated to provide the second precursor after the first precursor, i.e., the first precursor source 114A can provide a vapor of the first precursor into the reaction chamber 102 and permeate the permeable material 106 with the first precursor, and subsequently the second precursor source 114B can provide a vapor of the second precursor into the reaction chamber 102 and permeate the permeable material 106 with the second precursor.
In some embodiments, the sequence controller 142 may run a program on the memory 144 to activate the precursor distribution system and the removal system to provide the first precursor after the second precursor, i.e., the second precursor source 114B may provide vapor of the second precursor into the reaction chamber 102 to permeate the permeable material 106 with the second precursor vapor, and then the first precursor source 114A may provide vapor of the first precursor into the reaction chamber 102 to permeate the permeable material 106 with the first precursor.
In some embodiments of the present disclosure, a program installed in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by; the precursor distribution system and removal system are activated to provide the first precursor to the reaction chamber 102, followed by a purge cycle to remove excess first precursor and any byproducts from the reaction chamber, and then the second precursor is provided to the reaction chamber, followed by a second purge cycle to remove excess second precursor and any byproducts from the reaction chamber.
In more detail, the program installed in the memory 144 of the sequence controller 142 may first activate the first precursor source 114A and provide a vapor of the first precursor to the reaction chamber 102 to permeate the permeable material 106 with the vapor of the first precursor, then the first precursor source 114A may be deactivated, and the fluid connection between the first precursor source 114A and the reaction chamber 102 to the reaction chamber 102 may be disengaged, for example, through the valve 122A associated with the first precursor source 114A. After the first precursor source 114A is deactivated and disengaged from the reaction chamber 102, the program installed in the memory 144 of the sequence controller 142 may engage or continue to engage the vacuum pump 138 to evacuate the reaction chamber 102 of excess vapor and any byproducts of the first precursor. In additional embodiments, in addition to evacuating excess vapor of the first precursor and any byproducts from the reaction chamber 102 using the vacuum pump 138, a program installed in the memory 144 of the sequence controller 142 may also activate the source vessel 116 containing a source of purge gas, for example, by opening a valve 122C associated with the source vessel 116. A purge gas may flow through the gas line 128 and through the gas distributor 132 into the reaction chamber 102 and purge the reaction chamber 102, and in particular, may purge the permeable material 106 disposed on the substrate 104. A program installed in the memory 144 of the sequence controller 142 may then stop the flow of purge gas through the reaction chamber 102 and then activate the second precursor source 114B, thereby providing vapor of the second precursor to the reaction chamber 102 and, in particular, permeating the permeable material 106 with the second precursor vapor provided by the second vapor source 114B. A program installed in the memory 144 of the sequence controller 142 may then stop the flow of the vapor of the second precursor through the reaction chamber 102 and then activate the source vessel 116 to again purge the reaction chamber, for example, to remove excess vapor of the second precursor.
In some embodiments of the present disclosure, a program installed in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by; the precursor distribution system and removal system are activated to provide vapor of the second precursor to the reaction chamber, followed by a purge cycle to remove excess vapor of the second precursor and any byproducts from the reaction chamber, followed by providing vapor of the first precursor to the reaction chamber, followed by a purge cycle to remove excess vapor of the first precursor and any byproducts from the reaction chamber.
In additional embodiments of the present disclosure, the exemplary osmotic apparatus 100 may comprise a sequential osmotic synthesis (SIS) apparatus. For example, a Sequential Infiltration Synthesis (SIS) apparatus may be constructed and arranged to alternately, self-limit exposure of a permeable material to two or more gas phase precursors. Thus, in addition to the first precursor source 114A and the second precursor source 114B, the exemplary permeation device 100 can further include a reactant source vessel 118 and a reactant supply line (i.e., gas line 130) constructed and arranged to provide a reactant including an oxygen precursor to the reaction chamber 102.
In some embodiments of the present disclosure, the reactant source vessel 118 may contain reactants in a solid, liquid, or gas phase. In some embodiments, the reactant source vessel 118 may comprise a reactant vaporizer, i.e., one or more heating elements may be incorporated with the reactant source vessel to effect vaporization of the reactants and thereby provide vaporized reactants comprising oxygen precursors to the reaction chamber 102. At one endIn some embodiments, controlling the flow of the vapor reactant comprising the oxygen precursor to the reaction chamber may be accomplished by using both a valve 122D and a flow controller 120D in conjunction with the reactant source vessel 118. In some embodiments of the present disclosure in which the reactant source vessel 118 further comprises a reactant vaporizer, the reactant vaporizer can be constructed and arranged to vaporize water (H)2O) or hydrogen peroxide (H)2O2) As a reactant including an oxygen precursor.
In some embodiments of the present disclosure, the reactant source vessel 118 may store and distribute gaseous oxygen precursor to the reaction chamber 102 through the reactant supply line 130 and the gas distributor 132. In some embodiments, the gaseous oxygen precursor may comprise ozone (O)3) Or molecular oxygen (O)2) At least one of (1).
In some embodiments of the present disclosure, the exemplary permeation device 100 may optionally further comprise a plasma generator 146 constructed and arranged to generate a plasma from the gaseous oxygen precursor, thereby providing one or more of atomic oxygen, oxygen ions, oxygen radicals, and excited species of oxygen to the reaction chamber 102, whereby the oxygen-based plasma generated by the plasma generator 146 may react with the permeable material 106 disposed on the substrate 104.
In some embodiments of the present disclosure, the exemplary permeation device 100 may be a sequential permeation synthesis device further comprising a reactant source vessel 118 and a reactant supply line 130 constructed and arranged to provide a reactant comprising an oxygen precursor to the reaction chamber 102, wherein the program in the memory 144 of the sequence controller 142 may be programmed to perform the permeation of the permeable material 106 when run on the sequence controller 142 by: the precursor distribution system and the removal system are activated to remove gas from the reaction chamber 102, and the precursor distribution system and the removal system are activated to provide a reactant comprising an oxygen precursor to the reaction chamber 102, whereby the permeable material 106 on the substrate 104 in the reaction chamber 102 is made permeable to silicon atoms and oxygen atoms by the reaction of the first precursor with the reactant comprising the oxygen precursor with the permeable material 106. In some embodiments, the sequence of providing the first precursor and subsequently providing the reactant may be repeated one or more times. In some embodiments, a purge cycle may be performed after each step in the program sequence to remove excess precursor and byproducts from the reaction chamber by evacuating the reaction chamber 102 with a vacuum pump 138 and optionally flowing a purge gas from the source vessel 116.
In some embodiments of the present disclosure, the program installed in the memory 114 may be programmed to perform continuous permeation synthesis of the permeable material 106 when run on the sequence controller 142 by; the precursor distribution system and removal system are activated to provide an oxygen precursor to the reaction chamber from the reactant source vessel 118, and then a vapor of the first precursor is provided to the reaction chamber 102 from the first precursor source 114A, thereby permeating the permeable material with both silicon atoms and oxygen atoms. In some embodiments, the sequence of providing the oxygen precursor and then providing the vapor of the first precursor may be repeated one or more times. In some embodiments, a purge cycle may be performed after each step in the program sequence to remove excess precursor and byproducts from the reaction chamber by evacuating the reaction chamber 102 with a vacuum pump 138 and optionally flowing a purge gas from the source vessel 116.
In some embodiments of the present disclosure, the apparatus comprises a sequential permeation synthesis apparatus and further comprises a second precursor source 114B constructed and arranged to provide a vapor of a second precursor to the reaction chamber 102. For example, the second precursor source 114B may comprise a second precursor vaporizer constructed and arranged to vaporize a second precursor comprising a silicon compound. In some embodiments, the precursor distribution system and removal system may be constructed and arranged to provide vapor of the second precursor from the second precursor source 114B to the reaction chamber 102, and the program in the memory 144 is programmed to perform infiltration of the permeable material when run on the sequence controller 142 by; the precursor distribution system and the removal system are activated to provide a second precursor.
In some embodiments of the present disclosure, the program in the memory 144 is programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by: the precursor distribution system and the removal system are activated to provide a first precursor, followed by a reactant, followed by a second precursor, and followed by a reactant.
In some embodiments of the present disclosure, the program in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by: the precursor distribution system and the removal system are activated to provide a first precursor, followed by a reactant, followed by a second precursor, and followed by a reactant, in a plurality of iterations.
In some embodiments of the present disclosure, the program in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by: the precursor distribution system and the removal system are activated to remove the precursor and/or the reactant from the reaction chamber between each step of providing the first precursor, subsequently providing the reactant, subsequently providing the second precursor and subsequently providing the reactant.
In some embodiments of the present disclosure, the program in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by: the precursor distribution system and the removal system are activated to provide a first precursor, followed by a second precursor, and followed by a reactant. In some embodiments, the sequence of providing the first precursor, then providing the second precursor, and then providing the reactant may be repeated one or more times. In some embodiments, a purge cycle may be performed after each step in the program sequence to remove excess precursor and byproducts from the reaction chamber by evacuating the reaction chamber 102 with a vacuum pump 138 and optionally flowing a purge gas from the source vessel 116.
In some embodiments of the present disclosure, the program in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by: the precursor distribution system and the removal system are activated to provide a second precursor, followed by the first precursor, and followed by the reactants. In some embodiments, the sequence of providing the second precursor, then providing the first precursor, and then providing the reactant may be repeated one or more times. In some embodiments, a purge cycle may be performed after each step in the program sequence to remove excess precursor and byproducts from the reaction chamber by evacuating the reaction chamber 102 with a vacuum pump 138 and optionally flowing a purge gas from the source vessel 116.
In some embodiments of the present disclosure, the program in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by: the precursor distribution system and the removal system are activated to provide a first precursor, followed by the provision of a reactant, and followed by the provision of a second precursor. In some embodiments, the sequence of providing the first precursor, then providing the reactant, and then providing the second precursor may be repeated one or more times. In some embodiments, a purge cycle may be performed after each step in the program sequence to remove excess precursor and byproducts from the reaction chamber by evacuating the reaction chamber 102 with a vacuum pump 138 and optionally flowing a purge gas from the source vessel 116.
In some embodiments of the present disclosure, the program in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by: the precursor distribution system and the removal system are activated to provide a reactant, followed by providing a first precursor, followed by providing a second precursor, and followed by providing a reactant. In some embodiments, the sequence of providing a reactant, then providing a first precursor, then providing a second precursor, and then providing a reactant may be repeated one or more times. In some embodiments, a purge cycle may be performed after each step in the program sequence to remove excess precursor and byproducts from the reaction chamber by evacuating the reaction chamber 102 with a vacuum pump 138 and optionally flowing a purge gas from the source vessel 116.
In some embodiments of the present disclosure, the program in the memory 144 may be programmed to perform infiltration of the permeable material 106 when run on the sequence controller 142 by: the precursor distribution system and the removal system are activated to provide a reactant, followed by providing a first precursor, followed by providing a reactant, and followed by providing a second precursor. In some embodiments, the sequence of providing a reactant, subsequently providing a first precursor, subsequently providing a reactant, and subsequently providing a second precursor may be repeated one or more times. In some embodiments, a purge cycle may be performed after each step in the program sequence to remove excess precursor and byproducts from the reaction chamber by evacuating the reaction chamber 102 with a vacuum pump 138 and optionally flowing a purge gas from the source vessel 116.
Embodiments of the present disclosure may also include methods for infiltrating a permeable material and particular methods for infiltrating a permeable material with silicon atoms.
Accordingly, embodiments of the present disclosure may provide a method of permeating a permeable material, the method comprising: providing a substrate having a permeable material disposed thereon in a reaction chamber; providing a first precursor comprising a silicon compound to a permeable material in a reaction chamber for a first period of time (T)1) Thereby causing a permeable material on a substrate disposed within the reaction chamber to be permeated with silicon atoms; and purging the reaction chamber for a second period of time (T)2)。
An exemplary infiltration process 200 is shown in fig. 2, wherein the infiltration process 200 may proceed by way of a process block 210 that includes providing a substrate having a permeable material disposed thereon in a reaction chamber. The substrate may comprise one or more materials as previously disclosed, and may comprise a planar substrate or a patterned substrate. In some embodiments, the permeable material comprises at least one of a photoresist, an Extreme Ultraviolet (EUV) resist, an immersion resist, a Chemically Amplified Resist (CAR), an e-beam resist, a porous material, or a hardmask material, such as silicon oxide, silicon nitride, or silicon oxynitride.
The exemplary infiltration process 200 may continue by way of a process block 220 that includes providing a first precursor comprising a silicon compound to the permeable material in the reaction chamber for a first period of time (T;)1) Thereby causing a permeable material on a substrate disposed within the reaction chamber to be permeated with silicon atoms. The first precursor may comprise a silicon compound in a vapor phase and may include any of the silicon compounds previously described herein. In some embodiments, the first precursor comprises at least one of an aminosilane, an ethoxysilane, a methoxysilane, or a silicon halide. At one endIn some embodiments, the first precursor comprises at least one of 3-Aminopropyltriethoxysilane (APTES) or Hexachlorodisilane (HCSD). In some embodiments, the first time period (T)1) That is, the period of time that the first precursor is provided to and contacts the permeable material may be between approximately 25 milliseconds and approximately 10 hours.
The exemplary infiltration process 200 may continue by way of a process block 230 that includes purging the reaction chamber for a period of time (T;)2). For example, the reaction chamber may be purged by evacuating excess first precursor (and any reaction byproducts) from the reaction chamber using a vacuum pump. In addition, the purge process may also include supplying a purge gas into the reaction chamber to assist in excess precursor gas venting. In some embodiments, the reaction chamber may be purged for a period of time (T) between approximately 25 milliseconds and approximately 10 hours2)。
The exemplary infiltration process 200 may continue with a decision gate 240, wherein the decision gate 240 may depend on the atomic percent (at%) of silicon infiltrated into the permeable material. If insufficient silicon atoms penetrate into the permeable material, the exemplary process 200 may return to process block 220 and the permeable material may be exposed to the first silicon precursor again by providing the first silicon precursor to the permeable material, followed by process block 230, wherein the reaction chamber is purged of excess precursor and byproducts. Accordingly, some embodiments of the present disclosure may comprise repeating the steps of: the steps of providing the first precursor and subsequently purging the reaction chamber are performed one or more times until the desired atomic% of the silicon atoms penetrate into the permeable material. After the desired atomic% of the silicon atoms penetrate into the permeable material, the exemplary process may end via process block 250. For example, an exemplary infiltration process may produce an infiltrated permeable material having an atomic percent of silicon atoms greater than 0.1%, or greater than 5%, or greater than 15%, or greater than 50%, or greater than 75%, or even approximately 100%. In some embodiments, the infiltration process may produce an infiltrated permeable material having greater than 15 atomic percent of silicon atoms. In some embodiments, the infiltrating silicon atoms can be uniformly distributed within the permeable material. In some embodiments, the infiltrating silicon atoms may be non-uniformly distributed within the permeable material.
An additional exemplary infiltration process 300 may be illustrated with reference to fig. 3, wherein the exemplary infiltration process 300 may proceed by way of a process block 310 that includes providing a substrate having a permeable material disposed thereon in a reaction chamber. Process block 310 is equivalent to process block 210 of fig. 2 and, therefore, is not described in greater detail herein.
The exemplary infiltration process 300 may continue by way of a process block 320 including providing a first precursor comprising a silicon compound to the permeable material in the reaction chamber for a first period of time (T;)1) Thereby causing a permeable material on a substrate disposed within the reaction chamber to be permeated with silicon atoms. Process block 320 is equivalent to process block 220 of fig. 2 and, therefore, is not described in greater detail herein.
The exemplary infiltration process 300 may continue by way of a process block 330 including providing a second precursor comprising a silicon compound to the permeable material in the reaction chamber for a third period of time (T)3) Thereby causing a permeable material on a substrate disposed within the reaction chamber to be permeated with silicon atoms. For example, a third time period (T) for providing and contacting the second precursor with the permeable material3) May be between approximately 25 milliseconds and approximately 10 hours.
In some embodiments of the present disclosure, the second precursor comprising a silicon compound may comprise any of the silicon compounds described in detail previously herein. In particular embodiments, the second precursor may comprise at least one of an aminosilane, an ethoxysilane, a methoxysilane, or a silicon halide. In some embodiments, the second precursor may comprise at least one of 3-Aminopropyltriethoxysilane (APTES) or Hexachlorodisilane (HCSD).
In some embodiments of the present disclosure, the first precursor may be different from the second precursor, i.e., the first precursor may comprise a first silicon vapor phase reactant and the second precursor may further comprise a second silicon vapor phase reactant different from the first silicon vapor phase reactant.
Although shown as two separate process blocks in fig. 3, the process block 320 comprising providing the first precursor and the process block 330 comprising providing the second precursor may be performed simultaneously, i.e., the first precursor and the second precursor may be provided simultaneously to the permeable material in the reaction chamber to thereby permeate the permeable material with silicon atoms.
In alternative embodiments, the first precursor and the second precursor may be provided separately to the permeable material, i.e., such that the first precursor and the second precursor do not contact the permeable material at the same time. In such embodiments where the first precursor and the second precursor are provided separately to the permeable material, the exemplary infiltration process may further comprise: purging the reaction chamber between providing the first precursor and providing the second precursor allows excess first precursor (and any reaction byproducts) to be removed from the reaction chamber prior to providing the second precursor to the permeable material. An additional reaction chamber purge may be performed after providing the second precursor to remove excess second precursor and any reaction byproducts. It should be noted that in such embodiments where the first precursor and the second precursor are provided separately to the permeable material, the order of providing the precursors may be such that the second precursor is provided first to the permeable material followed by the first precursor with an optional purging of the reaction chamber between the providing steps.
The exemplary infiltration process 300 may continue by way of process block 340, which includes purging the reaction chamber for a fourth period of time (T) after providing the second precursor to the permeable material4). For example, a fourth time period (T) to remove excess precursor from the reaction chamber4) May be between approximately 25 milliseconds and approximately 10 hours.
The exemplary infiltration process 300 may continue with a decision gate 350, wherein the decision gate 350 may depend on the atomic percent (at%) of silicon infiltrated into the permeable material. If insufficient silicon atoms penetrate into the permeable material, the exemplary process 300 may return to process block 320 and the permeable material may again be exposed to the first silicon precursor (process block 320) and the second precursor (process block 330) with an optional intermediate reaction chamber purge followed by process block 340 with the reaction chamber purged of excess precursor and any reaction byproducts. Accordingly, the methods disclosed herein may comprise repeating the steps of: the first precursor is provided, followed by purging the reaction chamber, followed by providing the second precursor, and then purging the reaction chamber one or more times, i.e., until the desired atomic% of silicon is infiltrated into the permeable material.
After the desired atomic% of the silicon atoms penetrate into the permeable material, the exemplary process 300 may end via process block 360.
Without being bound by any particular theory, it is believed that the disclosed method comprising providing a first silicon precursor and a second, different silicon precursor to a permeable material may result in the infiltration of a greater atomic% of silicon atoms. For example, the exemplary infiltration process 300 may produce an infiltrated permeable material having an atomic percent of silicon atoms greater than 0.1%, or greater than 5%, or greater than 15%, or greater than 50%, or greater than 75%, or even approximately 100%. In some embodiments, the infiltration process may produce an infiltrated permeable material having greater than 15 atomic percent of silicon atoms. In some embodiments, the infiltrating silicon atoms can be uniformly distributed within the permeable material. In some embodiments, the infiltrating silicon atoms may be non-uniformly distributed within the permeable material.
In additional embodiments of the present disclosure, the disclosed methods may comprise a Sequential Infiltration Synthesis (SIS) method, which may comprise alternately exposing a permeable material to more than two precursors to enable infiltration of atoms and/or materials into the permeable material, such as a polymer resist or a hardmask material.
Accordingly, additional embodiments of the present disclosure may be illustrated with reference to fig. 4, which illustrates an exemplary SIS process 400. In more detail, an exemplary SIS process can begin by means of a process block 410 that includes providing a substrate having a permeable material disposed thereon in a reaction chamber. Process block 410 is equivalent to process 210 of fig. 2 and, therefore, is not described in greater detail herein.
An exemplary SIS process 400 can be conducted by performing one or more SIS cycles 405, wherein an SIS cycle can be conducted by means of a process block 420 that includes providing a first precursor comprising a silicon compound to a permeable material within a reaction chamber for a first period of time (T;)1) Thereby enabling a permeable material on a substrate disposed in the reaction chamber to be coated with silicon atomsAnd (4) infiltration. Process block 420 is equivalent to process block 220 of fig. 2 and, therefore, is not described in more detail herein.
The SIS cycle 405 of the exemplary SIS process 400 can be performed by means of a process block 430 that includes providing a reactant comprising an oxygen precursor to a permeable material within a reaction chamber for a fifth period of time (T;)5) Thereby causing the permeable material on the substrate disposed within the reaction chamber to be permeated with oxygen atoms.
In more detail, in some embodiments, the reactant comprising the oxygen precursor may comprise water (H)2O) or hydrogen peroxide (H)2O2) Vapor of at least one of the above. In some embodiments, the oxygen precursor may comprise ozone (O)3) Or molecular oxygen (O)2). In some embodiments of the present disclosure, the reactant comprising an oxygen precursor may comprise an oxygen-based plasma comprising oxygen atoms, oxygen ions, oxygen radicals, and excited species of oxygen generated by plasma excitation of an oxygen-containing gas, such as ozone (O), for example3) Or molecular oxygen (O)2) At least one of (1). For example, in some embodiments, the method may include providing a reactant including an oxygen precursor to the permeable material for a fifth time period (T) of between approximately 25 milliseconds and approximately 10 hours5)。
In some embodiments of the present disclosure, the process block 420 of providing the first precursor and the process block 430 of providing the reactant may be separated by a reaction chamber purge to remove excess precursor and reaction byproducts from the reaction chamber. Additionally, the process block 430 of providing the reactants may be followed by an additional reaction chamber purge to remove excess reactants and reaction byproducts. It should also be noted that the process sequence shown in fig. 4 may be modified such that the reactant comprising the oxygen precursor may be provided to the permeable material first, followed by providing the first precursor to the permeable material.
The SIS cycle 405 of the exemplary SIS process 400 may continue with a decision gate 440, where the decision gate 440 may depend on the atomic percent (at%) of silicon permeated into the permeable material and the atomic percent (at%) of oxygen permeated into the permeable material. If insufficient silicon and oxygen atoms permeate into the permeable material, the SIS cycle 405 of the exemplary SIS process 400 can be repeated by returning to process block 420, and the permeable material can again be exposed to the first silicon precursor (process block 420) and the reactant comprising the oxygen precursor (process block 430), with an optional reaction chamber purge following each separate process block.
Thus, in some embodiments, the unit SIS cycle 405 of the exemplary SIS process 400 can include providing a first precursor comprising a silicon compound, purging the reaction chamber, providing a reactant comprising an oxygen precursor, and purging the reaction chamber. In alternative embodiments, the unit SIS cycle 405 of the exemplary SIS process 400 can include providing a reactant comprising an oxygen precursor, purging the reaction chamber, providing a first precursor comprising a silicon compound, and purging the reaction chamber.
After the desired atomic% of the silicon and oxygen atoms have permeated into the permeable material, the exemplary SIS process 400 can end via process block 450.
Additional embodiments of the present disclosure may include other sequential osmotic synthesis (SIS) methods that may be illustrated with reference to fig. 5, which illustrates an exemplary SIS process 500. In more detail, the exemplary SIS process 500 can begin by means of a process block 510 that includes providing a substrate having a permeable material disposed thereon in a reaction chamber. Process block 510 is equivalent to process 210 of fig. 2 and, therefore, is not described in greater detail herein.
The exemplary SIS process 500 can continue with an SIS cycle 505, which can begin by way of a process block 520 that includes providing a first precursor comprising a silicon compound to a permeable material in a reaction chamber for a first period of time (T;)1) Thereby causing a permeable material on a substrate disposed within the reaction chamber to be permeated with silicon atoms. Process block 520 is equivalent to process block 220 of fig. 2 and, therefore, is not described in more detail herein.
The SIS cycle 505 of the exemplary SIS process 500 may continue by way of a process block 530 that includes providing a second precursor comprising a silicon compound to the permeable material, wherein the second precursor is different than the first precursor. Process block 530 is equivalent to process block 330 of fig. 3 and therefore is not described in further detail herein.
The SIS cycle 505 of the exemplary SIS process 500 may continue by way of a process block 540 that includes providing a reactant comprising an oxygen precursor to the permeable material. Process block 540 is equivalent to process block 430 of fig. 4 and, therefore, is not described in greater detail herein.
The SIS cycle 505 of the exemplary SIS process 500 may continue with a decision gate 550, where the decision gate 550 may depend on the atomic percent (at%) of silicon permeated into the permeable material and the atomic percent (at%) of oxygen permeated into the permeable material. If insufficient silicon and oxygen atoms permeate into the permeable material, the SIS cycle 505 can be repeated by returning to process block 520, and the permeable material can be exposed to the first silicon precursor again (process block 520), to the second silicon precursor (process block 530), and to the reactant comprising the oxygen precursor (process block 540). After the desired atomic% of the silicon and oxygen atoms have permeated into the permeable material, the exemplary SIS process 500 can end via process block 560.
Accordingly, the methods disclosed herein can comprise performing one or more sequential osmotic synthesis (SIS) cycles 505, wherein a unit SIS cycle can comprise: providing a first precursor comprising a silicon compound to a permeable material; a second precursor comprising a silicon compound different from the first precursor is provided to the permeable material and a reactant comprising an oxygen precursor is provided to the permeable material.
In some embodiments, each step of the SIS cycle may be followed by purging the reaction chamber to remove excess precursor/reactive species between successive process steps. As non-limiting examples, an exemplary unit SIS cycle may comprise: providing a first precursor; purging the reaction chamber; providing a second precursor; purging the reaction chamber; providing a reactant comprising an oxygen precursor; and purging the reaction chamber, wherein the SIS cycle can be repeated one or more times.
In some embodiments of the present disclosure, the process sequence of the exemplary SIS process 500, including the unit SIS cycles, may be performed in an alternative order. In some embodiments, a unit SIS cycle may comprise: providing a second precursor; purging the reaction chamber; providing a first precursor; purging the reaction chamber; providing a reactant comprising an oxygen precursor; and purging the reaction chamber, whereby the SIS cycle can be repeated one or more times. In some embodiments, a unit SIS cycle may comprise: providing a first precursor; purging the reaction chamber; providing a reactant; purging the reaction chamber; providing a second precursor; and purging the reaction chamber. In some embodiments, a unit SIS cycle may comprise: providing a first precursor; purging the reaction chamber; providing a reactant; purging the reaction chamber; providing a second precursor; purging the reaction chamber; providing a reactant; and purging the reaction chamber. In some embodiments, a unit SIS cycle may comprise: providing a reactant; purging the reaction chamber; providing a first precursor; purging the reaction chamber; providing a second precursor; purging the reaction chamber; providing a reactant; and purging the reaction chamber. In some embodiments, a unit SIS cycle may comprise: providing a reactant; purging the reaction chamber; providing a first precursor; purging the reaction chamber; providing a reactant; purging the reaction chamber; and providing a second precursor; and purging the reaction chamber.
As a non-limiting example illustrating the capabilities of the infiltration apparatus and infiltration method disclosed herein, fig. 6 shows x-ray photoelectron spectroscopy (XPS) obtained from Extreme Ultraviolet (EUV) chemically amplified resist infiltrated with silicon atoms using the infiltration apparatus and infiltration process disclosed herein. In more detail, the EUV chemically amplified resist is infiltrated with a silicon precursor containing Hexachlorosilane (HCDS). Inspection of the XPS spectrum 600 reveals a raw data line 602 and a processed data line 604, wherein the processed data line 604 indicates a large number of salient features. For example, the shoulder peak labeled 604A and the peak labeled 604B in the data both indicate the presence of silicon oxide in the penetrating EUV resist, while the peak labeled 606 indicates the presence of elemental silicon in the penetrating EUV resist. Thus, embodiments of the present disclosure may not only infiltrate silicon atoms into a permeable material, but in some embodiments, may infiltrate the permeable material with silicon oxide. In the example shown in fig. 6, the EUV resist is infiltrated by silicon atoms to a concentration of approximately 6 atomic%.
As another non-limiting example to illustrate the capabilities of the infiltration apparatus and infiltration method disclosed herein, fig. 7 shows a Secondary Ion Mass Spectrum (SIMS)700 obtained from an EUV chemically amplified resist film infiltrated with silicon atoms using the infiltration apparatus and infiltration process described herein. In more detail, the EUV chemically amplified resist film is infiltrated with a silicon precursor comprising 3-Aminopropyltriethoxysilane (APTES). Inspection of SIMS spectra 700 obtained from the infiltrated EUV resist film reveals a data line 702 indicative of carbon (C) composition in the film, which corresponds to organic EUV resist, and a data line 704 indicative of silicon (Si) composition in the film, which corresponds to a plurality of silicon atoms infiltrated into the EUV resist. Data line 704, which represents the silicon composition in the EUV resist film, indicates that the silicon atoms are uniformly distributed throughout the EUV resist film. In this particular example, EUV is infiltrated by silicon atoms to a concentration of approximately 3 atomic%.
The infiltration apparatus and infiltration method disclosed herein may be used to form infiltration materials, such as polymer resists and hard mask materials, with increased resistance to etching processes. The permeable material may be used in the fabrication of semiconductor device structures, for example, by serving as an etch mask to transfer patterned permeable features into an underlying substrate.
As a non-limiting example of an embodiment of the present disclosure, fig. 8 illustrates a semiconductor device structure 800 including a substrate 802 and an interpenetrating polymer resist feature 804. In more detail, the substrate 802 may comprise any of the materials previously described with respect to the substrate 104 of fig. 1, and may further include a planar structure (as shown in fig. 8) or a non-planar structure. In some embodiments, the substrate 802 may include fabricated or at least partially fabricated semiconductor device structures, such as transistors and/or memory elements.
In some embodiments of the present disclosure, an interpenetrating polymer resist feature 804 may be disposed on a surface of the substrate 802. For example, the polymer resist features may be fabricated by standard lithographic methods and may include any geometry or features that may be produced using standard lithographic methods, such features including, but not limited to, wire features, frame features, apertured features, and circular features. In some embodiments, the osmopolymer resist 804 may include an organic component and an inorganic component including a plurality of silicon (Si) atoms that are infiltrated into the organic component. In some embodiments, the concentration of the plurality of silicon atoms within the organic component may be greater than 0.1 atomic%, or greater than 5 atomic%, or greater than 15 atomic%, or greater than 50 atomic%, or greater than 75 atomic%, or even approximately 100 atomic%. In some embodiments, the concentration of the plurality of silicon atoms and the organic component may be greater than approximately 15 atomic%.
In some embodiments, the plurality of silicon atoms infiltrated into the organic component can be uniformly distributed throughout the organic component. In some embodiments, the plurality of silicon atoms infiltrated into the organic component may be non-uniformly distributed throughout the organic component.
In some embodiments of the present disclosure, the organic component further comprises a plurality of oxygen atoms infiltrated into the organic component. For example, the concentration of the plurality of oxygen atoms within the organic component can be greater than 0.1 atomic%, or greater than 5 atomic%, or greater than 15 atomic%, or even greater than 50 atomic%.
In some embodiments of the present disclosure, the organic component of the osmopolymer resist may further comprise a plurality of silicon atoms and a plurality of oxygen atoms. In some embodiments, the organic component of the osmopolymer resist may further comprise osmopolymer silicon oxide (Si)xOy) Wherein the silicon oxide is not limited to any particular stoichiometry. For example, the plurality of silicon atoms may be elemental silicon (Si) and silicon oxide (Si)xOy) Disposed within the organic component of the osmopolymer resist 804.
The above-described exemplary embodiments of the present disclosure do not limit the scope of the invention, as these embodiments are merely examples of embodiments of the present invention, which is defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be included within the scope of the present invention. Indeed, various modifications of the disclosure, as alternative available combinations of the elements described, in addition to those shown and described herein will be apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

Claims (56)

1. An osmosis apparatus, comprising:
a reaction chamber constructed and arranged to receive at least one substrate having a permeable material thereon;
a first precursor source constructed and arranged to provide a vapor of a first precursor comprising a silicon compound;
a precursor distribution system and a removal system constructed and arranged to provide vapor of the first precursor from the first precursor source to the reaction chamber and to remove vapor of the first precursor from the reaction chamber; and
a sequence controller operably connected to the precursor distribution system and removal system and comprising a memory, the memory being programmed to perform infiltration of the permeable material when run on the sequence controller by;
activating the precursor distribution system and removal system to provide the vapor of the first precursor to the permeable material on the substrate in the reaction chamber, thereby causing the permeable material on the substrate in the reaction chamber to be permeated with silicon atoms by reaction of the vapor of the first precursor with the permeable material.
2. The apparatus of claim 1, wherein the first precursor source is constructed and arranged to provide a vapor of substituted silane.
3. The apparatus of claim 2, wherein the first precursor source is constructed and arranged to provide a vapor of an aminosilane.
4. The apparatus of claim 1, wherein the first precursor source is constructed and arranged to provide a vapor comprising a compound of 3-aminopropyl and silicon.
5. The apparatus of claim 1, wherein the first precursor source is constructed and arranged to provide a vapor of a silicon precursor comprising an alkoxide ligand and an additional ligand other than the alkoxide ligand.
6. The apparatus of claim 1, wherein the first precursor source is constructed and arranged to provide a vapor of 3-Aminopropyltriethoxysilane (APTES).
7. The apparatus of claim 1, wherein the first precursor source is constructed and arranged to provide a vapor of a silicon precursor comprising an amino-substituted alkyl group attached to a silicon atom.
8. The apparatus of claim 1, wherein the first precursor source is constructed and arranged to provide a vapor of 3-aminopropyl-trimethoxysilane (APTMS).
9. The apparatus of claim 1, wherein the first precursor source is constructed and arranged to provide a vapor of a silicon compound comprising a halide.
10. The apparatus of claim 9, wherein the first precursor source is constructed and arranged to provide a vapor of a silicon halide, a silane halide, or a silane comprising a halide.
11. The apparatus of claim 9, wherein the silicon compound comprises a chloride.
12. The apparatus of claim 11, wherein the first precursor source is constructed and arranged to provide Hexachlorodisilane (HCDS), Dichlorosilane (DCS), or silicon tetrachloride (SiCl)4) Vapor of at least one of the above.
13. The apparatus of claim 1, wherein the apparatus comprises a second precursor source constructed and arranged to provide a vapor of a second precursor comprising a silicon compound; and the precursor distribution system and removal system are constructed and arranged to provide vapor of the second precursor from the second precursor source to the reaction chamber, and the program in the memory is programmed to perform infiltration of the permeable material when run on the sequence controller by; activating the precursor distribution system and removal system to provide the vapor of the second precursor to the reaction chamber, whereby the permeable material on the substrate within the reaction chamber is permeated with silicon atoms from the vapor of the second precursor.
14. The apparatus of claim 13, wherein the second precursor source is constructed and arranged to provide a vapor of a silicon compound different from the first precursor.
15. The apparatus of claim 13, wherein the program in the memory is programmed to perform infiltration of the permeable material when run on the sequence controller by; activating the precursor distribution system and the removal system to simultaneously provide the second precursor and the first precursor.
16. The apparatus of claim 13, wherein the program in the memory is programmed to perform infiltration of the permeable material when run on the sequence controller by; activating the precursor distribution system and removal system to provide the second precursor after the first precursor.
17. The apparatus of claim 1, wherein the apparatus is a sequential osmosis synthesis apparatus, further comprising:
a reactant source vessel and reactant supply lines constructed and arranged to provide a reactant comprising an oxygen precursor to the reaction chamber, wherein the program in the memory of the sequence controller is programmed to perform permeation of the permeable material when run on the sequence controller by: activating the precursor distribution system and the removal system to remove gas from the reaction chamber; and activating the precursor distribution system and removal system to provide the reactant comprising the oxygen precursor to the reaction chamber, thereby causing the permeable material on the substrate in the reaction chamber to be permeated with silicon atoms and oxygen atoms by reaction of the first precursor and the reactant comprising the oxygen precursor with the permeable material.
18. The apparatus of claim 17, wherein the reactant source vessel further comprises a water (H) constructed and arranged to evaporate2O) or hydrogen peroxide (H)2O2) A reactant vaporizer of at least one of (a).
19. The apparatus of claim 17, wherein the reactant source vessel contains a gas comprising ozone (O)3) And molecular oxygen (O)2) A gaseous oxygen precursor of at least one of (a).
20. The apparatus of claim 17, wherein the apparatus further comprises a plasma generator constructed and arranged to generate a plasma from the oxygen precursor, thereby providing one or more of atomic oxygen, oxygen radicals, and excited species of oxygen to the reaction chamber.
21. The apparatus of claim 17, wherein the apparatus comprises a second precursor source constructed and arranged to vaporize a vapor of a second precursor comprising a silicon compound; and the precursor distribution system and removal system are constructed and arranged to provide vapor of the second precursor from the second precursor source to the reaction chamber, and the program in the memory is programmed to perform infiltration of the permeable material when run on the sequence controller by; activating the precursor distribution system and the removal system to provide a vapor of the second precursor.
22. The apparatus of claim 21, wherein the program in the memory is programmed to perform infiltration of the permeable material when run on the sequence controller by: activating the precursor distribution system and the removal system to provide the first precursor, subsequently providing the reactant, subsequently providing the second precursor, and subsequently providing the reactant.
23. The apparatus of claim 21, wherein the program in the memory is programmed to perform infiltration of the permeable material when run on the sequence controller by: activating the precursor distribution system and the removal system to repeat the providing the first precursor, then providing the reactant, then providing the second precursor, and then providing the reactant a plurality of times.
24. The apparatus of claim 21, wherein the program in the memory is programmed to perform infiltration of the permeable material when run on the sequence controller by: activating the precursor distribution system and the removal system to remove the precursor and/or reactant from the reaction chamber between providing the first precursor, subsequently providing the reactant, subsequently providing the second precursor, and subsequently providing each of the reactants.
25. A method of permeating a permeable material comprising:
providing a substrate having the permeable material disposed thereon in a reaction chamber;
providing a first precursor comprising a silicon compound to the permeable material in the reaction chamber for a first period of time (Tp)1) Thereby causing the permeable material on the substrate disposed within the reaction chamber to be permeated with silicon atoms; and is
Purging the reaction chamber for a second period of time (T)2)。
26. The method of claim 25, wherein the permeable material comprises at least one of a photoresist, an Extreme Ultraviolet (EUV) resist, a Chemically Amplified Resist (CAR), an electron beam resist, an immersion photoresist, a porous material, or a hardmask material.
27. The method of claim 25, wherein the first precursor comprises at least one of an aminosilane, an ethoxysilane, a methoxysilane, or a silicon halide.
28. The method of claim 27, wherein the first precursor comprises at least one of 3-Aminopropyltriethoxysilane (APTES), or Hexachlorodisilane (HCSD).
29. Method according to claim 25, wherein said first period of time (T)1) Between approximately 25 milliseconds and approximately 10 hours.
30. Method according to claim 25, wherein said second period of time (T)2) Between approximately 25 milliseconds and approximately 10 hours.
31. The method of claim 25, further comprising repeating the steps of providing the first precursor and subsequently purging the reaction chamber one or more times until a desired atomic% of silicon atoms are infiltrated into the permeable material.
32. The method of claim 25, wherein the permeable material being infiltrated comprises greater than 0.1 atomic% silicon atoms.
33. The method of claim 25, wherein infiltrating silicon atoms are uniformly distributed within the permeable material.
34. The method of claim 25, wherein the method further comprises:
providing a second precursor comprising a silicon compound to the permeable material in the reaction chamber for a third period of time (Tp)3) Whereby the liner disposed within the reaction chamberThe permeable material on the substrate is infiltrated with silicon atoms.
35. The method of claim 34, wherein the first precursor is different from the second precursor.
36. The method of claim 34, further comprising providing the first precursor and the second precursor simultaneously to the permeable material in the reaction chamber.
37. The method of claim 34, further comprising purging the reaction chamber for a fourth period of time (T) after providing the second precursor to the permeable material4)。
38. The method of claim 37, further comprising repeating the steps of: providing the first precursor, subsequently purging the reaction chamber, subsequently providing the second precursor, and subsequently purging the reaction chamber one or more times.
39. The method of claim 34, wherein the permeable material being infiltrated comprises greater than 0.1 atomic percent of silicon atoms.
40. Method according to claim 34, wherein said third period of time (T)3) Between approximately 25 milliseconds and approximately 10 hours.
41. Method according to claim 37, wherein said fourth period of time (T)4) Between approximately 25 milliseconds and approximately 10 hours.
42. The method of claim 25, wherein the method further comprises:
providing a reactant comprising an oxygen precursor to the permeable material in the reaction chamber for a fifth period of time (T;)5) Thereby disposing the substrate in the reaction chamberThe permeable material of (a) is permeated by oxygen atoms.
43. The method of claim 42, wherein the permeable material is infiltrated with silica.
44. The method of claim 42, wherein the oxygen precursor comprises a vapor of at least one of: water (H)2O), ozone (O)3) Molecular oxygen (O)2) Or hydrogen peroxide (H)2O2)。
45. The method of claim 42, wherein the oxygen precursor comprises an oxygen-based plasma comprising oxygen atoms, oxygen ions, oxygen radicals, and excited species of oxygen.
46. The method of claim 42, wherein the method further comprises performing one or more sequential osmotic synthesis (SIS) cycles, a unit SIS cycle comprising:
providing the first precursor comprising a silicon compound to the permeable material; and is
Providing the reactant comprising the oxygen precursor to the permeable material.
47. The method of claim 46, wherein a unit SIS cycle further comprises providing a second precursor comprising a silicon compound to the permeable material, wherein the second precursor is different than the first precursor.
48. The method of claim 46, wherein a unit SIS cycle further comprises purging the reaction chamber between each step of the SIS cycle.
49. The method according to claim 42, wherein said fifth time period (T)5) Between approximately 25 milliseconds and 10 hours.
50. A semiconductor device structure, comprising:
a substrate; and
an interpenetrating polymer resist member disposed on a surface of the substrate, the interpenetrating polymer resist member comprising:
an organic component; and
an inorganic component comprising a plurality of silicon (Si) atoms infiltrated into the organic component.
51. The structure of claim 50, wherein a concentration of the plurality of silicon atoms infiltrated into the organic component is greater than 0.1 atomic%.
52. The structure of claim 50, wherein the plurality of silicon atoms infiltrated into the organic component are uniformly distributed throughout the organic component.
53. The structure of claim 50, wherein the inorganic component further comprises a plurality of oxygen atoms that permeate into the organic component.
54. The structure of claim 53 wherein the plurality of silicon atoms are selected from the group consisting of elemental silicon (Si) and silicon oxide (Si)xOy) Forms are disposed within the organic component.
55. The structure of claim 53 wherein the inorganic component further comprises silicon oxide (Si)xOy)。
56. The structure of claim 50, wherein the penetrating polymer resist comprises at least one of a photoresist, an Extreme Ultraviolet (EUV) resist, an immersion photoresist, a Chemically Amplified Resist (CAR), or an e-beam resist.
CN201980034922.5A 2018-06-01 2019-05-29 Infiltration apparatus and method of infiltrating permeable material Active CN112204166B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/996,286 US20190368040A1 (en) 2018-06-01 2018-06-01 Infiltration apparatus and methods of infiltrating an infiltrateable material
US15/996,286 2018-06-01
PCT/IB2019/000729 WO2019229537A2 (en) 2018-06-01 2019-05-29 Infiltration apparatus and methods of infiltrating an infiltrateable material

Publications (2)

Publication Number Publication Date
CN112204166A true CN112204166A (en) 2021-01-08
CN112204166B CN112204166B (en) 2024-01-26

Family

ID=68172230

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980034922.5A Active CN112204166B (en) 2018-06-01 2019-05-29 Infiltration apparatus and method of infiltrating permeable material

Country Status (6)

Country Link
US (1) US20190368040A1 (en)
JP (1) JP7420744B2 (en)
KR (1) KR20210016349A (en)
CN (1) CN112204166B (en)
TW (1) TWI826451B (en)
WO (1) WO2019229537A2 (en)

Families Citing this family (244)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9394608B2 (en) 2009-04-06 2016-07-19 Asm America, Inc. Semiconductor processing reactor and components thereof
US8802201B2 (en) 2009-08-14 2014-08-12 Asm America, Inc. Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
US9312155B2 (en) 2011-06-06 2016-04-12 Asm Japan K.K. High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules
US20130023129A1 (en) 2011-07-20 2013-01-24 Asm America, Inc. Pressure transmitter for a semiconductor processing environment
US9017481B1 (en) 2011-10-28 2015-04-28 Asm America, Inc. Process feed management for semiconductor substrate processing
US10714315B2 (en) 2012-10-12 2020-07-14 Asm Ip Holdings B.V. Semiconductor reaction chamber showerhead
US20160376700A1 (en) 2013-02-01 2016-12-29 Asm Ip Holding B.V. System for treatment of deposition reactor
US10683571B2 (en) 2014-02-25 2020-06-16 Asm Ip Holding B.V. Gas supply manifold and method of supplying gases to chamber using same
US11015245B2 (en) 2014-03-19 2021-05-25 Asm Ip Holding B.V. Gas-phase reactor and system having exhaust plenum and components thereof
US10858737B2 (en) 2014-07-28 2020-12-08 Asm Ip Holding B.V. Showerhead assembly and components thereof
US9890456B2 (en) 2014-08-21 2018-02-13 Asm Ip Holding B.V. Method and system for in situ formation of gas-phase compounds
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
US10458018B2 (en) 2015-06-26 2019-10-29 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US10211308B2 (en) 2015-10-21 2019-02-19 Asm Ip Holding B.V. NbMC layers
US11139308B2 (en) 2015-12-29 2021-10-05 Asm Ip Holding B.V. Atomic layer deposition of III-V compounds to form V-NAND devices
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10190213B2 (en) 2016-04-21 2019-01-29 Asm Ip Holding B.V. Deposition of metal borides
US10865475B2 (en) 2016-04-21 2020-12-15 Asm Ip Holding B.V. Deposition of metal borides and silicides
US10367080B2 (en) 2016-05-02 2019-07-30 Asm Ip Holding B.V. Method of forming a germanium oxynitride film
US10032628B2 (en) 2016-05-02 2018-07-24 Asm Ip Holding B.V. Source/drain performance through conformal solid state doping
US11453943B2 (en) 2016-05-25 2022-09-27 Asm Ip Holding B.V. Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US10714385B2 (en) 2016-07-19 2020-07-14 Asm Ip Holding B.V. Selective deposition of tungsten
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
KR102532607B1 (en) 2016-07-28 2023-05-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and method of operating the same
US10643826B2 (en) 2016-10-26 2020-05-05 Asm Ip Holdings B.V. Methods for thermally calibrating reaction chambers
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US10229833B2 (en) 2016-11-01 2019-03-12 Asm Ip Holding B.V. Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
KR102546317B1 (en) 2016-11-15 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Gas supply unit and substrate processing apparatus including the same
KR20180068582A (en) 2016-12-14 2018-06-22 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11447861B2 (en) 2016-12-15 2022-09-20 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
US11581186B2 (en) * 2016-12-15 2023-02-14 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus
KR20180070971A (en) 2016-12-19 2018-06-27 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US10269558B2 (en) 2016-12-22 2019-04-23 Asm Ip Holding B.V. Method of forming a structure on a substrate
US10867788B2 (en) 2016-12-28 2020-12-15 Asm Ip Holding B.V. Method of forming a structure on a substrate
US11390950B2 (en) 2017-01-10 2022-07-19 Asm Ip Holding B.V. Reactor system and method to reduce residue buildup during a film deposition process
US10655221B2 (en) 2017-02-09 2020-05-19 Asm Ip Holding B.V. Method for depositing oxide film by thermal ALD and PEALD
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10529563B2 (en) 2017-03-29 2020-01-07 Asm Ip Holdings B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
KR102457289B1 (en) 2017-04-25 2022-10-21 에이에스엠 아이피 홀딩 비.브이. Method for depositing a thin film and manufacturing a semiconductor device
US10770286B2 (en) 2017-05-08 2020-09-08 Asm Ip Holdings B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
US10892156B2 (en) 2017-05-08 2021-01-12 Asm Ip Holding B.V. Methods for forming a silicon nitride film on a substrate and related semiconductor device structures
US11306395B2 (en) 2017-06-28 2022-04-19 Asm Ip Holding B.V. Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
US10685834B2 (en) 2017-07-05 2020-06-16 Asm Ip Holdings B.V. Methods for forming a silicon germanium tin layer and related semiconductor device structures
KR20190009245A (en) 2017-07-18 2019-01-28 에이에스엠 아이피 홀딩 비.브이. Methods for forming a semiconductor device structure and related semiconductor device structures
US11374112B2 (en) 2017-07-19 2022-06-28 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US10541333B2 (en) 2017-07-19 2020-01-21 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US11018002B2 (en) 2017-07-19 2021-05-25 Asm Ip Holding B.V. Method for selectively depositing a Group IV semiconductor and related semiconductor device structures
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10770336B2 (en) 2017-08-08 2020-09-08 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US10692741B2 (en) 2017-08-08 2020-06-23 Asm Ip Holdings B.V. Radiation shield
US11139191B2 (en) 2017-08-09 2021-10-05 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US10249524B2 (en) 2017-08-09 2019-04-02 Asm Ip Holding B.V. Cassette holder assembly for a substrate cassette and holding member for use in such assembly
US11769682B2 (en) 2017-08-09 2023-09-26 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11830730B2 (en) 2017-08-29 2023-11-28 Asm Ip Holding B.V. Layer forming method and apparatus
KR102491945B1 (en) 2017-08-30 2023-01-26 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11295980B2 (en) 2017-08-30 2022-04-05 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
US11056344B2 (en) 2017-08-30 2021-07-06 Asm Ip Holding B.V. Layer forming method
KR102630301B1 (en) 2017-09-21 2024-01-29 에이에스엠 아이피 홀딩 비.브이. Method of sequential infiltration synthesis treatment of infiltrateable material and structures and devices formed using same
US10844484B2 (en) 2017-09-22 2020-11-24 Asm Ip Holding B.V. Apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US10658205B2 (en) 2017-09-28 2020-05-19 Asm Ip Holdings B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
US10403504B2 (en) 2017-10-05 2019-09-03 Asm Ip Holding B.V. Method for selectively depositing a metallic film on a substrate
US10319588B2 (en) 2017-10-10 2019-06-11 Asm Ip Holding B.V. Method for depositing a metal chalcogenide on a substrate by cyclical deposition
US10923344B2 (en) 2017-10-30 2021-02-16 Asm Ip Holding B.V. Methods for forming a semiconductor structure and related semiconductor structures
US10910262B2 (en) 2017-11-16 2021-02-02 Asm Ip Holding B.V. Method of selectively depositing a capping layer structure on a semiconductor device structure
KR102443047B1 (en) 2017-11-16 2022-09-14 에이에스엠 아이피 홀딩 비.브이. Method of processing a substrate and a device manufactured by the same
US11022879B2 (en) 2017-11-24 2021-06-01 Asm Ip Holding B.V. Method of forming an enhanced unexposed photoresist layer
JP7214724B2 (en) 2017-11-27 2023-01-30 エーエスエム アイピー ホールディング ビー.ブイ. Storage device for storing wafer cassettes used in batch furnaces
TWI791689B (en) 2017-11-27 2023-02-11 荷蘭商Asm智慧財產控股私人有限公司 Apparatus including a clean mini environment
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
TW202325889A (en) 2018-01-19 2023-07-01 荷蘭商Asm 智慧財產控股公司 Deposition method
CN111630203A (en) 2018-01-19 2020-09-04 Asm Ip私人控股有限公司 Method for depositing gap filling layer by plasma auxiliary deposition
USD903477S1 (en) 2018-01-24 2020-12-01 Asm Ip Holdings B.V. Metal clamp
US11018047B2 (en) 2018-01-25 2021-05-25 Asm Ip Holding B.V. Hybrid lift pin
USD880437S1 (en) 2018-02-01 2020-04-07 Asm Ip Holding B.V. Gas supply plate for semiconductor manufacturing apparatus
US11081345B2 (en) 2018-02-06 2021-08-03 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
JP7124098B2 (en) 2018-02-14 2022-08-23 エーエスエム・アイピー・ホールディング・ベー・フェー Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
US10896820B2 (en) 2018-02-14 2021-01-19 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
US10731249B2 (en) 2018-02-15 2020-08-04 Asm Ip Holding B.V. Method of forming a transition metal containing film on a substrate by a cyclical deposition process, a method for supplying a transition metal halide compound to a reaction chamber, and related vapor deposition apparatus
KR102636427B1 (en) 2018-02-20 2024-02-13 에이에스엠 아이피 홀딩 비.브이. Substrate processing method and apparatus
US10975470B2 (en) 2018-02-23 2021-04-13 Asm Ip Holding B.V. Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment
US11473195B2 (en) 2018-03-01 2022-10-18 Asm Ip Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
US11629406B2 (en) 2018-03-09 2023-04-18 Asm Ip Holding B.V. Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate
US11114283B2 (en) 2018-03-16 2021-09-07 Asm Ip Holding B.V. Reactor, system including the reactor, and methods of manufacturing and using same
KR102646467B1 (en) 2018-03-27 2024-03-11 에이에스엠 아이피 홀딩 비.브이. Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
US11088002B2 (en) 2018-03-29 2021-08-10 Asm Ip Holding B.V. Substrate rack and a substrate processing system and method
US11230766B2 (en) 2018-03-29 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
KR102501472B1 (en) 2018-03-30 2023-02-20 에이에스엠 아이피 홀딩 비.브이. Substrate processing method
KR20190128558A (en) 2018-05-08 2019-11-18 에이에스엠 아이피 홀딩 비.브이. Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures
TW202349473A (en) 2018-05-11 2023-12-16 荷蘭商Asm Ip私人控股有限公司 Methods for forming a doped metal carbide film on a substrate and related semiconductor device structures
KR102596988B1 (en) 2018-05-28 2023-10-31 에이에스엠 아이피 홀딩 비.브이. Method of processing a substrate and a device manufactured by the same
US11270899B2 (en) 2018-06-04 2022-03-08 Asm Ip Holding B.V. Wafer handling chamber with moisture reduction
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
US11286562B2 (en) 2018-06-08 2022-03-29 Asm Ip Holding B.V. Gas-phase chemical reactor and method of using same
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
KR102568797B1 (en) 2018-06-21 2023-08-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing system
WO2020003000A1 (en) 2018-06-27 2020-01-02 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
CN112292478A (en) 2018-06-27 2021-01-29 Asm Ip私人控股有限公司 Cyclic deposition methods for forming metal-containing materials and films and structures containing metal-containing materials
US10612136B2 (en) 2018-06-29 2020-04-07 ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
KR20200002519A (en) 2018-06-29 2020-01-08 에이에스엠 아이피 홀딩 비.브이. Method for depositing a thin film and manufacturing a semiconductor device
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10767789B2 (en) 2018-07-16 2020-09-08 Asm Ip Holding B.V. Diaphragm valves, valve components, and methods for forming valve components
US11053591B2 (en) 2018-08-06 2021-07-06 Asm Ip Holding B.V. Multi-port gas injection system and reactor system including same
US10883175B2 (en) 2018-08-09 2021-01-05 Asm Ip Holding B.V. Vertical furnace for processing substrates and a liner for use therein
US10829852B2 (en) 2018-08-16 2020-11-10 Asm Ip Holding B.V. Gas distribution device for a wafer processing apparatus
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
KR20200030162A (en) 2018-09-11 2020-03-20 에이에스엠 아이피 홀딩 비.브이. Method for deposition of a thin film
US11049751B2 (en) 2018-09-14 2021-06-29 Asm Ip Holding B.V. Cassette supply system to store and handle cassettes and processing apparatus equipped therewith
CN110970344A (en) 2018-10-01 2020-04-07 Asm Ip控股有限公司 Substrate holding apparatus, system including the same, and method of using the same
US11232963B2 (en) 2018-10-03 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
KR102592699B1 (en) 2018-10-08 2023-10-23 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same
US10847365B2 (en) 2018-10-11 2020-11-24 Asm Ip Holding B.V. Method of forming conformal silicon carbide film by cyclic CVD
US10811256B2 (en) 2018-10-16 2020-10-20 Asm Ip Holding B.V. Method for etching a carbon-containing feature
KR102546322B1 (en) 2018-10-19 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
KR102605121B1 (en) 2018-10-19 2023-11-23 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
USD948463S1 (en) 2018-10-24 2022-04-12 Asm Ip Holding B.V. Susceptor for semiconductor substrate supporting apparatus
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
KR20200051105A (en) 2018-11-02 2020-05-13 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and substrate processing apparatus including the same
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US11031242B2 (en) 2018-11-07 2021-06-08 Asm Ip Holding B.V. Methods for depositing a boron doped silicon germanium film
US10847366B2 (en) 2018-11-16 2020-11-24 Asm Ip Holding B.V. Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
US11217444B2 (en) 2018-11-30 2022-01-04 Asm Ip Holding B.V. Method for forming an ultraviolet radiation responsive metal oxide-containing film
KR102636428B1 (en) 2018-12-04 2024-02-13 에이에스엠 아이피 홀딩 비.브이. A method for cleaning a substrate processing apparatus
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
JP2020096183A (en) 2018-12-14 2020-06-18 エーエスエム・アイピー・ホールディング・ベー・フェー Method of forming device structure using selective deposition of gallium nitride, and system for the same
TWI819180B (en) 2019-01-17 2023-10-21 荷蘭商Asm 智慧財產控股公司 Methods of forming a transition metal containing film on a substrate by a cyclical deposition process
KR20200091543A (en) 2019-01-22 2020-07-31 에이에스엠 아이피 홀딩 비.브이. Semiconductor processing device
CN111524788B (en) 2019-02-01 2023-11-24 Asm Ip私人控股有限公司 Method for topologically selective film formation of silicon oxide
TW202104632A (en) 2019-02-20 2021-02-01 荷蘭商Asm Ip私人控股有限公司 Cyclical deposition method and apparatus for filling a recess formed within a substrate surface
KR20200102357A (en) 2019-02-20 2020-08-31 에이에스엠 아이피 홀딩 비.브이. Apparatus and methods for plug fill deposition in 3-d nand applications
KR102626263B1 (en) 2019-02-20 2024-01-16 에이에스엠 아이피 홀딩 비.브이. Cyclical deposition method including treatment step and apparatus for same
TW202044325A (en) 2019-02-20 2020-12-01 荷蘭商Asm Ip私人控股有限公司 Method of filling a recess formed within a surface of a substrate, semiconductor structure formed according to the method, and semiconductor processing apparatus
TW202100794A (en) 2019-02-22 2021-01-01 荷蘭商Asm Ip私人控股有限公司 Substrate processing apparatus and method for processing substrate
KR20200108243A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Structure Including SiOC Layer and Method of Forming Same
KR20200108242A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer
US11742198B2 (en) 2019-03-08 2023-08-29 Asm Ip Holding B.V. Structure including SiOCN layer and method of forming same
KR20200116033A (en) 2019-03-28 2020-10-08 에이에스엠 아이피 홀딩 비.브이. Door opener and substrate processing apparatus provided therewith
KR20200116855A (en) 2019-04-01 2020-10-13 에이에스엠 아이피 홀딩 비.브이. Method of manufacturing semiconductor device
KR20200123380A (en) 2019-04-19 2020-10-29 에이에스엠 아이피 홀딩 비.브이. Layer forming method and apparatus
KR20200125453A (en) 2019-04-24 2020-11-04 에이에스엠 아이피 홀딩 비.브이. Gas-phase reactor system and method of using same
KR20200130121A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Chemical source vessel with dip tube
KR20200130118A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Method for Reforming Amorphous Carbon Polymer Film
KR20200130652A (en) 2019-05-10 2020-11-19 에이에스엠 아이피 홀딩 비.브이. Method of depositing material onto a surface and structure formed according to the method
JP2020188255A (en) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー.ブイ. Wafer boat handling device, vertical batch furnace, and method
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
USD975665S1 (en) 2019-05-17 2023-01-17 Asm Ip Holding B.V. Susceptor shaft
USD935572S1 (en) 2019-05-24 2021-11-09 Asm Ip Holding B.V. Gas channel plate
USD922229S1 (en) 2019-06-05 2021-06-15 Asm Ip Holding B.V. Device for controlling a temperature of a gas supply unit
KR20200141003A (en) 2019-06-06 2020-12-17 에이에스엠 아이피 홀딩 비.브이. Gas-phase reactor system including a gas detector
KR20200143254A (en) 2019-06-11 2020-12-23 에이에스엠 아이피 홀딩 비.브이. Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method
USD944946S1 (en) 2019-06-14 2022-03-01 Asm Ip Holding B.V. Shower plate
USD931978S1 (en) 2019-06-27 2021-09-28 Asm Ip Holding B.V. Showerhead vacuum transport
KR20210005515A (en) 2019-07-03 2021-01-14 에이에스엠 아이피 홀딩 비.브이. Temperature control assembly for substrate processing apparatus and method of using same
JP2021015791A (en) 2019-07-09 2021-02-12 エーエスエム アイピー ホールディング ビー.ブイ. Plasma device and substrate processing method using coaxial waveguide
CN112216646A (en) 2019-07-10 2021-01-12 Asm Ip私人控股有限公司 Substrate supporting assembly and substrate processing device comprising same
KR20210010307A (en) 2019-07-16 2021-01-27 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
KR20210010816A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Radical assist ignition plasma system and method
KR20210010820A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Methods of forming silicon germanium structures
US11643724B2 (en) 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
CN112242296A (en) 2019-07-19 2021-01-19 Asm Ip私人控股有限公司 Method of forming topologically controlled amorphous carbon polymer films
TW202113936A (en) 2019-07-29 2021-04-01 荷蘭商Asm Ip私人控股有限公司 Methods for selective deposition utilizing n-type dopants and/or alternative dopants to achieve high dopant incorporation
CN112309899A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112309900A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
US11587815B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587814B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11227782B2 (en) 2019-07-31 2022-01-18 Asm Ip Holding B.V. Vertical batch furnace assembly
CN112323048B (en) 2019-08-05 2024-02-09 Asm Ip私人控股有限公司 Liquid level sensor for chemical source container
USD965524S1 (en) 2019-08-19 2022-10-04 Asm Ip Holding B.V. Susceptor support
USD965044S1 (en) 2019-08-19 2022-09-27 Asm Ip Holding B.V. Susceptor shaft
JP2021031769A (en) 2019-08-21 2021-03-01 エーエスエム アイピー ホールディング ビー.ブイ. Production apparatus of mixed gas of film deposition raw material and film deposition apparatus
USD930782S1 (en) 2019-08-22 2021-09-14 Asm Ip Holding B.V. Gas distributor
KR20210024423A (en) 2019-08-22 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for forming a structure with a hole
USD940837S1 (en) 2019-08-22 2022-01-11 Asm Ip Holding B.V. Electrode
USD949319S1 (en) 2019-08-22 2022-04-19 Asm Ip Holding B.V. Exhaust duct
USD979506S1 (en) 2019-08-22 2023-02-28 Asm Ip Holding B.V. Insulator
US11286558B2 (en) 2019-08-23 2022-03-29 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
KR20210024420A (en) 2019-08-23 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane
KR20210029090A (en) 2019-09-04 2021-03-15 에이에스엠 아이피 홀딩 비.브이. Methods for selective deposition using a sacrificial capping layer
KR20210029663A (en) 2019-09-05 2021-03-16 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
CN112593212B (en) 2019-10-02 2023-12-22 Asm Ip私人控股有限公司 Method for forming topologically selective silicon oxide film by cyclic plasma enhanced deposition process
TW202129060A (en) 2019-10-08 2021-08-01 荷蘭商Asm Ip控股公司 Substrate processing device, and substrate processing method
KR20210043460A (en) 2019-10-10 2021-04-21 에이에스엠 아이피 홀딩 비.브이. Method of forming a photoresist underlayer and structure including same
KR20210045930A (en) 2019-10-16 2021-04-27 에이에스엠 아이피 홀딩 비.브이. Method of Topology-Selective Film Formation of Silicon Oxide
US11637014B2 (en) 2019-10-17 2023-04-25 Asm Ip Holding B.V. Methods for selective deposition of doped semiconductor material
KR20210047808A (en) 2019-10-21 2021-04-30 에이에스엠 아이피 홀딩 비.브이. Apparatus and methods for selectively etching films
US11646205B2 (en) 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
KR20210054983A (en) 2019-11-05 2021-05-14 에이에스엠 아이피 홀딩 비.브이. Structures with doped semiconductor layers and methods and systems for forming same
US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
KR20210062561A (en) 2019-11-20 2021-05-31 에이에스엠 아이피 홀딩 비.브이. Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure
CN112951697A (en) 2019-11-26 2021-06-11 Asm Ip私人控股有限公司 Substrate processing apparatus
US11450529B2 (en) 2019-11-26 2022-09-20 Asm Ip Holding B.V. Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface
CN112885692A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112885693A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
JP2021090042A (en) 2019-12-02 2021-06-10 エーエスエム アイピー ホールディング ビー.ブイ. Substrate processing apparatus and substrate processing method
KR20210070898A (en) 2019-12-04 2021-06-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11885013B2 (en) 2019-12-17 2024-01-30 Asm Ip Holding B.V. Method of forming vanadium nitride layer and structure including the vanadium nitride layer
KR20210080214A (en) 2019-12-19 2021-06-30 에이에스엠 아이피 홀딩 비.브이. Methods for filling a gap feature on a substrate and related semiconductor structures
KR20210095050A (en) 2020-01-20 2021-07-30 에이에스엠 아이피 홀딩 비.브이. Method of forming thin film and method of modifying surface of thin film
TW202130846A (en) 2020-02-03 2021-08-16 荷蘭商Asm Ip私人控股有限公司 Method of forming structures including a vanadium or indium layer
TW202146882A (en) 2020-02-04 2021-12-16 荷蘭商Asm Ip私人控股有限公司 Method of verifying an article, apparatus for verifying an article, and system for verifying a reaction chamber
US11776846B2 (en) 2020-02-07 2023-10-03 Asm Ip Holding B.V. Methods for depositing gap filling fluids and related systems and devices
TW202146715A (en) 2020-02-17 2021-12-16 荷蘭商Asm Ip私人控股有限公司 Method for growing phosphorous-doped silicon layer and system of the same
KR20210116240A (en) 2020-03-11 2021-09-27 에이에스엠 아이피 홀딩 비.브이. Substrate handling device with adjustable joints
KR20210116249A (en) 2020-03-11 2021-09-27 에이에스엠 아이피 홀딩 비.브이. lockout tagout assembly and system and method of using same
KR20210117157A (en) 2020-03-12 2021-09-28 에이에스엠 아이피 홀딩 비.브이. Method for Fabricating Layer Structure Having Target Topological Profile
KR20210124042A (en) 2020-04-02 2021-10-14 에이에스엠 아이피 홀딩 비.브이. Thin film forming method
TW202146689A (en) 2020-04-03 2021-12-16 荷蘭商Asm Ip控股公司 Method for forming barrier layer and method for manufacturing semiconductor device
TW202145344A (en) 2020-04-08 2021-12-01 荷蘭商Asm Ip私人控股有限公司 Apparatus and methods for selectively etching silcon oxide films
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
KR20210132600A (en) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element
KR20210132605A (en) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. Vertical batch furnace assembly comprising a cooling gas supply
CN113555279A (en) 2020-04-24 2021-10-26 Asm Ip私人控股有限公司 Method of forming vanadium nitride-containing layers and structures including the same
KR20210134226A (en) 2020-04-29 2021-11-09 에이에스엠 아이피 홀딩 비.브이. Solid source precursor vessel
KR20210134869A (en) 2020-05-01 2021-11-11 에이에스엠 아이피 홀딩 비.브이. Fast FOUP swapping with a FOUP handler
KR20210141379A (en) 2020-05-13 2021-11-23 에이에스엠 아이피 홀딩 비.브이. Laser alignment fixture for a reactor system
KR20210143653A (en) 2020-05-19 2021-11-29 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
KR20210145078A (en) 2020-05-21 2021-12-01 에이에스엠 아이피 홀딩 비.브이. Structures including multiple carbon layers and methods of forming and using same
TW202201602A (en) 2020-05-29 2022-01-01 荷蘭商Asm Ip私人控股有限公司 Substrate processing device
TW202218133A (en) 2020-06-24 2022-05-01 荷蘭商Asm Ip私人控股有限公司 Method for forming a layer provided with silicon
TW202217953A (en) 2020-06-30 2022-05-01 荷蘭商Asm Ip私人控股有限公司 Substrate processing method
KR20220010438A (en) 2020-07-17 2022-01-25 에이에스엠 아이피 홀딩 비.브이. Structures and methods for use in photolithography
TW202204662A (en) 2020-07-20 2022-02-01 荷蘭商Asm Ip私人控股有限公司 Method and system for depositing molybdenum layers
TW202212623A (en) 2020-08-26 2022-04-01 荷蘭商Asm Ip私人控股有限公司 Method of forming metal silicon oxide layer and metal silicon oxynitride layer, semiconductor structure, and system
USD990534S1 (en) 2020-09-11 2023-06-27 Asm Ip Holding B.V. Weighted lift pin
USD1012873S1 (en) 2020-09-24 2024-01-30 Asm Ip Holding B.V. Electrode for semiconductor processing apparatus
TW202229613A (en) 2020-10-14 2022-08-01 荷蘭商Asm Ip私人控股有限公司 Method of depositing material on stepped structure
TW202217037A (en) 2020-10-22 2022-05-01 荷蘭商Asm Ip私人控股有限公司 Method of depositing vanadium metal, structure, device and a deposition assembly
TW202223136A (en) 2020-10-28 2022-06-16 荷蘭商Asm Ip私人控股有限公司 Method for forming layer on substrate, and semiconductor processing system
KR20220076343A (en) 2020-11-30 2022-06-08 에이에스엠 아이피 홀딩 비.브이. an injector configured for arrangement within a reaction chamber of a substrate processing apparatus
US11946137B2 (en) 2020-12-16 2024-04-02 Asm Ip Holding B.V. Runout and wobble measurement fixtures
TW202231903A (en) 2020-12-22 2022-08-16 荷蘭商Asm Ip私人控股有限公司 Transition metal deposition method, transition metal layer, and deposition assembly for depositing transition metal on substrate
USD1023959S1 (en) 2021-05-11 2024-04-23 Asm Ip Holding B.V. Electrode for substrate processing apparatus
USD981973S1 (en) 2021-05-11 2023-03-28 Asm Ip Holding B.V. Reactor wall for substrate processing apparatus
USD980813S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas flow control plate for substrate processing apparatus
USD980814S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas distributor for substrate processing apparatus
USD990441S1 (en) 2021-09-07 2023-06-27 Asm Ip Holding B.V. Gas flow control plate

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050255327A1 (en) * 2004-05-14 2005-11-17 Bryce Chaney Articles having bioactive surfaces and solvent-free methods of preparation thereof
US20120241411A1 (en) * 2011-03-24 2012-09-27 Uchicago Argonne Llc Sequential infiltration synthesis for advanced lithography
US20140120726A1 (en) * 2012-11-01 2014-05-01 Srinivas D. Nemani Method of patterning a low-k dielectric film
US20150152547A1 (en) * 2012-08-17 2015-06-04 Ihi Corporation Method and apparatus for manufacturing heat-resistant composite material
CN105845551A (en) * 2015-02-03 2016-08-10 朗姆研究公司 Metal doping of amorphous carbon and silicon films used as hardmasks in substrate processing systems
US20160305015A1 (en) * 2014-02-17 2016-10-20 Ihi Corporation Heat-resistant composite material production method and production device
US20180057931A1 (en) * 2016-08-30 2018-03-01 Rolls-Royce Corporation Swirled flow chemical vapor deposition

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6071562A (en) * 1998-05-07 2000-06-06 Lsi Logic Corporation Process for depositing titanium nitride films
JP2000031136A (en) 1998-07-09 2000-01-28 Tokai Carbon Co Ltd Protective member for plasma processing system
US6451512B1 (en) * 2000-05-01 2002-09-17 Advanced Micro Devices, Inc. UV-enhanced silylation process to increase etch resistance of ultra thin resists
US6861334B2 (en) * 2001-06-21 2005-03-01 Asm International, N.V. Method of fabricating trench isolation structures for integrated circuits using atomic layer deposition
US20040253377A1 (en) * 2002-10-24 2004-12-16 Bok Lowell D. Batch and continuous CVI densification furnace
US8152922B2 (en) 2003-08-29 2012-04-10 Asm America, Inc. Gas mixer and manifold assembly for ALD reactor
US7691443B2 (en) * 2005-05-31 2010-04-06 Goodrich Corporation Non-pressure gradient single cycle CVI/CVD apparatus and method
JP5200371B2 (en) * 2006-12-01 2013-06-05 東京エレクトロン株式会社 Film forming method, semiconductor device, and storage medium
US9018104B2 (en) * 2010-04-09 2015-04-28 Hitachi Kokusai Electric Inc. Method for manufacturing semiconductor device, method for processing substrate and substrate processing apparatus
US9147574B2 (en) 2013-03-14 2015-09-29 Tokyo Electron Limited Topography minimization of neutral layer overcoats in directed self-assembly applications
WO2014159427A1 (en) 2013-03-14 2014-10-02 Applied Materials, Inc Resist hardening and development processes for semiconductor device manufacturing
US9673042B2 (en) * 2015-09-01 2017-06-06 Applied Materials, Inc. Methods and apparatus for in-situ cleaning of copper surfaces and deposition and removal of self-assembled monolayers
US9786492B2 (en) 2015-11-12 2017-10-10 Asm Ip Holding B.V. Formation of SiOCN thin films
US10550010B2 (en) 2015-12-11 2020-02-04 Uchicago Argonne, Llc Oleophilic foams for oil spill mitigation
JP6545093B2 (en) 2015-12-14 2019-07-17 株式会社Kokusai Electric Semiconductor device manufacturing method, substrate processing apparatus and program
JP6573578B2 (en) * 2016-05-31 2019-09-11 株式会社Kokusai Electric Semiconductor device manufacturing method, substrate processing apparatus, and program
JP6456893B2 (en) * 2016-09-26 2019-01-23 株式会社Kokusai Electric Semiconductor device manufacturing method, recording medium, and substrate processing apparatus
US9916980B1 (en) * 2016-12-15 2018-03-13 Asm Ip Holding B.V. Method of forming a structure on a substrate

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050255327A1 (en) * 2004-05-14 2005-11-17 Bryce Chaney Articles having bioactive surfaces and solvent-free methods of preparation thereof
US20120241411A1 (en) * 2011-03-24 2012-09-27 Uchicago Argonne Llc Sequential infiltration synthesis for advanced lithography
US20150152547A1 (en) * 2012-08-17 2015-06-04 Ihi Corporation Method and apparatus for manufacturing heat-resistant composite material
US20140120726A1 (en) * 2012-11-01 2014-05-01 Srinivas D. Nemani Method of patterning a low-k dielectric film
US20160305015A1 (en) * 2014-02-17 2016-10-20 Ihi Corporation Heat-resistant composite material production method and production device
CN105845551A (en) * 2015-02-03 2016-08-10 朗姆研究公司 Metal doping of amorphous carbon and silicon films used as hardmasks in substrate processing systems
US20180057931A1 (en) * 2016-08-30 2018-03-01 Rolls-Royce Corporation Swirled flow chemical vapor deposition

Also Published As

Publication number Publication date
WO2019229537A3 (en) 2020-03-05
WO2019229537A2 (en) 2019-12-05
TWI826451B (en) 2023-12-21
JP2021525455A (en) 2021-09-24
TW202003914A (en) 2020-01-16
US20190368040A1 (en) 2019-12-05
CN112204166B (en) 2024-01-26
KR20210016349A (en) 2021-02-15
JP7420744B2 (en) 2024-01-23

Similar Documents

Publication Publication Date Title
CN112204166B (en) Infiltration apparatus and method of infiltrating permeable material
US20210247693A1 (en) Method of forming an enhanced unexposed photoresist layer
TWI827645B (en) Substrate processing apparatus and method
US9916980B1 (en) Method of forming a structure on a substrate
US20210033977A1 (en) Substrate processing apparatus and method
JP7050468B2 (en) Oxide thin film deposition
JP2024009207A (en) Method for forming transition metal containing film onto substrate by cyclical deposition process, method for supplying transition metal halide compound into reaction chamber, and related vapor deposition apparatus
US20200013629A1 (en) Semiconductor processing apparatus
CN111356785A (en) Method for ALD of metal oxides on metal surfaces
TWI589722B (en) Apparatuses and methods for depositing sic and sicn films via cross-metathesis reactions with organometallic co-reactants
JP2022101465A (en) Underlayer for photoresist adhesion and dose reduction
KR102021708B1 (en) Method for manufacturing semiconductor device, substrate processing apparatus and recording medium
US20220342301A1 (en) Photoresist with multiple patterning radiation-absorbing elements and/or vertical composition gradient
TW201623682A (en) Methods and apparatuses for uniform reduction of the in-feature wet etch rate of a silicon nitride film formed by ALD
US20200312653A1 (en) Methods And Precursors For Selective Deposition Of Metal Films
KR20210013775A (en) Tin-containing precursors and methods of depositing tin-containing films
TW202246560A (en) Method and system for forming boron nitride on a surface of a substrate
KR20180123436A (en) Methods for forming a silicon nitride film on a substrate and related semiconductor device structures

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant