CN112202531B

CN112202531B - Channel blind detection method and device, communication device and storage medium

Info

Publication number: CN112202531B
Application number: CN202011062227.0A
Authority: CN
Inventors: 任江涛; 邓敬贤; 胡剑锋; 张国松
Original assignee: Core Semiconductor Technology Beijing Co ltd
Current assignee: Core Semiconductor Technology Beijing Co ltd
Priority date: 2020-09-30
Filing date: 2020-09-30
Publication date: 2024-05-28
Anticipated expiration: 2040-09-30
Also published as: CN112202531A

Abstract

A channel blind detection method and apparatus, a communication apparatus and a storage medium are disclosed. The method comprises the steps of obtaining a first bit sequence corresponding to a subframe signal under the condition of the number of candidate antenna ports and a candidate subframe head index by receiving the subframe signal sent by a Physical Broadcast Channel (PBCH) in one subframe, determining the initial position of the first bit sequence according to a cyclic prefix type and the candidate subframe head index, performing rate de-matching on the first bit sequence according to the initial position to obtain a second bit sequence, decoding and checking the second bit sequence to obtain a checking result, and determining the number of candidate antenna ports and the candidate subframe head index corresponding to a third bit sequence with a correct checking result as the number of antenna ports and the subframe head index corresponding to the subframe signal. Therefore, the buffer memory and the calculation amount of the solution rate matching can be reduced, and the blind detection efficiency is improved.

Description

Channel blind detection method and device, communication device and storage medium

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method and apparatus for blind channel detection, and a communications device and storage medium.

Background

LTE (Long Term Evolution ) is a long term evolution of The UMTS (Universal Mobile Telecommunications System ) technical standard established by The 3GPP (The 3rd Generation Partnership Project, third generation partnership project) organization. The PBCH (physical broadcast channel ) of LTE is used to carry MIB (master information block ) of system broadcast information. After the transmitting end of the downlink control information determines the related data to be transmitted, the information after the processing such as CRC (Cyclic Redundancy Check, cyclic redundancy check code) check, channel coding, rate matching, winding, modulation, mapping preprocessing, resource mapping and the like are sequentially carried out on the MIB information, and the information after the processing is transmitted. If the receiving end needs to receive the MIB information, blind detection is needed to be carried out on the MIB information, namely, the position where the MIB information is located is searched in the calculated search space, the MIB information at the position is decoded, and the decoded MIB information is sequentially subjected to the treatments of de-resource mapping, de-rate matching, descrambling, de-channel coding, CRC (cyclic redundancy check) and the like, and if the CRC is correct, the blind detection is successful.

However, the blind detection method in the prior art needs to occupy a larger buffer memory, and the calculated amount is larger.

Disclosure of Invention

In view of the above, an object of the embodiments of the present invention is to provide a method and apparatus for blind detection of a channel, a communication device and a storage medium, which can reduce buffering and calculation amount of rate-de-matching and improve blind detection efficiency.

In a first aspect, an embodiment of the present invention provides a method for blind detection of a channel, where the method includes:

Receiving a subframe signal transmitted by a Physical Broadcast Channel (PBCH) in one subframe;

acquiring a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and the index of a candidate subframe head;

determining a starting position of the first bit sequence according to a cyclic prefix type and the candidate sub-period frame head index, wherein the cyclic prefix type comprises a conventional cyclic prefix and an extended cyclic prefix, and the cyclic prefix type is acquired during cell searching;

Performing de-rate matching on the first bit sequence according to the initial position to obtain a second bit sequence;

decoding the second bit sequence to obtain a corresponding third bit sequence;

checking the third bit sequence to obtain a checking result; and

And determining the number of candidate antenna ports and the candidate subframe head index corresponding to the third bit sequence with correct verification results as the number of antenna ports and the subframe head index corresponding to the subframe signal, wherein the subframe head index is used for representing the position of the subframe signal in the PBCH period.

Preferably, the number of candidate antenna ports includes 1,2 and 4, and the candidate sub-period frame header index includes 1,2,3 and 4.

Preferably, determining the start position of the first bit sequence according to the cyclic prefix type and the candidate sub-period frame header index includes:

in response to the cyclic prefix type being a normal cyclic prefix, starting positions of the first bit sequence are all 1 when the candidate sub-period frame head indexes are 1,2, 3, and 4.

In response to the cyclic prefix type being an extended cyclic prefix, and the candidate sub-period frame header index being 1, the starting position of the first bit sequence being 1;

in response to the cyclic prefix type being an extended cyclic prefix and the candidate sub-period frame header index being 2, the starting position of the first bit sequence is 117;

In response to the cyclic prefix type being an extended cyclic prefix and the candidate sub-period frame header index being 3, the starting position of the first bit sequence is 40; and

In response to the cyclic prefix type being an extended cyclic prefix and the candidate sub-period frame header index being 4, the starting position of the first bit sequence is 155.

Preferably, performing the de-rate matching on the first bit sequence according to the start position to obtain a second bit sequence includes:

sequentially adding the data in the second bit sequence to a plurality of data bits in a virtual circular buffer according to the starting position;

shunting the data in the virtual circular buffer; and

And performing sub-block de-interleaving on the shunted data to obtain the second bit sequence.

In a second aspect, an embodiment of the present invention provides a channel blind detection apparatus, where the apparatus includes:

A receiving unit, configured to receive a subframe signal transmitted by a physical broadcast channel PBCH in one subframe;

a first bit sequence obtaining unit, configured to obtain a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and the candidate subframe header index;

A starting position determining unit, configured to determine a starting position of the first bit sequence according to a cyclic prefix type and the candidate sub-period frame header index, where the cyclic prefix type includes a normal cyclic prefix and an extended cyclic prefix, and the cyclic prefix type is acquired during cell search;

A de-rate matching unit, configured to perform de-rate matching on the first bit sequence according to the starting position to obtain a second bit sequence;

A decoding unit, configured to perform decoding processing on the second bit sequence to obtain a corresponding third bit sequence;

The verification unit is used for verifying the third bit sequence to obtain a verification result; and

The position determining unit is configured to determine the number of candidate antenna ports and the candidate subframe header index corresponding to the third bit sequence with the correct verification result as the number of antenna ports and the subframe header index corresponding to the subframe signal, where the subframe header index is used to characterize the position of the subframe signal in the PBCH period.

In a third aspect, an embodiment of the present invention provides a communications apparatus, including a memory and a processor executing program instructions in the memory for implementing the method of the first aspect.

In a fourth aspect, an embodiment of the present invention provides a storage medium, where the storage medium is used to store a computer program, where the computer program is used to implement the method according to the first aspect.

According to the embodiment of the invention, a subframe signal transmitted by a Physical Broadcast Channel (PBCH) in one subframe is received, a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and the frame index of the candidate subframe is obtained, the starting position of the first bit sequence is determined according to the cyclic prefix type and the frame index of the candidate subframe, the first bit sequence is subjected to rate de-matching according to the starting position to obtain a second bit sequence, the second bit sequence is subjected to decoding and checking processing to obtain a checking result, and the number of candidate antenna ports and the frame index of the candidate subframe corresponding to a third bit sequence with correct checking result are determined as the number of antenna ports and the frame index of the subframe corresponding to the subframe signal. Therefore, the buffer memory and the calculation amount of the solution rate matching can be reduced, and the blind detection efficiency is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a communication system according to an embodiment of the present invention;

fig. 2 is a flowchart of data processing of a PBCH of a transmitting device according to an embodiment of the present invention;

fig. 3 is a schematic diagram of the number of antenna ports and the corresponding scrambling sequences according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a virtual circular buffer according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an inter-column permutation rule according to an embodiment of the present invention;

Fig. 6 is a block diagram of a channel time-frequency domain of a PBCH over one period according to an embodiment of the present invention;

fig. 7 is a flow chart of a prior art PBCH blind detection method;

FIG. 8 is a schematic diagram of a candidate sequence of the prior art;

Fig. 9 is a flow chart of a channel blind detection method according to an embodiment of the invention;

FIG. 10 is a flow chart of acquiring a first bit sequence according to an embodiment of the present invention;

FIG. 11 is a diagram illustrating a correspondence between a data length, a candidate sub-period frame header index, and a start position according to an embodiment of the present invention;

FIG. 12 is a flow chart of acquiring a third bit sequence according to an embodiment of the present invention;

Fig. 13 is a schematic structural diagram of a channel blind detection device according to an embodiment of the present invention;

fig. 14 is a schematic hardware configuration of a communication device according to an embodiment of the present invention.

Detailed Description

The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.

Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.

Unless the context clearly requires otherwise, the words "comprise," "comprising," and the like in the description are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".

In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

Fig. 1 is a schematic diagram of a communication system according to an embodiment of the present invention. As shown in fig. 1, the communication system of the embodiment of the present invention includes a transmitting apparatus 11 and a receiving apparatus 12.

In this embodiment, the transmitting device 11 is a network device, and the receiving device 12 is a terminal device.

Further, the transmitting apparatus 11 includes an encoder, so that the transmitting apparatus 11 can perform encoding and output the encoded sequence. The coded sequence is scrambled, modulated, layer mapped and precoded, RE mapped and baseband signal generated for transmission to the receiving device 12. The receiving device 12 includes a decoder, and the receiving device 12 can receive the signal transmitted by the transmitting device 101 and decode the received signal.

It should be understood that fig. 1 illustrates an architecture diagram of a communication system by way of example only and is not limiting of the architecture diagram of the communication system.

In the communication process, a transmitting end encodes information to obtain a bit sequence to be transmitted and transmits the bit sequence to be transmitted. The receiving end demodulates the received signal to obtain a set of Log Likelihood Ratios (LLRs), and the number of LLRs included in the set of LLRs is the same as the number of bits included in the bit sequence to be transmitted. The receiving end decodes according to the received set of LLRs. Wherein, whether the sender sends bit 1 or bit 0, the receiver may misjudge. For the signal r, the ratio of the probability p (r|b=0) of correctly judging 0 to the probability p (r|b=1) of correctly judging 1 at the receiving end is the likelihood ratio. For the convenience of calculation processing, the log-likelihood ratio is obtained by taking the natural logarithm, that is, llr=ln [ p (r|b=0)/p (r|b=1) ].

Further, the receiving device 12 includes, but is not limited to, a Mobile station (MobileStation, MS), a Mobile Terminal (MT), a Mobile phone (MT), a handset (handset), a portable device (portable equipment), etc., which may communicate with one or more core networks via a radio access network (RadioAccess Network, RAN). For example, the terminal device may be a mobile phone, a computer with a wireless communication function, or the like, and the terminal device may also be a portable, pocket-sized, hand-held, computer-built-in, or vehicle-mounted mobile apparatus or device.

Further, the transmitting device 11 may be an evolved base station (Evolutional NodeB, eNB or eNodeB) in the LTE system, or the network device may be a gNB or a transmission and reception point (transmission reception point, TRP), a micro base station, etc. in the 5G communication system, or the network device may be a relay station, an access point, a vehicle device, a wearable device, a network device in a public land mobile network (Public Land Mobile Network, PLMN) of future evolution, or a network in which other various technologies are converged, or a base station in other various evolved networks, etc.

Further, the embodiment of the invention decodes the data of the downlink channel of the LTE system.

Further, the embodiment of the invention decodes the downlink data of the PBCH of the LTE network.

Alternatively, the data processing flow of the PBCH of the transmitting device 11 may refer to fig. 2, including the steps of:

step S110, channel coding.

Further, the channel coding process of the PBCH includes the steps of:

step S111, CRC (Cyclic Redundancy Check ) check.

In this embodiment, CRC is a channel coding technique that generates a short fixed-bit check code based on a network packet, and is mainly used to detect or check errors that may occur after data transmission or storage.

Further, the MIB information bits carried by the PBCH are 24 bits in total, and mainly include a system bandwidth, PHICH (Physical Hybrid ARQ Indicator Channel, physical hybrid automatic repeat request indicator channel) configuration information, and a system frame number.

Dl-bandwidth: the system bandwidth comprises six bandwidths of 6, 15, 25, 50, 75 and 100, and the total bandwidth is 3 bits.

Phich-duration: the number of OFDM (Orthogonal Frequency Division Multiplexing ) symbols occupied by PDCCH (Physical Downlink Control Channel, physical downlink control channel) can be adaptively adjusted when the parameter is set to normal; when the parameter is set to extended, if the bandwidth is 6, the number of OFDM symbols occupied by the PDCCH may be 3 or 4, and for other system bandwidths, the number of symbols occupied by the PDCCH may be 3, which is 1bit in total.

Phich-Resource: the parameter is used to calculate the resources of the cell PHICH channel.

SystemFrameNumber: the system frame number is used for the receiving device to acquire the system clock, and the 40ms window receiving device of the PBCH can be determined through blind detection, and the total number is 8 bits.

Spark: reserved, temporarily unused, for a total of 10 bits.

And when in verification, the length of the CRC sequence is added to be 16 bits, so that the output after verification is 40bit data.

Further, after adding the check bits, the CRC sequence is scrambled with a specific antenna port number scrambling sequence according to the number of antenna ports configured by the base station, and the number of antenna ports and the corresponding scrambling sequence are shown in fig. 3 below. Wherein, < x _ant,0,x_ant,1,x_ant,2,…,x_ant,15 > is the added CRC-Mask sequence. The number of antenna ports of the transmitting end is 1, 2 or 4, when the number of antenna ports of the transmitting end is 1, the data in the CRC-Mask sequence is 0, when the number of antenna ports of the transmitting end is 2, the data in the CRC-Mask sequence is 1, and when the number of antenna ports of the transmitting end is 4, the CRC-Mask sequence is <0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1, >.

Step S112, TBCC coding.

In this embodiment, the coding principle of TBCC (Tail Biting CC, tail biting convolutional code) coding: when the encoder starts to work, special initialization is carried out, the last m bits of the input information bits are sequentially input into a register of the encoder, and when the encoding is finished, the ending state of the encoder is the same as the initial state. This coding method is called tail biting coding since no tail bits are present. The TBCC codes the control information and the broadcast channel, enhances the robustness, reduces the coding cost of tail bits, overcomes the problem of code rate loss, and is suitable for iterative decoding.

Further, after the information bits are input into the TBCC coding module and subjected to TBCC coding, the number of bits of the output information is 3 times of the number of bits of the input information. The input bits are denoted as a ₁,A₂,A₃,……,A_k, where k is the number of bits of the input information, the output information is d ₁₁,d₁₂,d₁₃,……d_1k, and d ₂₁,d₂₂,d₂₃,……d_2k, and d ₃₁,d₃₂,d₃₃,……d_3k.

Further, k=40.

In this embodiment, the code rate of tail-biting convolutional coding is 1/3. That is, the TBCC encoder has 40 bits of input information and 3×40 bits of output information.

Step S113, rate matching.

In this embodiment, output information of the TBCC encoding module is converted into data of a predetermined length through rate matching.

Further, 3×40 bits of data output by the TBCC encoding module are converted into data of a predetermined length through rate matching. Further, the data length of the rate matching output may be determined according to a CP (Cyclic Prefix) type. Specifically, the CP is formed by copying signals at the tail of the OFDM symbol to the head, and the types of CP are mainly two, namely a Normal (Normal) CP and an Extended (Extended) CP. The conventional cyclic prefix length is 4.7 mus and the extended cyclic prefix length is 16.67 mus. The cyclic prefix may be associated with other multipath component information to obtain complete information. In addition, the cyclic prefix can realize the pre-estimation of time and frequency synchronization.

Further, in the case of the normal CP, the data length of the rate-matched output is 1920 bits.

Further, in the case of extended CP, the data length of the rate-matched output is 1728 bits.

The rate matching is achieved by a virtual circular buffer, the structure of which can be seen in fig. 4, comprising three sub-block interleavers 41, 42 and 43, a bit collection unit 44 and a bit selection unit 45.

In the present embodiment, the data d ₁₁,d₁₂,d₁₃,……,d_1k obtained by the encoding in the step S112 is input to the sub-block interleaver 41, d ₂₁,d₂₂,d₂₃,……d_2k is input to the sub-block interleaver 42, and d ₃₁,d₃₂,d₃₃,……d_3k is input to the sub-block interleaver 43. Where k=40.

In the present embodiment, the workflow of the sub-block interleaver 41 includes the steps of:

Step S1131, determining the number of matrix columns.

In this embodiment, the matrix column number C is determined to be 32, and the serial numbers of each column are numbered 1,2,3, … …,32 from left to right.

Step S1132, determining the number of matrix rows.

In this embodiment, the sub-block interleaver acquires the number of matrix rows according to the determined number of matrix columns. Specifically, it can be obtained according to the following formula:

D≤(R*C)

Wherein D is the number of bits of the input information of the sub-block interleaver, R is the number of matrix rows, and C is the number of matrix columns.

Further, R is the smallest integer satisfying the above formula.

Further, it may be determined that d=k=40, c=32, and thus r=2.

Further, each row of the matrix is numbered 1,2 from top left to bottom.

Thus, a matrix of 2x 32 is obtained.

Step S1133, adding the input information to the matrix.

In this embodiment, the matrix of 2×32 has 64 data bits in total, and the number of input bits is 40, so 24 dummy bits need to be added to the header, and then the number of bits of input information is added to other positions of the matrix.

Specifically, from row 0 and column 0 of the matrix, 16 dummy bits are added first, and then 40bit data of input information is added to the matrix sequentially.

Step S1134, inter-column permutation.

In this embodiment, the matrix obtained above is subjected to inter-column permutation according to a predetermined rule. Specifically, the substitution rule is shown in fig. 5. Each column of the permuted matrix is designated P ₁,P₂,P₃,……,P₃₂ in sequence from left to right, and P ₁,P₂,P₃,……,P₃₂ is the column number 2, 18, 10, 26,6, 22, 14, 30,4, 20, 12, 28,8, 24, 16, 32,1, 17,9, 25,5, 21, 13, 29,3, 19, 11, 27,7, 23, 15, 31, respectively, before the permutation.

Thus, the sub-block interleaver 41 may obtain a first permutation matrix of 2 x 32.

Further, the sub-block interleavers 42 and 43 may obtain a second permutation matrix and a third permutation matrix of 2×32 according to the same procedure as described above.

In the present embodiment, the bit collection unit 44 performs data collection according to the above-described first permutation matrix, second permutation matrix, and third permutation matrix.

Specifically, a sequence of bits is read out of the first permutation matrix column by column in a left to right order, denoted v ₁₁,v₁₂,v₁₃,……,v_1m, where m=64. The bit sequence is read out from the second permutation matrix, denoted v ₂₁,v₂₂,v₂₃,……,v_2m, where m=64. The bit sequence is read out from the third permutation matrix, denoted v ₃₁,v₃₂,v₃₃,……,v_3m, where m=64. Let the i (i=1, 2,3, … …,191, 192) th data of the virtual circular buffer be w _i, then:

That is, the m bit sequences read out from the first permutation matrix are sequentially added to the 1 st to m th positions of the virtual circular buffer, the m bit sequences read out from the second permutation matrix are sequentially added to the m+1 st to 2*m th positions of the virtual circular buffer, and the m bit sequences read out from the third permutation matrix are sequentially added to the 2 x m+1 th to 3*m th positions of the virtual circular buffer, respectively.

Further, since m=64, the virtual circular buffers thus share 3*m =192 bit of data.

In the present embodiment, the bit selection unit 45 is configured to generate a bit sequence e of a predetermined length n.

Further, in the case of normal CP, the bit selection unit 45 is used to generate a sequence of n=1920 bits.

Further, in the case of extended CP, the bit selection unit 45 is configured to generate a sequence of n=1728bit.

Specifically, in the normal CP, the bit selection unit 45 selects one data from the virtual circular buffer in a predetermined order, determines whether the data is a dummy bit, adds the data to 1920 bits if the data is not a dummy bit, and skips the data to select the next data to continue processing until 1920 bits are filled if the data is a dummy bit. In the extended CP, the bit selection unit 45 selects one data from the virtual circular buffer in a predetermined order, judges whether the data is a dummy bit, if not, adds the data to 1728bit, and if so, skips the data to select the next data to continue processing until 1728bit is filled.

Further, according to the above principle, the virtual circular buffer shares 3×64 bits of data, and each 64 bits of data includes 40 bits of valid data, so each 40 bits is added, and the 64 bits of data in the virtual circular buffer need to be read. The calculation shows that:

At the normal CP, among 192bit data in the virtual circular buffer:

The first 480 bits, the start position k0 is 1;

the second 480bit, the start position k0 is 1;

the third 480bit, the starting position k0 is 1;

Fourth 480bit, start position k0 is 1.

In the extended CP, 192 bits of data in the virtual circular buffer:

The first 432 bits, the start position k0 is 1;

The second 432 bits, starting position k0 is 117;

The third 432bit, the starting position k0 is 40;

fourth 432 bits, start position k0 is 155.

Step S120, scrambling.

In this embodiment, scrambling is to multiply the spreading codes by a random code sequence, encrypt the signal, and downlink scrambling can be used to distinguish between cells and channels.

Further, the scrambling formula is as follows:

Wherein, For the scrambled h data, e (h) is the h data after rate matching, c (h) is the h data in the random sequence, h is more than or equal to 1 and less than or equal to 1920 (or more than or equal to 1 and less than or equal to 1728).

Specifically, since e (h) and c (h) are 0 or 1, scrambling is actually determined from c (h) in the random sequenceWhen c (h) is 0,/>When c (h) is 1,/>The 0/1 conversion is performed. Namely:

When e (h) =0, c (h) =0,

When e (h) =0, c (h) =1,

When e (h) =1, c (h) =0,

When e (h) =1, c (h) =1,

Step S130, QPSK modulation.

In this embodiment, NPDSCH adopts a QPSK (Quadrature PHASE SHIFT KEYING) modulation scheme. QPSK is a four-ary phase shift keying that uses four different phase differences of the carrier to characterize the input digital information. QPSK is a phase modulation technique at m=4, which specifies four carrier phases, 45 °,135 °,225 °,315 °, respectively, and the data input by the modulator is a binary digital sequence, which is converted into quaternary data in order to match the quaternary carrier phases.

Specifically, the above data obtained by scrambling are divided into 4 groups. That is, 1920 bits are divided into 4×480 bits in the normal CP, and 1728bi is divided into 4×432b bits in the extended CP.

For each set of 480/432 bits, every two bits in the binary digital sequence are grouped together in four combinations, i.e., 00, 01, 10, 11, where each set is referred to as a two-bit symbol. Each two-bit symbol is composed of two binary information bits, which represent one symbol (symbol) of four symbols, respectively. Each modulation in QPSK can transmit 2 information bits, which are conveyed by four phases of the carrier. The demodulator judges the information bit sent by the sending end according to the phase of the received carrier signal.

Step S140, layer mapping and precoding.

In this embodiment, since the number of codewords is different from the number of transmit antenna ports, it is necessary to map codewords onto different antenna ports. The layer number is indicated by RI (Rank Indication), rank is the Rank in the antenna matrix in the MIMO (multiple input multiple output ) scheme, i.e. the data streams that can be independently transmitted in parallel. RANK is the number of layers that the terminal tells the network side to support effectively. The PBCH performs the function of MIMO together by layer mapping and precoding. Firstly, codeword complex-valued modulation symbols to be transmitted are mapped into one or more layers through layer mapping, serial-parallel conversion is completed, the multiplexing rate of spatial multiplexing is controlled, and then, the data after layer mapping is precoded, namely, MIMO coding is realized. The precoding is used for matching the layer data to the antenna ports, reducing or controlling interference between the spatial multiplexing data streams, reducing complexity of receiver implementation, reducing system overhead, and improving performance of MIMO technology.

Step S150, RE mapping.

In this embodiment, RE (Resource Element) mapping maps the precoded output to allocated RB (Resource Block) resources through a random phase offset process, and the mapping process follows the principle of first frequency domain and then time domain, that is, all REs of one OFDM (Orthogonal Frequency Division Multiplexing ) symbol are filled first, and the next OFDM symbol is filled.

Step S160, baseband signal generation.

In this embodiment, the baseband signal is an original electrical signal sent by a source (transmitting end). Specifically, the method for generating the baseband signal may use various existing technologies, which are not described herein again

Thus, a transmission signal can be generated.

Specifically, fig. 6 may be referred to as a block diagram of a channel time-frequency domain of the PBCH over one period. As shown in fig. 6, one period of the PBCH is 40ms, divided into 4 sub-periods of 10ms each. Each sub-cycle transmits a 480/432bit segment of data, so 1920/1728 bits are transmitted exactly over 4 cycles. Meanwhile, the MIB signal is transmitted in 1ms of each sub-period (10 ms).

It should be understood that the above-mentioned PBCH signal processing is only one implementation manner of the embodiment of the present invention, and the embodiment of the present invention is not limited thereto, and may be implemented in various existing manners.

Further, in order to acquire MIB information, the receiving device 12 needs to perform blind detection on the MIB information, that is, search the calculated search space for the location where the MIB information is located, and decode the MIB information at the location.

Fig. 7 is a flow chart of a prior art PBCH blind detection method. As shown in fig. 7, the PBCH blind detection method of the prior art includes the steps of:

Step S210, obtaining soft bit LLR.

In this embodiment, the receiving device may obtain a frame header of 10ms of the received signal in the time domain, i.e. a certain 10ms start position in one 40ms period, through cell search. Soft bit LLRs for the received subframe signals are obtained.

Specifically, sampling is carried out at a preset rate, cyclic prefix is removed, baseband data on a first subframe is extracted, and complete MIB data and relevant pilot frequency data on a time domain are obtained; performing Fourier transform to generate frequency domain data of the subframe; performing blind detection on the number of antenna ports; performing de-resource mapping, and sequentially taking out complex-valued symbols from the positions of the resource grid; performing de-layer mapping and precoding according to the number of antenna ports; demodulation QPSK modulation, demodulating each complex value symbol into two bit data; thus, soft bit LLRs corresponding to the subframe signals when the number of antenna ports is 1, 2, and 4 are obtained.

Further, the obtained soft bit LLR is 480/432bit.

Step S220, descrambling.

In this embodiment, a random sequence of each sub-period when the sending device scrambles is obtained, and the obtained 480/432bit data is descrambled according to the random sequence.

Further, as can be seen from the above step S120, when scrambling is performed, the transmitting device may send each bit of data corresponding to one of the random sequences through one random sequence, so that each 480/432bit of transmitted data corresponds to one group of 480/432bit random sequences, and the received data is descrambled according to the random sequence when scrambling to recover the data before scrambling.

Further, according to the step S210, soft bit LLRs corresponding to the number of the antenna ports 1,2, and 4 of the subframe signals can be obtained. The method comprises the steps of obtaining random sequences of all sub-periods when a sending device scrambles, respectively descrambling obtained soft bit LLRs according to the random sequences of all the sub-periods to obtain descrambling sequences respectively corresponding to 4 sub-periods when the number of antenna ports is 1, descrambling sequences respectively corresponding to 4 sub-periods when the number of antenna ports is 2, and descrambling sequences respectively corresponding to 4 sub-periods when the number of antenna ports is 4. That is, the data of 480/432 bits of 3 x 4 groups is obtained after descrambling according to the number of antenna ports and the difference of subcycles.

Step S230, rate matching is achieved.

In this embodiment, the rate-de-matching is the inverse process of the above step S113, and specifically includes the following steps:

Step S231, determining candidate sequences.

In this embodiment, when the rates are matched, candidate sequences that need to be rate matched are determined.

Specifically, 3 x 12 groups of 480/432bit data are obtained through descrambling, and corresponding candidate sequences are determined according to the number of antenna ports and the subcycle corresponding to each group of 480/432bit data. And the obtained data is put into the sub-period, and the data in other sub-periods are filled with 0, so that a group of 1920/1728-bit data can be obtained, and when the number of antenna ports is 1, 4 cases are left, and 4 groups of 480/432-bit data are correspondingly obtained. When the number of antenna ports is 2, there are also 4 cases, and 4 sets of 480/432bit data are correspondingly obtained. When the number of antenna ports is 4, there are also 4 cases, and 4 sets of 480/432bit data are correspondingly obtained.

Fig. 8 shows a candidate sequence of the number of antenna ports, where X is the sub-period frame header index. Specifically, when x=i (i=1, 2,3, 4), the data in the i-th sub-period of the obtained 480/432bit data is filled with 0 in the other sub-periods.

It should be understood that fig. 8 only shows one candidate sequence of the number of antenna ports, and since there may be three cases of the number of antenna ports, there are 12 candidate sequences in total, each candidate sequence being 1920/1728 bits.

Step S232, rate matching is achieved.

In this embodiment, the receiving device acquires, through control information, the length D of the original sequence sent by the sending device, where the original sequence is a sequence obtained after the CRC check, that is, d=40 bits. Further, the virtual circular buffer is constructed according to the original sequence length, and the method specifically refers to fig. 4 and 5, and includes the following steps:

Step S2321, determining the number of matrix columns.

Step S2322, determining the number of matrix rows.

D≤(R*C)

Further, R is the smallest integer satisfying the above formula.

Further, d=40, c=32 can be determined, and thus, r=2 can be calculated.

Further, each row of the matrix is numbered 1,2 from top left to bottom.

Thus, a matrix of 2x 32 is obtained.

Step S2323, adding information to the matrix.

In this embodiment, the matrix of 2×32 has 64 data bits in total, and the number of bits of the original sequence is 40, so 24 dummy bits need to be added to the header, and then the effective information is added to other positions of the matrix.

Specifically, from row 0 and column 0 of the matrix, 24 dummy bits are added first, and then 40bit data is added to the matrix in sequence.

Step S2324, inter-column permutation.

Thus, the sub-block interleaver 41 may obtain a first permutation matrix of 32×2.

Further, the sub-block interleavers 42 and 43 may obtain a second permutation matrix and a third permutation matrix of 32×2 according to the same procedure as described above.

Specifically, a sequence of bits is read out of the first permutation matrix column by column in a left to right order, denoted v ₁₁,v₁₂,v₁₃,……,v_1m, where m=64. The bit sequence is read out from the second permutation matrix, denoted v ₂₁,v₂₂,v₂₃,……,v_2m, where m=64. The bit sequence is read out from the third permutation matrix, denoted v ₃₁,v₃₂,v₃₃,……,v_3m, where m=64. Let the i-th data of the virtual circular buffer be w _i, then:

Thus, a virtual circular buffer can be obtained.

Step S2325, adding the candidate sequence to the virtual circular buffer.

In this embodiment, the candidate sequence obtained above is added to the virtual circular buffer.

Further, 1920/1728bit data is added to 192 data bits in the virtual circular buffer for each candidate sequence.

Specifically, according to the above-described step of constructing the virtual circular buffer, it can be known that there are 120 valid bits and 72 virtual bit positions in 192 data bits. First, the first bit in the candidate sequence is selected, the first data bit in the virtual circular buffer is selected, whether the data bit is a valid bit is judged, if the data bit is a valid bit, the selected bit is filled into the data bit, if the data bit is not a valid bit, the next data bit in the virtual circular buffer is selected, and the judgment is continued. If the currently processed data bit is the last data bit in the 192 bits, the first data bit is returned at the next processing. The above steps are repeated until 1920/1728bit data are all added to 192 data bits.

Further, for each data bit, multiple bits of data are received, and the multiple bits of data are combined. Thereby, 192bit data can be obtained.

Step S2326, bit splitting.

In this embodiment, the obtained 192bit data is subjected to bit splitting to obtain 3×64bit data.

Specifically, 1-64 bits of data in 192 bits of data are fetched to generate a 64bit sequence, denoted as v ₁₁,v₁₂,v₁₃,……,v_1m, where m=64. The 65-128 bit data is fetched to generate a 64bit sequence denoted v ₂₁,v₂₂,v₂₃,……,v_2m, where m=64. The 129-192 bits of data are fetched to produce a 64bit sequence denoted v ₃₁,v₃₂,v₃₃,……,v_3m, where m=64. Thus, 3×64bit data can be obtained.

Step S2327, sub-block de-interleaving.

In this embodiment, for each 64bit data obtained above, it is added to a matrix of 2×32. The data of 3×40 bits can be obtained through the above procedure of step S2324 and the inverse procedure of step S2323.

Further, 3×40bit data of 12 candidate sequences can be obtained by the same method as described above.

Step S240, decoding.

In this embodiment, the above obtained 12 kinds of 3×40bit data are respectively subjected to TBCC decoding encoding to obtain 12 sets of 40bit data.

Further, the TBCC decoding may be performed by various methods, which are not limited herein.

Step S250, resolving CRC.

In this embodiment, the CRC is decoded on the 12 sets of 40bit data to obtain 12 check results.

Further, the number of antenna ports and the sub-period frame head index corresponding to the situation that the verification result is correct are obtained as decoding results.

However, in the prior art, the buffer memory and the calculation amount are relatively large in the rate de-matching process, and as described above, the buffer memory required to be occupied before the rate de-matching process is 12 x 1920bit (or 12 x 1728 bit), and the calculation amount is 12 x 1920bit (or 12 x 1728 bit).

Further, according to the rate matching process of the transmitting device, it is known that:

At the normal CP, among 192bit data in the virtual circular buffer:

The first 480 bits, the start position k0 is 1;

the second 480bit, the start position k0 is 1;

the third 480bit, the starting position k0 is 1;

Fourth 480bit, start position k0 is 1.

In the extended CP, 192 bits of data in the virtual circular buffer:

The first 432 bits, the start position k0 is 1;

The second 432 bits, starting position k0 is 117;

The third 432bit, the starting position k0 is 40;

fourth 432 bits, start position k0 is 155.

Therefore, the embodiment of the invention provides a channel blind detection method, which is used for reducing the buffer memory and the calculated amount of solution rate matching and improving the blind detection efficiency. As shown in fig. 9, the method comprises the following steps:

step S310, receiving a subframe signal sent by a physical broadcast channel PBCH in one subframe.

In this embodiment, the receiving device may obtain a frame header of 10ms of the received signal in the time domain, i.e. a certain 10ms start position in one 40ms period, through cell search. A subframe signal transmitted in one subframe of the physical broadcast channel PBCH is received.

Step S320, obtaining a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and the index of the candidate subframe header.

In this embodiment, the method for obtaining soft bit LLRs of a received subframe signal, as shown in fig. 10, includes the following steps:

and S321, extracting the sampled PBCH baseband data, and performing Fourier transform to obtain frequency domain data.

In this embodiment, sampling is performed at a predetermined frequency, cyclic prefix is removed, baseband data on a first subframe is extracted, and complete MIB data and related pilot data on a time domain are obtained. Fourier transform is performed to generate frequency domain data for the subframe.

Step S322, channel estimation is carried out to recover the signal of the transmitting end.

In this embodiment, blind detection is performed on the number of antenna ports, and the transmitting-end signal is recovered.

Step S323, performing de-resource mapping.

In this embodiment, MIB information is transmitted in a PBCH channel, and the PBCH channel data transmission period is 4 subcycles. Therefore, blind detection is needed for which sub-period of the PBCH period the frame is located in, so that the sub-period frame head index X sequentially takes values of 1 to 4, and the complex value symbol of MIB information.

Step S324, de-layer mapping and precoding.

Further, the de-layer mapping and precoding may be implemented by various methods existing.

Step S325, QPSK modulation is demodulated.

Further, the resulting complex-valued symbols are adjusted to a pair of bit data. Thus, soft bit LLRs can be obtained.

Thus, the data of the subframe signal under the number of candidate antenna ports and the index of the candidate subframe header can be obtained through the steps S321 to S325.

Further, since the number of candidate antenna ports includes 1,2 and 4, and the candidate sub-period frame header index includes 1,2, 3 and 4, 12 sets of soft bit LLRs are obtained in total, each set of soft bit LLRs being 480 bits or 432 bits.

Step S326, descrambling.

In this embodiment, for each set of 480/432bit data obtained as described above, the receiving device generates a random sequence of 4×480 bits or 4×432 bits, and selects which set of 480/432bit random sequences to descramble according to which sub-period the sub-frame signal is in the PBCH period assumed in step S323.

In this embodiment, when scrambling is performed, the transmitting device may perform descrambling on the received data according to the random sequence during scrambling by using a random sequence, where each bit of data transmitted corresponds to one data in the random sequence, and each sub-period corresponds to one scrambling sequence, so as to recover the data before scrambling by the transmitting device.

Further, for the mapping of the candidate sub-period frame header index x=i (i=1, 2,3, 4), descrambling is performed according to the random sequence of the i-th sub-period to obtain the corresponding first bit sequence.

Specifically, the descrambling formula is as follows:

y＝LLR*(1-2c)

wherein LLR is bit sequence obtained by demodulation, c is random sequence, and y is sequence after descrambling.

As can be seen from the above formula, when c=0, y=llr; when c=1, y= -LLR.

That is, if the random sequence is 0, the demodulated bit sequence is not changed; if the scrambling sequence is 1, the demodulated bit sequence is subjected to 0/1 conversion.

Thus, a first bit sequence corresponding to the number of candidate antenna ports and the candidate sub-period frame head index can be obtained.

Step S330, determining a start position (hereinafter referred to as start position k 0) of the first bit sequence according to the cyclic prefix type and the candidate sub-period frame header index.

In this embodiment, the cyclic prefix type includes a normal cyclic prefix and an extended cyclic prefix, and is acquired at the time of cell search.

Further, when the cyclic prefix type includes a normal CP, the data length of the first bit sequence is a first length.

Further, when the cyclic prefix type includes an extended CP, the data length of the first bit sequence is a second length.

Further, the first length is 480 bits and the second length is 432 bits.

Further, according to the transmission device rate matching process, it is known that:

At the normal CP, among 192bit data in the virtual circular buffer:

The first 480 bits, the start position k0 is 1;

the second 480bit, the start position k0 is 1;

the third 480bit, the starting position k0 is 1;

Fourth 480bit, start position k0 is 1.

In the extended CP, 192 bits of data in the virtual circular buffer:

The first 432 bits, the start position k0 is 1;

The second 432 bits, starting position k0 is 117;

The third 432bit, the starting position k0 is 40;

fourth 432 bits, start position k0 is 155.

Further, the relationship among the data length of the first bit sequence, the candidate sub-period frame header index, and the start position k0 of the first bit sequence in the virtual circular buffer is shown in fig. 11. Determining the starting position of the first bit sequence according to the cyclic prefix type and the candidate sub-period frame head index comprises:

In step S331, in response to the cyclic prefix type being a normal cyclic prefix, when the candidate sub-period frame head indexes are 1,2,3 and 4, the starting positions of the first bit sequences are all 1.

Step S332, in response to the cyclic prefix type being an extended cyclic prefix, and the candidate sub-period frame header index being 1, the start position of the first bit sequence being 1.

Step S333, in response to the cyclic prefix type being an extended cyclic prefix, and the candidate sub-period frame header index being 2, the starting position of the first bit sequence is 117.

Step S334, in response to the cyclic prefix type being an extended cyclic prefix, and the candidate sub-period frame header index being 3, the starting position of the first bit sequence is 40.

Step S335, in response to the cyclic prefix type being an extended cyclic prefix, and the candidate sub-period frame header index being 4, the starting position of the first bit sequence is 155.

Thus, the start position k0 can be determined.

Step S340, performing de-rate matching on the first bit sequence according to the starting position to obtain a second bit sequence.

In this embodiment, for each first bit sequence, the second bit sequence is obtained by performing rate de-matching according to the above determined start position. As shown in fig. 12, the method comprises the following steps:

step S341, adding the data in the second bit sequence to a plurality of data bits in the virtual circular buffer in sequence according to the start position.

In this embodiment, the transmitting device acquires a virtual circular buffer, and sequentially adds the data in the second bit sequence to a plurality of data bits in the virtual circular buffer. Specifically, the step of obtaining the virtual buffer may refer to step S232 described above, and will not be described herein.

Further, the determined starting position is k0, and the second bit sequence obtained above is filled from the k0 th data bit of 192 data bits in the virtual circular buffer.

Specifically, the first bit in the second bit sequence is selected, the kth 0 data bit in the virtual circular buffer is selected, whether the data bit is a valid bit is judged, if the data bit is a valid bit, the selected bit is filled into the data bit, and if the data bit is not a valid bit, the next data bit in the virtual circular buffer is selected, and the judgment is continued. If the currently processed data bit is the last data bit in 192, the first data bit is returned at the next processing. The above steps are repeated until 480/432bit data are all added to 192 data bits.

Further, for each data bit, if multiple bits of data are received, the multiple bits of data are combined. Thereby, 192bit data can be obtained.

Step S342, splitting the data in the virtual circular buffer.

Specifically, 1-64 bits of data in 192 bits of data are fetched to generate a set of 64bit sequences, denoted v11, v12, v13, … …, v1m, where m=64. The 65-128 bit data is fetched to generate a set of 64bit sequences denoted v21, v22, v23, … …, v2m, where m=64. The 129-192 bits of data are fetched to generate a set of 64bit sequences denoted v31, v32, v33, … …, v3m, where m=64. Thus, 3×64bit data can be obtained.

Step S343, performing sub-block de-interleaving on the split data to obtain the second bit sequence.

In this embodiment, the corresponding second bit sequence is obtained according to the obtained 3×64bit data through sub-block deinterleaving.

Further, for each set of 64bit data obtained as described above, it is added to the matrix of 2×32 column by column in a left to right order. And performing inter-column inverse substitution to obtain an original matrix through the inverse process of the step S1134, reading out data in the original matrix row by row from the 0 th row and the 0 th column of the matrix, and removing the first 24 virtual bits to generate 40bit data. Thus, for data of 3×64bit, the second bit sequence obtained by sub-block deinterleaving is 3×40bit.

Further, for the 3×4 kinds of 480/432 bits obtained after descrambling in the step S330, 3×4 groups of 3×40 bits are obtained after rate-de-matching.

In the embodiment of the invention, the descrambled data is directly subjected to rate de-matching, the buffer memory for rate de-matching is 12 x 3 x 40bit, and compared with the 12 x 1920bit (or 12 x 1728 bit) data buffered before rate de-matching in the prior art, the occupied buffer memory is 1/16 (or 5/72) of the prior art.

And step S350, decoding the second bit sequence to obtain a corresponding third bit sequence.

In this embodiment, decoding processing is performed on the obtained 12 groups of 3×40 bits to obtain a corresponding third bit sequence.

Further, the data of 3 x 40 bits of each group is subjected to decoding algorithm to obtain 40bit data before tail biting convolution coding with constraint length of 7 and code rate of 1/3, namely a third bit sequence. The idea of decoding is to find maximum likelihood decoding based on the received sequence. Initializing a state register, a state transition register and a path register, circulating each state after the initial state, calculating the hamming distance between the state and the two previous possible states, comparing and selecting a path with a smaller hamming distance until a path with the maximum probability value is found, and backtracking the path transition to generate decoding data.

And step S360, checking the third bit sequence to obtain a checking result.

In this embodiment, the above-obtained 12 sets of third bit sequences are checked respectively to obtain a check result.

Further, the 40-bit data of the third bit sequence contains 24-bit MIB data and 16-bit CRC check data, and the 16-bit check bits are scrambled by different scrambling sequences. Firstly, according to the number of the antenna ports assumed before, different scrambling codes are selected, and descrambling operation is carried out on CRC check bits. Specifically, for 4 cases where the number of the assumed antenna ports is 1, the scrambling sequence of all 0 in fig. 3 is selected for the descrambling process; for 4 cases where the number of assumed antenna ports is 2, the scrambling sequence of all 1 in fig. 3 is selected for the descrambling process, and for 4 cases where the number of assumed antenna ports is 4, the scrambling sequence of alternating 0 and 1 in fig. 3 is selected for the descrambling process. The descrambled 16-bit CRC data is then used to determine if the data was decoded correctly.

Step S370, determining the number of antenna ports corresponding to the subframe signals and the subframe head index according to the checking result.

In this embodiment, the number of candidate antenna ports and the candidate subframe header index corresponding to the third bit sequence with the correct verification result are determined as the number of antenna ports and the subframe header index corresponding to the subframe signal, where the subframe header index is used to characterize the position of the subframe signal in the PBCH period.

Thus, the number of frame heads of 10ms for which the received subframe signal is received can be determined.

Further, decoding the CRC from the third bit sequence with correct check result obtains MIB information (24 bits) sent by the sending device.

Further, as can be seen from the above steps, the embodiment of the present invention directly performs rate de-matching on the received 480/432bit data, and only needs to buffer the 12×3×40bit data outputted by the rate de-matching, where the calculated amount is 12×480bit (or 12×432). Compared with the buffer memory of 12 x 1920bit (or 12 x 1728 bit) required by the prior art, the calculated amount of 12 x 1920bit (or 12 x 1728 bit) is 1/16 (or 5/72) of the prior art, and the calculated amount is 1/4 of the prior art.

Fig. 13 is a schematic structural diagram of a channel blind detection device according to an embodiment of the present invention. As shown in fig. 13, the channel blind detection apparatus according to the embodiment of the present invention includes: a receiving unit 131, a first bit sequence acquiring unit 132, a starting position determining unit 133, a de-rate matching unit 134, a decoding unit 135, a checking unit 136, and a position determining unit 137. Wherein, the receiving unit 131 is configured to receive a subframe signal sent by the physical broadcast channel PBCH in one subframe. The first bit sequence obtaining unit 132 is configured to obtain a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and the candidate subframe header index. The starting position determining unit 133 is configured to determine a starting position of the first bit sequence according to a cyclic prefix type and the candidate sub-period frame header index, where the cyclic prefix type includes a normal cyclic prefix and an extended cyclic prefix, and the cyclic prefix type is acquired during cell search. The de-rate matching unit 134 is configured to perform de-rate matching on the first bit sequence according to the start position to obtain a second bit sequence. The decoding unit 135 is configured to perform decoding processing on the second bit sequence to obtain a corresponding third bit sequence. The checking unit 136 is configured to check the third bit sequence to obtain a check result. The position determining unit 137 is configured to determine the number of candidate antenna ports and the candidate subframe header index corresponding to the third bit sequence with the correct verification result as the number of antenna ports and the subframe header index corresponding to the subframe signal, where the subframe header index is used to characterize the position of the subframe signal in the PBCH period.

Further, the number of candidate antenna ports includes 1,2, and 4, and the candidate sub-period frame header index includes 1,2, 3, and 4.

Further, the start position determination unit 133 includes:

A first determining subunit, configured to respond to the cyclic prefix type being a normal cyclic prefix, where the starting positions of the first bit sequences when the candidate sub-period frame head indexes are 1,2, 3 and 4 are all 1.

Further, the start position determination unit 134 further includes:

A second determining subunit, configured to respond to the cyclic prefix type being an extended cyclic prefix, and the candidate sub-period frame header index being 1, where a start position of the first bit sequence is 1;

A third determining subunit, configured to respond to the cyclic prefix type being an extended cyclic prefix, and the candidate sub-period frame header index being 2, and the starting position of the first bit sequence being 117;

A fourth determining subunit, configured to respond to the cyclic prefix type being an extended cyclic prefix, and the candidate sub-period frame header index being 3, where a start position of the first bit sequence is 40; and

A fifth determining subunit, configured to respond to the cyclic prefix type being an extended cyclic prefix, and the candidate sub-period frame header index being 4, and the starting position of the first bit sequence being 155.

Further, performing a de-rate matching on the first bit sequence according to the start position to obtain a second bit sequence includes:

further, the rate de-matching unit 134 includes:

A data adding subunit, configured to sequentially add the data in the second bit sequence to a plurality of data bits in the virtual circular buffer according to the start position;

a splitting subunit, configured to split data in the virtual circular buffer; and

And the de-interleaving subunit is used for performing sub-block de-interleaving on the data after the splitting to obtain the second bit sequence.

Fig. 14 is a schematic hardware structure of a communication device according to an embodiment of the present invention. As shown in fig. 14, the communication apparatus includes: a memory 141 and a processor 142, wherein the memory 141 and the processor 142 are in communication; illustratively, the memory 141 and the processor 142 communicate via a communication bus 143, the memory 141 being adapted to store a computer program, the processor 142 executing the computer program to perform the methods shown in the above embodiments.

Optionally, the communication device may further comprise a transmitter and/or a receiver.

Alternatively, the Processor may be a central processing unit (Central Processing Unit, CPU), but may also be implemented as other general purpose Processor, PLC (Programmable Logic Controller ), FPGA (Field-Programmable GATE ARRAY, field Programmable gate array), DSP (DIGITAL SIGNAL Processor), or ASIC (Application SPECIFIC INTEGRATED Circuit). A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.

The embodiment of the invention provides a storage medium for storing a computer program for implementing the channel blind detection method according to any of the above method embodiments.

The embodiment of the invention provides a chip for supporting receiving equipment (such as terminal equipment, network equipment and the like) to realize the functions shown in the embodiment of the invention, and the chip is particularly used for a chip system, wherein the chip system can be formed by the chip, and can also comprise the chip and other discrete devices. When the above method is implemented as a chip in a receiving device, the chip may further comprise a processing unit, which may be, for example, a processor, and when the chip comprises a communication unit, which may be, for example, an input/output interface, pins or circuits, etc. The processing unit executes all or part of actions executed by each processing module in the embodiment of the present invention, and the communication unit may execute corresponding receiving or transmitting actions. In another specific embodiment, the processing module of the receiving device in the embodiment of the present invention may be a processing unit of a chip, and the receiving module or the transmitting module of the control device is a communication unit of the chip.

All or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a readable memory. The program, when executed, performs steps including the method embodiments described above; and the aforementioned memory (storage medium) includes: read-only memory (abbreviated as ROM), RAM, flash memory, hard disk, solid state disk, magnetic tape (English: MAGNETIC TAPE), floppy disk (English: floppydisk), optical disk (English: optical disk), and any combination thereof.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims and the equivalents thereof, the present invention is also intended to include such modifications and variations.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for blind detection of a channel, the method comprising:

decoding the second bit sequence to obtain a corresponding third bit sequence;

checking the third bit sequence to obtain a checking result; and

Determining the number of candidate antenna ports and the candidate sub-period frame head index corresponding to the third bit sequence with correct verification result as the number of antenna ports and the sub-period frame head index corresponding to the sub-frame signal, wherein the sub-period frame head index is used for representing the position of the sub-period of the sub-frame signal in the PBCH period;

Wherein determining the starting position of the first bit sequence according to the cyclic prefix type and the candidate sub-period frame header index comprises:

in response to the cyclic prefix type being a normal cyclic prefix, starting positions of the first bit sequence are all 1 when the candidate sub-period frame head indexes are 1,2, 3 and 4;

2. The method of claim 1, wherein the number of candidate antenna ports comprises 1,2, and 4, and wherein the candidate sub-period frame header index comprises 1,2, 3, and 4.

3. The method of claim 1, wherein de-rate matching the first bit sequence according to the starting position to obtain a second bit sequence comprises:

shunting the data in the virtual circular buffer; and

4. A channel blind detection apparatus, the apparatus comprising:

The position determining unit is used for determining the number of candidate antenna ports and the candidate subframe head index corresponding to the third bit sequence with correct verification results as the number of antenna ports and the subframe head index corresponding to the subframe signal, wherein the subframe head index is used for representing the position of the subframe signal in the PBCH period;

the start position determination unit 133 includes:

a first determining subunit, configured to respond to the cyclic prefix type being a normal cyclic prefix, where the starting positions of the first bit sequences when the candidate sub-period frame head indexes are 1, 2, 3 and 4 are all 1;

5. A communication device comprising a memory and a processor executing program instructions in the memory for implementing the method of any of claims 1-3.

6. A storage medium for storing a computer program for implementing the method of any one of claims 1-3.