CN112201617A - Copper electroplating filling process - Google Patents
Copper electroplating filling process Download PDFInfo
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- CN112201617A CN112201617A CN202011056561.5A CN202011056561A CN112201617A CN 112201617 A CN112201617 A CN 112201617A CN 202011056561 A CN202011056561 A CN 202011056561A CN 112201617 A CN112201617 A CN 112201617A
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 240
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 240
- 239000010949 copper Substances 0.000 title claims abstract description 240
- 238000009713 electroplating Methods 0.000 title claims abstract description 87
- 238000005429 filling process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 123
- 230000008569 process Effects 0.000 claims abstract description 104
- 239000013078 crystal Substances 0.000 claims abstract description 35
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000005751 Copper oxide Substances 0.000 claims abstract description 27
- 229910000431 copper oxide Inorganic materials 0.000 claims abstract description 27
- 238000011946 reduction process Methods 0.000 claims abstract description 16
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 238000010992 reflux Methods 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 161
- 239000011229 interlayer Substances 0.000 claims description 54
- 230000004888 barrier function Effects 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 238000005240 physical vapour deposition Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000003929 acidic solution Substances 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000243 solution Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 2
- 230000006872 improvement Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses an electro-coppering filling process method, which comprises the following steps: step one, forming an opening; step two, forming a copper seed crystal layer, and forming an overhang of the copper seed crystal layer at the top corner of the opening; step three, annealing reflux treatment is carried out, so that the overhang is reduced or eliminated; fourthly, the surface of the copper seed crystal layer is oxidized to form copper oxide in the waiting time from the formation of the copper seed crystal layer to the next copper electroplating process; and fifthly, adding a reduction process before the copper electroplating process, and then, filling the copper layer into the opening by the copper electroplating process. The invention can reduce or eliminate the overhang formed by the copper seed layer at the top corner of the opening by adding the annealing reflux treatment process, can eliminate the copper oxide on the surface of the copper seed layer in the copper electroplating process and keep the thickness of the copper seed layer at each position of the inner side surface of the opening by adding the reduction process before the copper electroplating process, and finally can reduce the difficulty of the copper electroplating filling process and increase the copper electroplating filling capacity.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for filling a copper plating.
Background
The Back End Of Line (BEOL) process usually adopts a copper interconnection process, and the copper interconnection process is usually realized by adopting a damascene process, i.e. an opening Of a dielectric layer is formed first, and then copper is electroplated in the opening, so that the patterning Of the copper interconnection is realized through the opening Of the dielectric layer without etching a copper layer. As shown in fig. 1A to 1C, the present invention is a device structure diagram in each step of the existing copper electroplating filling process method, and the existing copper electroplating filling process method includes the following steps:
step one, as shown in fig. 1A, an opening 102 is formed.
Typically, the opening 102 is a trench or a via opening. The opening 102 is formed in the interlayer film 101.
The openings 102 are formed using a lithographic definition plus etch process.
The etching process for forming the opening 102 is dry etching.
Step two, as shown in fig. 1B, a copper diffusion barrier layer 103 and a copper seed layer 104 are sequentially formed on the inner surface of the opening 102.
The copper diffusion barrier layer 103 and the copper seed layer 104 also extend onto the surface of the interlayer film 101 outside the area of the opening 102.
Typically, the copper seed layer 104 and the copper diffusion barrier layer 103 are formed using a Physical Vapor Deposition (PVD) process.
Step four, as shown in fig. 1C, there is a waiting time between the formation of the copper seed layer 104 and the next copper electroplating process, and within the waiting time, the surface of the copper seed layer 104 is oxidized to form copper oxide 105.
And step five, performing the copper electroplating process to fill the copper layer into the opening 102.
The filled copper layer also extends to the surface of the interlayer film 101 outside the opening 102, and after the fifth step, the method further comprises performing a copper chemical mechanical polishing process to remove the copper layer on the surface of the interlayer film 101 outside the opening 102 and polishing the surface of the copper layer in the area of the opening 102 to be equal to the surface of the interlayer film 101.
The copper electroplating filling process is a back-end process, the interlayer film 101 comprises a plurality of layers, the copper layer filled in the groove of the interlayer film 101 is used as a front metal connecting line, and a through hole is formed by copper filled in the through hole opening of the interlayer film 101.
The interlayer film 101 is made of an oxide layer or a dielectric layer having a dielectric constant lower than that of the oxide layer.
The interlayer film 101 at the bottommost layer is formed on the surface of a semiconductor substrate such as a silicon substrate, and the front metal connecting wire formed in the interlayer film 101 at the bottommost layer is connected with a doped region at the bottom, such as a source region or a drain region of a MOSFET and a polysilicon gate, through the through hole.
Each of the interlayer films 101 on the lowermost layer is formed on the interlayer film 101 of the previous layer on which the front metal wiring has been formed, respectively, and reference numeral 201 in fig. 1A corresponds to the front metal wiring of the interlayer film 101 of the previous layer.
As shown in fig. 1B, the step coverage of the copper seed layer 104 is generally poor, and an overhang protruding into the opening is formed at the top of the opening 102, as shown by the dashed circle corresponding to the mark 202. The overhang reduces the top width of the opening 102 after the copper seed layer 104 is formed, which increases the difficulty of the electro-coppering process. When the width of the opening 102 itself is large, the ratio of the width of the overhang to the width of the entire opening 102 is small, and the difficulty of the copper electroplating filling process is not significantly increased or is not revealed. As technology nodes continue to shrink, the ratio of the width of the overhang to the width of the entire opening 102 is large, which can have a significant impact on the difficulty of the copper electroplating filling process.
As shown in fig. 1C, it is understood that the copper electroplating process according to the conventional method is performed under the condition that the copper oxide 105 is formed on the surface of the copper seed layer 104, and a natural phenomenon occurs within the waiting time. In the presence of the copper oxide 105, the plating solution of the copper electroplating process, especially the acidic plating solution such as sulfuric acid, can rapidly dissolve the copper seed layer 104 having the copper oxide 105 formed thereon, for example, at the bottom corner of the opening 102 corresponding to the mark 203 in fig. 1C, the copper seed layer 104 itself has a small thickness, and a weak point (weak point) is generated after the copper seed layer is rapidly dissolved, which increases the difficulty of the copper electroplating filling process.
Disclosure of Invention
The invention aims to solve the technical problem of providing an electroplating copper filling process method which can reduce the electroplating copper filling difficulty and improve the electroplating copper filling capacity.
In order to solve the technical problem, the electro-coppering filling process method provided by the invention comprises the following steps:
step one, forming an opening pattern.
And step two, forming a copper seed crystal layer, wherein the copper seed crystal layer covers the inner side surface of the opening and extends to the surface outside the opening, and an overhang formed by the copper seed crystal layer protruding towards the inside of the opening is formed at the top corner of the opening.
And step three, carrying out annealing reflux treatment on the copper seed crystal layer to reduce or eliminate the overhang of the top corner of the opening so as to improve the filling capacity of the subsequent copper electroplating process.
And step four, waiting time is provided between the formation of the copper seed crystal layer and the next copper electroplating process, and the surface of the copper seed crystal layer is oxidized to form copper oxide within the waiting time range.
Step five, adding a reduction process before the electro-coppering process, and then filling the copper layer into the opening by the electro-coppering process; the reduction process reduces the copper oxide on the surface of the copper seed crystal layer into copper so as to eliminate the copper oxide on the surface of the copper seed crystal layer during the copper electroplating process and keep the thickness of the copper seed crystal layer at each position on the inner side surface of the opening.
In a further improvement, a step of forming a copper diffusion barrier layer is further included before forming the copper seed layer in the second step, the copper diffusion barrier layer is formed on the inner side surface of the opening, and the copper seed layer is formed on the surface of the copper diffusion barrier layer.
In a further improvement, the copper seed layer is formed by a physical vapor deposition process.
In a further improvement, the copper diffusion barrier layer is formed by a physical vapor deposition process.
In a further refinement, the material of the copper diffusion barrier layer comprises Ta or TaN.
The further improvement is that the reduction process in the fourth step adopts ammonia water treatment.
In a further improvement, the opening in the first step is a trench or a via opening.
In a further refinement, the opening is formed in the interlayer film in step one.
In a further improvement, in the second step, the copper seed layer further extends to the surface of the interlayer film outside the opening area.
The copper layer filled in the fifth step further extends to the surface of the interlayer film outside the opening, and after the fifth step, the method further comprises the steps of carrying out a chemical mechanical polishing process of copper to remove the copper layer on the surface of the interlayer film outside the opening and polishing the surface of the copper layer in the opening area to be equal to the surface of the interlayer film.
In a further improvement, the interlayer film comprises a plurality of layers, the copper layer filled in the groove of the interlayer film is used as a front metal connecting line, and the through hole is formed by copper filled in the through hole opening of the interlayer film.
The further improvement is that the copper electroplating process in the fifth step adopts an acid solution.
In a further improvement, the acidic solution used in the electrolytic copper plating process comprises sulfuric acid.
The further improvement is that the interlayer film is made of an oxide layer or a dielectric layer with a dielectric constant lower than that of the oxide layer.
The further improvement is that the bottom layer interlayer film is formed on the surface of the semiconductor substrate, and the front metal connecting line formed in the bottom layer interlayer film is connected with the doped region at the bottom through the through hole.
And the interlayer films on the bottommost layer are respectively formed on the interlayer film of the previous layer on which the front metal connecting wire is formed.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the openings are applied in the process of 22nm, 20nm and below 16nm technology nodes.
The annealing reflux treatment process for the copper seed crystal layer is carried out after the copper seed crystal layer is formed and before the subsequent copper electroplating process, and the annealing reflux treatment process can reduce or eliminate the overhang formed by the copper seed crystal layer at the vertex angle of the opening, so that the width of the top of the opening after the copper seed crystal layer is formed can be increased, namely the depth-to-width ratio of the opening before the copper electroplating process can be reduced, thereby reducing the filling difficulty of the copper electroplating process and improving the filling capacity. The invention is particularly suitable for being applied to smaller technical nodes such as technical nodes below 22nm, 20nm and 16nm, because the width of an opening such as a groove or a through hole for filling copper is smaller and smaller along with the continuous equal proportional reduction of the size of a device, the ratio of the size of an overhang formed at the top of the opening to the width of the whole opening is larger due to the poorer step coverage of the copper seed crystal layer, so that the depth-width ratio of the opening after the copper seed crystal layer is formed is increased, which can generate larger influence on the filling difficulty of the copper electroplating process, and after the annealing reflux treatment of the invention, the technical problem of the large filling difficulty of the copper electroplating process caused by the poor step coverage of the copper seed crystal layer and the smaller width of the opening of the smaller technical node can be well solved; meanwhile, the process is simple and easy to realize, and has unexpected technical effects.
In addition, the invention can reduce the copper oxide on the surface of the copper seed layer into copper by adding a reduction process before the copper electroplating process after the copper seed layer is formed, and can eliminate the situation that the copper oxide is on the surface of the copper seed layer in the copper electroplating process, namely, the copper oxide on the surface of the copper seed layer is eliminated before the copper electroplating process is started, and simultaneously, the thickness of the copper seed layer on each position of the inner side surface of the opening can be maintained, so that the filling difficulty of the copper electroplating can be reduced, for example, the situation that the copper seed layer with the copper oxide on the surface is quickly dissolved by electroplating liquid such as sulfuric acid in the copper electroplating process can be prevented, and the filling quality of the copper electroplating can also be improved.
In addition, the reduction process can keep the thickness of the copper seed crystal layer while removing the copper oxide, so that the Q-Time between the formation of the copper seed crystal layer and the next copper electroplating process can be increased, namely, the Q-Time window of the process can be increased.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1C are device structure diagrams at various steps of a conventional electro-coppering process;
FIG. 2 is a flow chart of an electro-coppering process method according to an embodiment of the present invention;
fig. 3A-3E are device structure diagrams at various steps of an electroplated copper fill process method in accordance with an embodiment of the present invention.
Detailed Description
FIG. 2 is a flow chart of an exemplary method of the copper electroplating fill process; as shown in fig. 3A to fig. 3E, which are device structure diagrams in each step of the filling process method of copper electroplating according to the embodiment of the present invention, the filling process method of copper electroplating according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, an opening 102 pattern is formed.
Preferably, the opening 102 is formed in the interlayer film 101. In other embodiments, the opening 102 can also be formed directly in a semiconductor substrate, such as a silicon substrate.
The openings 102 are formed using a lithographic definition plus etch process.
The etching process for forming the opening 102 is dry etching.
The opening 102 is a trench or a via opening.
The openings 102 are used in the process for 22nm, 20nm and sub-16 nm technology nodes.
Step two, as shown in fig. 3B, forming a copper seed layer 104, where the copper seed layer 104 covers the inner side surface of the opening 102 and extends to the surface outside the opening 102, and an overhang formed by protruding the copper seed layer 104 into the opening 102 is formed at the top corner of the opening 102, and the overhang is shown as a dashed circle corresponding to the mark 202.
Preferably, the step of forming the copper seed layer 104 further comprises forming a copper diffusion barrier layer 103 before forming the copper seed layer 104, wherein the copper diffusion barrier layer 103 is formed on the inner side surface of the opening 102, and the copper seed layer 104 is formed on the surface of the copper diffusion barrier layer 103.
The copper diffusion barrier layer 103 and the copper seed layer 104 also extend onto the surface of the interlayer film 101 outside the area of the opening 102.
The copper seed layer 104 is formed by a physical vapor deposition process.
The copper diffusion barrier layer 103 is formed by a physical vapor deposition process. The material of the copper diffusion barrier layer 103 includes Ta or TaN.
And thirdly, as shown in fig. 3C, performing annealing reflow treatment on the copper seed layer 104 to reduce or eliminate the overhang at the top corner of the opening 102, so as to improve the filling capability of the subsequent copper electroplating process. As shown in fig. 3C, the anneal reflow process not only reduces or eliminates the overhang, but also increases the thickness of the copper seed layer 104 at the bottom corner of the opening 102.
Step four, as shown in fig. 3D, there is a waiting time between the formation of the copper seed layer 104 and the next copper electroplating process, and within the waiting time, the surface of the copper seed layer 104 is oxidized to form copper oxide 105.
Preferably, the reduction process adopts ammonia water treatment.
Step five, as shown in fig. 3E, a reduction process is added before the copper electroplating process, and then the copper electroplating process is performed to fill the copper layer into the opening 102; the reduction process reduces the copper oxide 105 on the surface of the copper seed layer 104 to copper, so as to eliminate the copper oxide 105 on the surface of the copper seed layer 104 during the copper electroplating process and maintain the thickness of the copper seed layer 104 at various positions on the inner surface of the opening 102.
As shown in fig. 1C and fig. 3D, in the embodiment of the invention, after the annealing reflow process of step three is added, the thickness of the copper seed layer 104 at the bottom corner of the opening 102 is increased, so that after the copper oxide 105 is formed in step four, the thickness of the copper seed layer 104 remaining at the bottom corner of the opening 102 is increased, and therefore, the annealing reflow process can also improve the bottom corner structure of the opening 102, i.e., the annealing reflow process can improve the bottom corner structure of the opening 102 together with the reduction process.
The copper electroplating process adopts an acidic solution. The acidic solution adopted by the copper electroplating process comprises sulfuric acid. When the copper electroplating process uses an acidic solution as the electroplating solution, when the copper seed layer 104 has the copper oxide 105 on the surface, the copper seed layer 104 is easily dissolved rapidly, which increases the difficulty of electroplating.
Preferably, the filled copper layer further extends to the surface of the interlayer film 101 outside the opening 102, and after the fifth step, the method further comprises performing a copper chemical mechanical polishing process to remove the copper layer on the surface of the interlayer film 101 outside the opening 102 and polishing the surface of the copper layer in the area of the opening 102 to be even with the surface of the interlayer film 101.
In the method of the embodiment of the invention, the copper electroplating filling process is a back-end process. The interlayer film 101 includes a plurality of layers, the copper layer filled in the groove of the interlayer film 101 serves as a front metal connection line, and the via hole is composed of copper filled in a via opening of the interlayer film 101.
The interlayer film 101 is made of an oxide layer or a dielectric layer having a dielectric constant lower than that of the oxide layer.
The interlayer film 101 at the bottommost layer is formed on the surface of a semiconductor substrate such as a silicon substrate, and the front metal connecting wire formed in the interlayer film 101 at the bottommost layer is connected with a doped region at the bottom, such as a source region or a drain region of a MOSFET and a polysilicon gate, through the through hole.
Each of the interlayer films 101 on the lowermost layer is formed on the interlayer film 101 of the previous layer on which the front metal wiring has been formed, respectively, and reference numeral 201 in fig. 3A corresponds to the front metal wiring of the interlayer film 101 of the previous layer.
In the embodiment of the invention, the annealing reflux treatment process for the copper seed layer 104 is carried out after the copper seed layer 104 is formed and before the subsequent copper electroplating process, and the annealing reflux treatment process can reduce or eliminate the overhang formed by the copper seed layer 104 at the top corner of the opening 102, so that the top width of the opening 102 after the copper seed layer 104 is formed can be increased, namely the depth-to-width ratio of the opening 102 before the copper electroplating process can be reduced, thereby reducing the filling difficulty of the copper electroplating process and improving the filling capacity. The embodiment of the invention is particularly suitable for being applied to smaller technical nodes such as technical nodes below 22nm, 20nm and 16nm, because the width of the opening 102 such as the opening 102 of a trench or a through hole for filling copper is smaller and smaller as the size of the device is continuously reduced in equal proportion, the proportion of the size of an overhang formed at the top of the opening 102 in the width of the whole opening 102 is larger due to the poorer step coverage capability of the copper seed layer 104, so that the aspect ratio of the opening 102 after the copper seed layer 104 is formed is increased, which can greatly influence the filling difficulty of the copper electroplating process, and after the annealing reflow treatment of the embodiment of the invention, the technical problem of the large filling difficulty of the copper electroplating process caused by the poor step coverage capability of the copper seed layer 104 and the smaller width of the opening 102 of the smaller technical node can be well solved; meanwhile, the annealing reflow process of the embodiment of the invention can also increase the thickness of the copper seed layer 104 at the bottom corner of the opening 102, and the process is simple and easy to implement, thereby having unexpected technical effects.
In addition, the embodiment of the invention adds a reduction process before the copper electroplating process after the copper seed layer 104 is formed, so that the copper oxide 105 on the surface of the copper seed layer 104 can be reduced into copper, and the situation that the copper oxide 105 is on the surface of the copper seed layer 104 in the copper electroplating process can be eliminated, namely the copper oxide 105 on the surface of the copper seed layer 104 is eliminated before the copper electroplating process is started, and the thickness of the copper seed layer 104 on each position of the inner side surface of the opening 102 can be kept, so that the filling difficulty of the copper electroplating can be reduced, for example, the situation that the copper seed layer 104 with the copper oxide 105 on the surface is quickly dissolved by electroplating liquid such as sulfuric acid in the copper electroplating process can be prevented, and the filling quality of the copper electroplating can also be improved.
In addition, since the reduction process of the embodiment of the invention can maintain the thickness of the copper seed layer 104 while removing the copper oxide 105, the Q-Time between the copper electroplating process and the next step after the copper seed layer 104 is formed can be increased, i.e., the Q-Time window of the process can be increased.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (16)
1. The copper electroplating filling process method is characterized by comprising the following steps:
step one, forming an opening pattern;
forming a copper seed crystal layer, wherein the copper seed crystal layer covers the inner side surface of the opening and extends to the surface outside the opening, and an overhang formed by the copper seed crystal layer protruding towards the inside of the opening is formed at the top corner of the opening;
thirdly, carrying out annealing reflux treatment on the copper seed crystal layer to reduce or eliminate the overhang of the opening vertex angle so as to improve the filling capacity of the subsequent copper electroplating process;
step four, waiting time is provided between the formation of the copper seed crystal layer and the next copper electroplating process, and the surface of the copper seed crystal layer is oxidized to form copper oxide within the waiting time range;
step five, adding a reduction process before the electro-coppering process, and then filling the copper layer into the opening by the electro-coppering process; the reduction process reduces the copper oxide on the surface of the copper seed crystal layer into copper so as to eliminate the copper oxide on the surface of the copper seed crystal layer during the copper electroplating process and keep the thickness of the copper seed crystal layer at each position on the inner side surface of the opening.
2. The copper electroplating fill process as claimed in claim 1, wherein: and a step of forming a copper diffusion barrier layer before forming the copper seed crystal layer in the second step, wherein the copper diffusion barrier layer is formed on the inner side surface of the opening, and the copper seed crystal layer is formed on the surface of the copper diffusion barrier layer.
3. The copper electroplating fill process as claimed in claim 1, wherein: and forming the copper seed crystal layer by adopting a physical vapor deposition process method.
4. The copper electroplating fill process as claimed in claim 2, wherein: and forming the copper diffusion barrier layer by adopting a physical vapor deposition process.
5. The copper electroplating fill process as claimed in claim 2, wherein: the material of the copper diffusion barrier layer comprises Ta or TaN.
6. The copper electroplating fill process as claimed in claim 1, wherein: and the reduction process in the fourth step adopts ammonia water treatment.
7. The copper electroplating fill process as claimed in claim 1, wherein: the opening in the first step is a groove or a through hole opening.
8. The copper electroplating fill process as claimed in claim 7, wherein: the opening is formed in the interlayer film in the first step.
9. The copper electroplating fill process as recited in claim 8, wherein: in the second step, the copper seed crystal layer also extends to the surface of the interlayer film outside the opening region;
the copper layer filled in the fifth step further extends to the surface of the interlayer film outside the opening, and after the fifth step, the method further comprises the steps of carrying out a chemical mechanical polishing process of copper to remove the copper layer on the surface of the interlayer film outside the opening and polishing the surface of the copper layer in the opening area to be equal to the surface of the interlayer film.
10. The copper electroplating fill process as recited in claim 9, wherein: the interlayer film comprises a plurality of layers, the copper layer filled in the groove of the interlayer film is used as a front metal connecting line, and a through hole is formed by copper filled in the through hole opening of the interlayer film.
11. The copper electroplating fill process as claimed in claim 1, wherein: and fifthly, adopting an acid solution for the copper electroplating process.
12. The copper electroplating fill process as recited in claim 11, wherein: the acidic solution adopted by the copper electroplating process comprises sulfuric acid.
13. The copper electroplating fill process as recited in claim 10, wherein: the interlayer film is made of an oxide layer or a dielectric layer with a dielectric constant lower than that of the oxide layer.
14. The copper electroplating fill process as recited in claim 10, wherein: the bottom interlayer film is formed on the surface of the semiconductor substrate, and the front metal connecting line formed in the bottom interlayer film is connected with the doped region at the bottom through the through hole;
and the interlayer films on the bottommost layer are respectively formed on the interlayer film of the previous layer on which the front metal connecting wire is formed.
15. The copper electroplating fill process as claimed in claim 1, wherein: the semiconductor substrate is a silicon substrate.
16. The copper electroplating fill process as claimed in claim 7, wherein: the opening is applied to the technology of technology nodes of 22nm, 20nm and below 16 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011056561.5A CN112201617A (en) | 2020-09-30 | 2020-09-30 | Copper electroplating filling process |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103295958A (en) * | 2013-06-04 | 2013-09-11 | 上海华力微电子有限公司 | Method for producing copper seed layers |
| CN103346121A (en) * | 2013-07-22 | 2013-10-09 | 华进半导体封装先导技术研发中心有限公司 | Method for manufacturing TSV seed layer with fine pitch and high depth-to-width ratio |
| CN110473828A (en) * | 2019-08-22 | 2019-11-19 | 上海华力集成电路制造有限公司 | Electro-coppering fill process method |
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- 2020-09-30 CN CN202011056561.5A patent/CN112201617A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103295958A (en) * | 2013-06-04 | 2013-09-11 | 上海华力微电子有限公司 | Method for producing copper seed layers |
| CN103346121A (en) * | 2013-07-22 | 2013-10-09 | 华进半导体封装先导技术研发中心有限公司 | Method for manufacturing TSV seed layer with fine pitch and high depth-to-width ratio |
| CN110473828A (en) * | 2019-08-22 | 2019-11-19 | 上海华力集成电路制造有限公司 | Electro-coppering fill process method |
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