CN112201289A

CN112201289A - Word line modulation circuit

Info

Publication number: CN112201289A
Application number: CN202011117126.9A
Authority: CN
Inventors: 张世钊
Original assignee: Shanghai Zhaoxin Integrated Circuit Co Ltd
Current assignee: Shanghai Zhaoxin Integrated Circuit Co Ltd
Priority date: 2020-10-19
Filing date: 2020-10-19
Publication date: 2021-01-08

Abstract

The invention provides a word line modulation circuit. The word line modulation circuit comprises at least one inverter, a power switch circuit, at least one first capacitor and at least one second capacitor. The inverter is coupled to a word line and an inverted word line for receiving an inverted word line signal and generating a word line signal, and coupled to a first capacitor via the word line. The power switch circuit is coupled to the inverter and is used for receiving a power switch control signal. The second capacitor is coupled to an internal node of the inverter and the power switch circuit and is used for receiving a boost signal.

Description

Word line modulation circuit

Technical Field

Embodiments of the present invention generally relate to a Word Line modulation circuit technology, and more particularly, to a Word Line modulation circuit technology for implementing a Charge Sharing (CS) -Word Line Under-Driving (WLUD) mechanism and a Capacitive Coupling (CC) -Word Line Over-Driving (WLOD) mechanism by using a Word Line modulation circuit.

Background

The use of read-write assist techniques is an important means to increase the yield of memory devices in advanced processes. Taking Static Random Access Memory (SRAM) as an example, Access Disturb Margin (ADM) can be raised by using the read assist technique to reduce the probability of read corruption, and Write Margin (WM) can be raised by using the write assist technique to reduce the probability of write failure.

Among the various assist techniques, word line modulation is a common approach. The Word Line modulation may include Word-Line Under-Driving (WLUD) and Word-Line Over-Driving (WLOD), the principle of which is to control the Driving capability of pass-gate transistors in the bit cells (or referred to as "bit cells") of the memory device.

However, the conventional use of upper word line inhibit driving (WLUD) and the use of Word Line Overdrive (WLOD) require separate configuration of a dc voltage dividing circuit on a chip or an addition of an external power supply. Therefore, the area and power consumption of the memory device will increase.

Disclosure of Invention

In view of the above-mentioned problems of the prior art, embodiments of the present invention provide a wordline modulation circuit, a method of a charge sharing-wordline inhibit driving scheme, and a method of a capacitive coupling-wordline overdrive scheme.

According to one embodiment of the present invention, a word line modulation circuit is provided. The word line modulation circuit comprises at least one inverter, a power switch circuit, at least one first capacitor and at least one second capacitor. The inverter is coupled to a word line and an inverted word line for receiving an inverted word line signal and generating a word line signal, and coupled to a first capacitor via the word line. The power switch circuit is coupled to the inverter and is used for receiving a power switch control signal. The second capacitor is coupled to an internal node of the inverter and the power switch circuit and is used for receiving a boost signal.

According to an embodiment of the present invention, the inverter includes a first P-transistor and a first N-transistor, wherein a gate of the first P-transistor is coupled to a gate of the first N-transistor, and the gate of the first P-transistor and the gate of the first N-transistor are coupled to the inverted word line for receiving the inverted word line signal.

According to an embodiment of the present invention, the drain of the first P-transistor is coupled to the drain of the first N-transistor, and the drain of the first P-transistor and the drain of the first N-transistor are coupled to the word line to generate the word line signal, wherein the word line is coupled to one end of the first capacitor, and the other end of the first capacitor is coupled to a ground node.

According to an embodiment of the present invention, a first source of the first P-transistor is coupled to the power switch circuit and the second capacitor at the internal node, and a second source of the first N-transistor is coupled to a ground node.

According to an embodiment of the present invention, the power switch circuit includes at least one second P-type transistor.

According to an embodiment of the present invention, a gate of the second P-transistor receives the power switch control signal, a drain of the second P-transistor is coupled to the inverter and the second capacitor at the internal node, and a source of the second P-transistor is coupled to a power node.

According to an embodiment of the present invention, one end of the second capacitor is coupled to the inverter and the power switch circuit at an internal node, and the other end of the second capacitor receives the boost signal.

According to one embodiment of the present invention, a method for a charge sharing-wordline inhibit driving scheme is provided. The method of the charge sharing-wordline inhibit driving scheme can be applied to an auxiliary read operation of a wordline modulation circuit. The method for the charge sharing-wordline inhibit driving scheme comprises the following steps: turning off a first P-transistor of an inverter of the word line modulation circuit and turning on a second P-transistor of a power switch circuit of the word line modulation circuit; precharging a voltage of an internal node to a power voltage, wherein the inverter is coupled to a first capacitor through a word line, and the inverter and the power switch circuit are coupled to a second capacitor at the internal node; increasing a voltage of a power switch control signal to turn off the second P-transistor of the power switch circuit; lowering an inverted wordline voltage of an inverted wordline signal to turn on the first P-transistor P1 of the inverter; transferring the charges of the internal nodes to the word lines; and determining whether a voltage of the power switch control signal is decreased earlier than a voltage of the inverted word line signal when the read operation is completed. When the voltage of the power switch control signal is decreased earlier than the time when the inverted word line voltage of the inverted word line signal is increased, the word line voltage of a word line signal is temporarily increased to the power voltage, and the word line voltage of the word line signal starts to be discharged to 0 after the inverted word line voltage of the inverted word line signal starts to be increased. When the time when the inverted word line voltage of the inverted word line signal rises is earlier than the time when the power switch control signal voltage falls, the word line voltage of the word line signal starts to discharge to 0 after the inverted word line voltage of the inverted word line signal starts to rise.

A method for a capacitively coupled-wordline overdrive scheme is provided according to an embodiment of the invention. The capacitive coupling-word line overdrive scheme is applied to the auxiliary write operation of a word line modulation circuit. The method of the capacitive coupling-word line overdrive mechanism comprises the following steps: turning off a first P-transistor of an inverter of the word line modulation circuit and turning on a second P-transistor of a power switch circuit of the word line modulation circuit; reducing an inverted word line voltage of an inverted word line signal to turn on the first P-type transistor of the inverter, and pre-charging a word line voltage of a word line signal on a word line to a power supply voltage; increasing the voltage of the power switch control signal to turn off the second P-transistor of the power switch circuit; increasing a voltage rise of a boost signal to inject charge into an internal node, wherein the inverter is coupled to a first capacitor via the word line, and the inverter and the power switch circuit are coupled to a second capacitor at the internal node; transferring charge on the internal node to the word line; and determining whether a voltage of the power switch control signal is decreased earlier than a voltage of the inverted word line signal when the write operation is completed. When the voltage of the power switch control signal is decreased earlier than the time when the inverted word line voltage of the inverted word line signal is increased, the word line voltage of the word line signal is temporarily decreased to the power supply voltage, and the word line voltage of the word line signal starts to be discharged to 0 after the inverted word line voltage of the inverted word line signal starts to be increased. When the voltage of the inverted word line signal rises earlier than the voltage of the power switch control signal, the word line voltage of the word line signal starts to discharge to 0

Other additional features and advantages of the present invention will be apparent to those skilled in the art from the following description, wherein modifications and variations can be made in the methods for wordline modulation, charge sharing-wordline inhibit driving, and capacitive coupling-wordline overdrive disclosed in the present application without departing from the spirit and scope of the invention.

Drawings

Fig. 1 is a block diagram illustrating a word line modulation circuit 100 according to an embodiment of the invention.

Fig. 2A-2E are waveform diagrams illustrating a driving scheme using charge sharing-wordline inhibit according to an embodiment of the invention.

Fig. 3A-3E are waveform diagrams illustrating a driving scheme using charge sharing-wordline inhibit according to another embodiment of the present invention.

FIGS. 4A-4E are waveform diagrams illustrating a scheme for using capacitive coupling-word line overdrive according to an embodiment of the present invention.

FIGS. 5A-5E are waveform diagrams illustrating a scheme for using capacitive coupling-word line overdrive according to another embodiment of the present invention.

Fig. 6A-6E are waveform diagrams illustrating a combination charge sharing-wordline inhibit drive scheme and capacitive coupling-wordline overdrive scheme according to an embodiment of the invention.

Fig. 7 is a flowchart of a method of a charge sharing-wordline inhibit driving scheme according to an embodiment of the invention.

FIG. 8 is a flow chart of a method of a capacitive coupled-wordline overdrive scheme in accordance with an embodiment of the present invention.

[ notation ] to show

100: word line modulation circuit

110: inverter with a capacitor having a capacitor element

120: power switch circuit

130: first capacitor

140: second capacitor

BST: boost signal

N1: a first N-type transistor

P1: a first P-type transistor

P2: second P-type transistor

PG: power switch control signal

VDDPG: internal node

VDD: power supply node

VSS: ground node

WLB: inverted word line signal

WL: word line signal

S710 to S780, S810 to S880: step (ii) of

Detailed Description

The preferred embodiments of the present invention are described in this section for illustrative purposes only and are not intended to limit the scope of the invention, which is defined by the following claims.

Fig. 1 is a block diagram illustrating a word line modulation circuit 100 according to an embodiment of the invention. The word line modulation circuit 100 can be applied to a memory device, such as: a Static Random Access Memory (SRAM), but the invention is not limited thereto. As shown in fig. 1, the word line modulation circuit 100 may include an inverter 110, a power switch circuit 120, a first capacitor 130, and a second capacitor 140. Note that the block diagram shown in fig. 1 is only for convenience of describing the embodiment of the present invention, but the present invention is not limited to fig. 1. Other elements may also be included in the word line modulation circuit 100. In addition, the word line modulation circuit 100 shown in fig. 1 includes an inverter, a first capacitor, a second capacitor, and a power switch circuit, but the invention is not limited thereto. According to an embodiment of the present invention, the word line modulation circuit 100 may also include a plurality of inverters, a plurality of first capacitors, a plurality of power switch circuits, and a plurality of second capacitors, wherein each inverter corresponds to one of the first capacitors and one of the second capacitors. In addition, according to an embodiment of the present invention, the power switch circuit 120 may be configured to couple to a plurality of inverters simultaneously to control the plurality of inverters.

As shown in fig. 1, the inverter 110 may include a first P-Transistor (e.g., a Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET)) P1 and a first N-Transistor (e.g., an NMOSFET) N1. the gate of the first P-Transistor P1 may be coupled to the gate of the first N-Transistor N1, the gate of the first P-Transistor P1 and the gate of the first N-Transistor N1 may be coupled to an inverting word line to receive the inverting word line signal wlb. the drain of the first P-Transistor P1 may be coupled to the drain of the first N-Transistor N1, and the drain of the first P-Transistor P1 and the drain of the first N-Transistor N1 may be coupled to a word line, to generate a word line signal WL. The source of the first P-type transistor P1 may be coupled to the power switch circuit 120 and the second capacitor 140 at an internal node VDDPG. The source of the first N-type transistor N1 may be coupled to a ground node VSS.

In addition, as shown in fig. 1, the power switch circuit 120 may include a second P-type transistor P2. The gate of the second P-type transistor P2 may receive a power switch control signal PG. The source of the second P-type transistor P2 may be coupled to a power node VDD to receive a power voltage V_DD. The drain of the second P-transistor P2 is coupled to the inverter 110 (the source of the first P-transistor P1) and the second capacitor 140 at the internal node VDDPG. According to another embodiment of the present invention, the power switch circuit 120 may also include a plurality of second P-type transistors.

In addition, as shown in fig. 1, one end of the first capacitor 130 may be coupled to the word line, and the other end of the first capacitor 130 may be coupled to the ground node VSS. One terminal of the second capacitor 140 may be coupled to the inverter 110 (the source of the first P-transistor P1) and the power switch circuit 120 (the drain of the second P-transistor P2) at the internal node VDDPG, and the other terminal of the second capacitor 140 may receive the boost signal BST.

According to an embodiment of the present invention, the Word Line modulation circuit 100 can be used to perform a Charge Sharing (CS) -Word Line Under-Driving (WLUD) mechanism to assist the memory device in performing a read operation when the memory device is performing the read operation. The operation of which will be described in detail below.

In an initial state, the second P-transistor P2 of the power switch circuit 120 is turned on, and the first P-transistor P1 of the inverter 110 is turned off. In addition, the voltage of the internal node VDDPG is precharged to the power supply voltage V_DDAnd the inverter 110 maintains the word line voltage of the word line signal WL at 0. When the voltage of the power switch control signal PG rises, the second P-transistor P2 of the power switch circuit 120 is turned off. Since the first P-type transistor P1 of the inverter 110 is still turned off when the power switch control signal PG starts to rise, the voltage of the internal node VDDPG is maintained at the power voltage V_DD. When the inverted word line voltage of the inverted word line signal WLB starts to drop, the first P-type transistor P1 of the inverter 110 is turned on. Due to the charge sharing effect, when the first P-transistor of the inverter 110 is turned on, the charge of the internal node VDDPG is transferred to the word line. In addition, since the first N-transistor N1 of the inverter 110 is turned off when the first P-transistor P1 of the inverter 110 is turned on, charges are maintained on the word line and the internal node VDDPG. At this time, the voltage of the word line signal WL is determined by the following equation:

wherein V_WLA word line voltage C representing a word line signal WL_CSIndicates the capacitance value, C, of the second capacitor 140_WLRepresents the capacitance value of the first capacitor 130, and V_DDRepresenting the supply voltage. When the read operation is finished, the voltage of the power switch control signal PG starts to decrease, and the inverted word line voltage of the inverted word line signal WLB starts to increase. When the voltage of the power switch control signal PG is decreasedWhen the time is earlier than the rise time of the inverted word line voltage of the inverted word line signal WLB, the word line voltage of the word line signal WL temporarily rises to the power supply voltage V first_DDAfter the inverted word line voltage of the inverted word line signal WLB starts to rise, the word line voltage of the word line signal WL starts to discharge to 0. The word line voltage of the word line signal WL temporarily rises to the power supply voltage V first_DDMay depend on the delay time between the power switch control signal PG and the inverted word line signal WLB. Further, in this case (the time at which the voltage of the power switch control signal PG falls is earlier than the time at which the inverted word line voltage of the inverted word line signal WLB rises), the time at which the charge sharing-word line restraining driving mechanism proceeds depends on the time from the time point at which the inverted word line voltage of the inverted word line signal WLB falls to the time point at which the power switch control signal PG falls. When the voltage of the inverted word line signal WLB rises earlier than the voltage of the power switch control signal PG falls, the word line voltage of the word line signal WL starts to discharge to 0 after the voltage of the inverted word line signal WLB starts to rise. Further, in this case (the time at which the inverted word line voltage of the inverted word line signal WLB rises is earlier than the time at which the voltage of the power switch control signal PG falls), the time at which the charge sharing-word line restraining driving mechanism is performed depends on the time from the time point at which the inverted word line voltage of the inverted word line signal WLB falls to the time point at which the inverted word line voltage of the inverted word line signal WLB rises. In addition, in this embodiment, the voltage of the boost signal BST maintains a constant value. FIGS. 2A-2E and 3A-3E will be described below.

Fig. 2A-2E are waveform diagrams illustrating a driving scheme using charge sharing-wordline inhibit according to an embodiment of the invention. Fig. 2A is a waveform diagram of the corresponding power switch control signal PG. Fig. 2B is a waveform diagram of the corresponding inverted word line signal WLB. Fig. 2C is a waveform diagram of the corresponding boost signal BST. Fig. 2D is a waveform diagram of the voltage corresponding to the internal node VDDPG. Fig. 2E is a waveform diagram of the corresponding word line signal WL. Furthermore, in FIGS. 2A-2E, the supply voltage V_DDAssume 1 volt (V). As shown in FIGS. 2A-2E, when the voltage of the power switch control signal PG rises to the power voltage V_DDAfter a later period of time, the reactionThe inverted word line voltage of the phase word line signal WLB starts to fall. The charge of the internal node VDDPG starts to be transferred to the word line (i.e., the word line voltage of the word line signal WL starts to rise, and the rising voltage is determined by the above formula). In addition, as can be seen from FIG. 2E, under the action of the charge sharing-word line inhibit driving mechanism, the word line voltage of the word line signal WL is smaller than the power voltage V_DD. When the read operation is finished, the voltage of the power switch control signal PG starts to decrease, and the inverted word line voltage of the inverted word line signal WLB starts to increase. In this embodiment, since the voltage of the power switch control signal PG is decreased earlier than the inverse word line voltage of the inverse word line signal WLB, the word line voltage of the word line signal WL temporarily increases to the power voltage V first_DD. After the inverted word line voltage of the inverted word line signal WLB starts to rise, the word line voltage of the word line signal WL starts to discharge to 0.

Fig. 3A-3E are waveform diagrams illustrating a driving scheme using charge sharing-wordline inhibit according to another embodiment of the present invention. Fig. 3A is a waveform diagram of the corresponding power switch control signal PG. Fig. 3B is a waveform diagram of the corresponding inverted word line signal WLB. Fig. 3C is a waveform diagram of the corresponding boost signal BST. Fig. 3D is a waveform diagram of the voltage corresponding to the internal node VDDPG. Fig. 3E is a waveform diagram of the corresponding word line signal WL. Furthermore, in FIGS. 3A-3E, the supply voltage V_DDAssume 1 volt (V). As shown in FIGS. 3A-3E, when the voltage of the power switch control signal PG rises to the power voltage V_DDAt a later time, the inverted word line voltage of the inverted word line signal WLB starts to fall. The charge of the internal node VDDPG starts to be transferred to the word line (i.e., the word line voltage of the word line signal WL starts to rise, and the rising voltage is determined by the above formula). In addition, as can be seen from FIG. 3E, under the action of the charge sharing-word line inhibit driving mechanism, the word line voltage of the word line signal WL is smaller than the power voltage V_DD. When the read operation is finished, the voltage of the power switch control signal PG starts to decrease, and the inverted word line voltage of the inverted word line signal WLB starts to increase. In this embodiment, the inverted word line voltage rises earlier than the power switch control signal PG due to the inverted word line signal WLBThe voltage of the word line signal WL starts to discharge to 0 after the inverted word line voltage of the inverted word line signal WLB starts to rise. That is, before the word line voltage of the word line signal WL starts to discharge to 0, the word line voltage of the word line signal WL is subjected to the charge sharing-word line inhibit driving mechanism (i.e. the word line voltage of the word line signal WL is smaller than the power supply voltage V)_DD)。

According to an embodiment of the present invention, the Word Line modulation circuit 100 may be used to perform a Capacitive Coupling (CC) -Word Line Over-Driving (WLOD) mechanism to assist the memory device in performing a write operation when the memory device is performing the write operation. The operation of which will be described in detail below.

In an initial state, the second P-transistor P2 of the power switch circuit 120 is turned on, and the first P-transistor P1 of the inverter 110 is turned off. In addition, when the inverted word line voltage of the inverted word line signal WLB starts to fall, the first P-type transistor P1 of the inverter 110 is turned on to pre-charge the word line voltage of the word line signal WL to the power supply voltage V in advance_DD. When the inverted word line voltage of the inverted word line signal WLB starts to fall, the second P-type transistor P2 of the power switch circuit 120 is still in a conductive state. When the voltage of the power switch control signal PG starts to rise, the second P-type transistor P2 of the power switch circuit 120 is turned off. Then, the voltage of the boost signal BST rises. Due to the capacitive coupling effect, when the voltage of the boost signal BST rises, charge is injected into the internal node VDDPG. In addition, due to the charge sharing effect, the charge on the internal node VDDPG is also transferred to the word line. In addition, since the first N-transistor N1 of the inverter 110 is turned off when the first P-transistor P1 of the inverter 110 is turned on, charges are maintained on the word line and the internal node VDDPG. At this time, the voltage of the word line signal WL is determined by the following equation:

wherein V_WLA word line voltage C representing a word line signal WL_CSIndicates the capacitance value, C, of the second capacitor 140_WLRepresents the capacitance value of the first capacitor 130, and V_DDRepresenting the supply voltage. When the write operation is finished, the voltage of the power switch control signal PG starts to decrease, and the inverted word line voltage of the inverted word line signal WLB starts to increase. When the voltage of the power switch control signal PG is decreased earlier than the inverse word line voltage WLB, the word line voltage of the word line signal WL is temporarily decreased to the power supply voltage V_DDAfter the inverted word line voltage of the inverted word line signal WLB starts to rise, the word line voltage of the word line signal WL starts to discharge to 0. The word line voltage of the word line signal WL temporarily drops to the power supply voltage V first_DDMay depend on the delay time between the power switch control signal PG and the inverted word line signal WLB. Further, in this case (the time at which the voltage of the power switch control signal PG falls is earlier than the time at which the inverted word line voltage of the inverted word line signal WLB rises), the time at which the capacitive coupling-word line overdrive scheme is performed depends on the time from the time point at which the boost signal BST rises to the time point at which the voltage of the power switch control signal PG falls. When the voltage of the inverted word line signal WLB rises earlier than the voltage of the power switch control signal PG falls, the word line voltage of the word line signal WL starts to discharge to 0 after the voltage of the inverted word line signal WLB starts to rise. Further, in this case (the time at which the inverted word line voltage of the inverted word line signal WLB rises is earlier than the time at which the voltage of the power switch control signal PG falls), the time at which the capacitive coupling-word line overdrive scheme is performed depends on the time from the time point at which the boost signal BST rises to the time point at which the inverted word line voltage of the inverted word line signal WLB rises. In addition, when the voltage of the power switch control signal PG starts to decrease, the voltage of the internal node VDDPG starts to decrease. Fig. 4A to 4E and fig. 5A to 5E will be described below.

Fig. 4A-4E are waveform diagrams illustrating a driving scheme using capacitive coupling-wordline inhibit according to an embodiment of the invention. FIG. 4A is a waveform of the corresponding power switch control signal PGFigure (a). Fig. 4B is a waveform diagram of the corresponding inverted word line signal WLB. Fig. 4C is a waveform diagram of the corresponding boost signal BST. Fig. 4D is a waveform diagram of the voltage corresponding to the internal node VDDPG. Fig. 4E is a waveform diagram of the corresponding word line signal WL. Further, in FIGS. 4A-4E, the supply voltage V_DDAssume 1 volt (V). As shown in FIGS. 4A-4E, when the inverted word line voltage of the inverted word line signal WLB begins to fall, the word line voltage of the word line signal WL begins to rise to the power supply voltage V_DDAnd the voltage of the internal node VDDPG will drop first and then return to the power voltage V_DD. When the word line voltage of the word line signal WL rises to the power supply voltage V_DDThen, the voltage of the power switch control signal PG rises to the power supply voltage V_DD. Then, the voltage of the boost signal BST rises. Due to the capacitive coupling effect, when the voltage of the boost signal BST rises, charge is injected into the internal node VDDPG, so that the voltage of the internal node VDDPG is shifted from the power voltage V_DDAnd starts to rise. In addition, due to the charge sharing effect, the charges on the internal node VDDPG are also transferred to the word line, so that the word line voltage of the word line signal WL starts to be shifted from the power voltage V_DDRising (the voltage of the word line signal WL at which the word line voltage rises is determined by the above equation). As can be seen from FIG. 4E, under the action of the capacitive coupling-word line over-driving mechanism, the word line voltage of the word line signal WL is greater than the power voltage V_DD. When the write operation is finished, the voltage of the power switch control signal PG starts to decrease, and the inverted word line voltage of the inverted word line signal WLB starts to increase. In this embodiment, since the time when the inverted word line voltage of the inverted word line signal WLB rises is earlier than the time when the voltage of the power switch control signal PG falls, the word line voltage of the word line signal WL starts to discharge to 0 after the inverted word line voltage of the inverted word line signal WLB starts to rise. That is, before the word line voltage of the word line signal WL starts to discharge to 0, the word line voltage of the word line signal WL is subjected to the capacitive coupling-word line overdrive mechanism (i.e. the word line voltage of the word line signal WL is greater than the power supply voltage V)_DD). In addition, in this embodiment, when the voltage of the boost signal BST decreases, the voltage of the internal node VDDPG will be driven from the power voltage V first_DDDrops and returns to the power supply voltage VDD.

Fig. 5A-5E are waveform diagrams illustrating a driving scheme using charge sharing-wordline inhibit according to another embodiment of the present invention. Fig. 5A is a waveform diagram of the corresponding power switch control signal PG. Fig. 5B is a waveform diagram of the corresponding inverted word line signal WLB. Fig. 5C is a waveform diagram of the corresponding boost signal BST. Fig. 5D is a waveform diagram of the voltage corresponding to the internal node VDDPG. Fig. 5E is a waveform diagram of the corresponding word line signal WL. Further, in FIGS. 5A-5E, the supply voltage V_DDAssume 1 volt (V). As shown in FIGS. 5A-5E, when the inverted word line voltage of the inverted word line signal WLB begins to fall, the word line voltage of the word line signal WL begins to rise to the power supply voltage V_DDAnd the voltage of the internal node VDDPG will drop first and then return to the power voltage V_DD. When the word line voltage of the word line signal WL rises to the power supply voltage V_DDThen, the voltage of the power switch control signal PG rises to the power supply voltage V_DD. Then, the voltage of the boost signal BST rises. Due to the capacitive coupling effect, when the voltage of the boost signal BST rises, charges are injected into the internal node VDDPG, so that the voltage of the internal node VDDPG rises from the power supply voltage VDD. In addition, due to the charge sharing effect, the charges on the internal node VDDPG are also transferred to the word line, so that the word line voltage of the word line signal WL starts to be shifted from the power voltage V_DDRising (the voltage of the word line signal WL at which the word line voltage rises is determined by the above equation). As can be seen from FIG. 5E, under the action of the capacitive coupling-word line over-driving mechanism, the word line voltage of the word line signal WL is greater than the power voltage V_DD. When the write operation is finished, the voltage of the power switch control signal PG starts to decrease, and the inverted word line voltage of the inverted word line signal WLB starts to increase. In this embodiment, since the voltage of the power switch control signal PG is decreased earlier than the voltage of the inverted word line signal WLB, the word line voltage of the word line signal WL is temporarily decreased to the power voltage V first_DD. After the inverted word line voltage of the inverted word line signal WLB starts to rise, the word line voltage of the word line signal WL starts to discharge to 0. In addition, the implementation is hereIn one example, when the voltage of the boost signal BST decreases, the voltage of the internal node VDDPG will be driven from the power voltage V_DDFalls and returns to the power supply voltage V_DD。

According to an embodiment of the present invention, when the memory device is performing a read/write operation (i.e., generating two pulses of the power switch control signal within one word line signal WL pulse), the word line modulation circuit 100 may alternatively use the charge sharing-word line suppression driving scheme and the capacitive coupling-word line overdrive scheme to assist the read/write operation performed by the memory device. The operation of which will be described in detail below.

First, in an initial state, the second P-transistor P2 of the power switch circuit 120 is turned on, and the first P-transistor P1 of the inverter 110 is turned off. In addition, the voltage of the internal node VDDPG is precharged to the power supply voltage V_DDAnd the inverter 110 maintains the word line voltage of the word line signal WL at 0. When the voltage of the power switch control signal PG rises, the second P-transistor P2 of the power switch circuit 120 is turned off. When the inverted word line voltage of the inverted word line signal WLB starts to drop, the first P-type transistor P1 of the inverter 110 is turned on. Due to the charge sharing effect, when the first P-transistor of the inverter 110 is turned on, the charges on the internal node VDDPG are transferred to the word line, so as to implement the charge sharing-word line suppression driving mechanism. When the voltage of the power switch control signal PG begins to drop, the second P-transistor P2 of the power switch circuit 120 is turned on, so that the voltage of the internal node VDDPG and the word line voltage of the word line signal WL are restored to the power voltage V_DD(i.e., when the charge sharing-wordline inhibit drive scheme ends). Then, the voltage of the power switch control signal PG rises again, and the second P-type transistor P2 of the power switch circuit 120 is turned off. Then, the voltage of the boost signal BST rises. Due to the capacitive coupling effect, when the voltage of the boost signal BST rises, charge is injected into the internal node VDDPG, so that the voltage of the internal node VDDPG rises to be higher than the power supply voltage V_DD. In addition, due to the charge sharing effect, the charge on the internal node VDDPG is also transferred to the word line, so that the word of the word line signal WL is generatedThe line voltage will rise above the supply voltage V_DDTo implement a capacitive coupled-word line overdrive scheme. In this embodiment, the operations of the charge sharing-wordline inhibit driving scheme and the capacitive coupling-wordline overdrive scheme are similar to those described in the above embodiments, and thus are not described again. This embodiment will be described below with reference to fig. 6A-6E.

Fig. 6A-6E are waveform diagrams illustrating a combined shared-wordline inhibit drive scheme and capacitive coupled-wordline overdrive scheme according to another embodiment of the present invention. Fig. 6A is a waveform diagram of the corresponding power switch control signal PG. Fig. 6B is a waveform diagram of the corresponding inverted word line signal WLB. Fig. 6C is a waveform diagram of the corresponding boost signal BST. Fig. 6D is a waveform diagram of the voltage corresponding to the internal node VDDPG. Fig. 6E is a waveform diagram of the corresponding word line signal WL. Further, in FIGS. 6A-6E, the supply voltage V_DDAssume 1 volt (V). As shown in fig. 6A-6E, the operation in the first half of the waveform corresponds to the charge sharing-wordline inhibit driving scheme, and the operation in the second half of the waveform corresponds to the capacitive coupling-wordline overdrive scheme. In this embodiment, the operations of the charge sharing-wordline inhibit driving scheme and the capacitive coupling-wordline overdrive scheme are similar to those described above with respect to the embodiments of FIGS. 2A-2E, 3A-3E, 4A-4E, and 5A-5E, and thus will not be described again.

It is noted that the waveform diagrams shown in FIGS. 2A-2E, 3A-3E, 4A-4E, 5A-5E and 6A-6E are only used to illustrate the embodiments of the present invention, but the present invention is not limited thereto. In addition, the power switch control signal PG and the boost signal BST according to the embodiment of the invention can be provided by an external control device (not shown).

Fig. 7 is a flowchart of a method of a charge sharing-wordline inhibit driving scheme according to an embodiment of the invention. The method of charge sharing-wordline inhibit driving scheme described in this embodiment can be applied to the wordline modulation circuit 100 to assist a read operation. As shown in fig. 7, in step S710, the second P-type transistor P2 of the power switch circuit 120 of the word line modulation circuit 100 is turned on, and the first P-type transistor P1 of the inverter 110 of the word line modulation circuit 100 is turned off.

In step S720, the voltage of the internal node VDDPG is precharged to the power supply voltage V_DD. The inverter 110 is coupled to a first capacitor 130 via a word line, and the inverter 110 and the power switch circuit 120 are coupled to a second capacitor 140 at the internal node VDDPG.

In step S730, the voltage of the power switch control signal PG rises to turn off the second P-type transistor P2 of the power switch circuit 120.

In step S740, the inverted word line voltage of the inverted word line signal WLB drops to turn on the first P-type transistor P1 of the inverter 110.

In step S750, the charge of the internal node VDDPG is transferred to the word line.

In step S760, after the read operation is finished, it is determined whether the voltage of the power switch control signal PG is decreased earlier than the voltage of the inverted word line signal WLB.

When the voltage of the power switch control signal PG falls earlier than the time when the inverted word line voltage of the inverted word line signal WLB rises, step S770 is performed. In step S770, the word line voltage of the word line signal WL temporarily rises to the power voltage V first_DDAfter the inverted word line voltage of the inverted word line signal WLB starts to rise, the word line voltage of the word line signal WL starts to discharge to 0.

When the time at which the inverted word line voltage of the inverted word line signal WLB rises is earlier than the time at which the voltage of the power switch control signal PG falls, step S780 is performed. In step S780, after the inverted word line voltage of the inverted word line signal WLB starts to rise, the word line voltage of the word line signal WL starts to discharge to 0.

FIG. 8 is a flow chart of a method of a capacitive coupled-wordline overdrive scheme in accordance with an embodiment of the present invention. The method of capacitive coupling-word line overdrive scheme described in this embodiment can be applied to the case where the word line modulation circuit 100 assists a write operation. As shown in fig. 8, in step S810, the second P-type transistor P2 of the power switch circuit 120 of the word line modulation circuit 100 is turned on, and the first P-type transistor P1 of the inverter 110 of the word line modulation circuit 100 is turned off.

In step S820, the inverted word line voltage of the inverted word line signal WLB is dropped to turn on the first P-type transistor P1 of the inverter 110, and the word line voltage of the word line signal WL on a word line is pre-charged to the power supply voltage V in advance_DD。

In step S830, the voltage of the power switch control signal PG rises to turn off the second P-type transistor P2 of the power switch circuit 120.

In step S840, the voltage of the boost signal BST rises to inject charges into the internal node VDDPG. The inverter 110 is coupled to a first capacitor 130 via a word line, and the inverter 110 and the power switch circuit 120 are coupled to a second capacitor 140 at the internal node VDDPG.

In step S850, the charge on the internal node VDDPG is transferred to the word line.

In step S860, after the write operation is finished, it is determined whether the voltage of the power switch control signal PG falls earlier than the voltage of the inverted word line signal WLB rises.

When the voltage of the power switch control signal PG falls earlier than the time when the inverted word line voltage of the inverted word line signal WLB rises, step S870 is performed. In step S870, the word line voltage of the word line signal WL is temporarily decreased to the power voltage V_DDAfter the inverted word line voltage of the inverted word line signal WLB starts to rise, the word line voltage of the word line signal WL starts to discharge to 0.

When the time when the inverted word line voltage of the inverted word line signal WLB rises is earlier than the time when the voltage of the power switch control signal PG falls, step S880 is performed. In step S880, the word line voltage of the word line signal WL starts to discharge to 0 after the inverted word line voltage of the inverted word line signal WLB starts to rise.

According to the word line modulation circuit 100 of the embodiment of the invention, the charge sharing-word line suppression driving mechanism and the capacitive coupling-word line overdrive mechanism can be realized by using only the architecture of the word line modulation circuit 100. Therefore, the word line modulation circuit 100 according to the embodiment of the invention can reduce the area occupied by the word line modulation circuit compared to the conventional word line modulation circuit. In addition, since the word line modulation circuit 100 proposed by the embodiment of the present invention does not generate a static current, the power consumption of the memory device can be reduced.

Reference numerals, such as "first", "second", etc., in the description and in the claims are used for convenience of description only and do not have a sequential relationship with each other.

The steps of a method or algorithm described in this specification may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module (including executable instructions and associated data) and other data may be stored in a data memory such as Random Access Memory (RAM), flash memory (flash memory), Read Only Memory (ROM), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), registers, hard disk, a removable disk, a compact disc read only memory (CD-ROM), a DVD, or any other computer-readable storage media format known in the art. A storage medium may be coupled to a machine, such as, for example, a computer/processor (for convenience of description, the processor is referred to herein as a "processor"), which can read information (such as program code) from, and write information to, the storage medium. A storage medium may incorporate a processor. An Application Specific Integrated Circuit (ASIC) includes a processor and a storage medium. A user equipment includes an ASIC. In other words, the processor and the storage medium are included in the user equipment in a manner not directly connected to the user equipment. Further, in some embodiments, any suitable computer program product includes a readable storage medium including program code associated with one or more of the disclosed embodiments. In some embodiments, the product of the computer program may comprise packaging material.

The above paragraphs use various levels of description. It should be apparent that the teachings herein may be implemented in a wide variety of ways and that any specific architecture or functionality disclosed in the examples is merely representative. Based on the teachings herein one skilled in the art should appreciate that each of the layers disclosed herein may be implemented independently or that more than two layers may be implemented in combination.

Although the present disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the invention should be determined by that of the appended claims.

Claims

1. A word line modulation circuit, comprising:

a first capacitor;

at least one inverter coupled to the word line and the inverted word line for receiving the inverted word line signal and generating a word line signal, and coupled to the first capacitor via the word line;

a power switch circuit coupled to the inverter and configured to receive a power switch control signal; and

at least one second capacitor coupled to the inverter and the power switch circuit at an internal node and configured to receive a boost signal.

2. The word line modulation circuit of claim 1, wherein the inverter comprises a first P-transistor and a first N-transistor, wherein a gate of the first P-transistor is coupled to a gate of the first N-transistor, and a gate of the first P-transistor and a gate of the first N-transistor are coupled to the inverted word line for receiving the inverted word line signal.

3. The word line modulation circuit as claimed in claim 2, wherein the drain of the first P-transistor is coupled to the drain of the first N-transistor, and the drain of the first P-transistor and the drain of the first N-transistor are coupled to the word line to generate the word line signal, wherein the word line is coupled to one terminal of the first capacitor, and the other terminal of the first capacitor is coupled to a ground node.

4. The word line modulation circuit of claim 3, wherein the source of the first P-transistor is coupled to the power switch circuit and the second capacitor at the internal node, and the source of the first N-transistor is coupled to the ground node.

5. The word line modulation circuit of claim 1, wherein said power switching circuit comprises at least a second P-type transistor.

6. The word line modulation circuit of claim 5, wherein a gate of the second P-transistor receives the power switch control signal, a drain of the second P-transistor is coupled to the inverter and the second capacitor at the internal node, and a source of the second P-transistor is coupled to a power node.

7. The word line modulation circuit of claim 1, wherein one terminal of the second capacitor is coupled to the inverter and the power switch circuit at an internal node, and the other terminal of the second capacitor receives the boost signal.

8. The word line modulation circuit according to claim 1, wherein during a read operation, when an inverted word line voltage of the inverted word line signal decreases, the charge on the internal node is transferred to the word line.

9. The word line modulation circuit according to claim 1, wherein in a write operation, when an inverted word line voltage of the inverted word line signal falls, the inverter charges the word line voltage of the word line to a power supply voltage, and a voltage of the boosting signal rises to inject charges to the internal node, and the charges on the internal node are transferred to the word line.

10. A method of charge sharing-wordline inhibit driving scheme for use in an assisted read operation of a wordline modulation circuit, comprising:

turning off a first P-transistor of an inverter of the word line modulation circuit and turning on a second P-transistor of a power switch circuit of the word line modulation circuit;

precharging the voltage of the internal node to a power voltage, wherein the inverter is coupled to a first capacitor via a word line, and the inverter and the power switch circuit are coupled to a second capacitor at the internal node;

increasing the voltage of the power switch control signal to turn off the second P-transistor of the power switch circuit;

lowering an inverted word line voltage of the inverted word line signal to turn on the first P-type transistor P1 of the inverter;

transferring the charges of the internal nodes to the word lines; and

after the reading operation is finished, whether the voltage of the power switch control signal is reduced earlier than the voltage of the inverted word line signal.

11. The method of charge sharing-wordline inhibit drive scheme of claim 10, further comprising:

when the voltage of the power switch control signal is decreased earlier than the time when the inverted word line voltage of the inverted word line signal is increased, the word line voltage of the word line signal is temporarily increased to the power supply voltage, and the word line voltage of the word line signal starts to be discharged to 0 after the inverted word line voltage of the inverted word line signal starts to be increased; and

when the time when the inverted word line voltage of the inverted word line signal rises is earlier than the time when the power switch control signal voltage falls, the word line voltage of the word line signal starts to discharge to 0 after the inverted word line voltage of the inverted word line signal starts to rise.

12. A method of capacitive coupling-word line over-drive mechanism, applied to auxiliary write operation of word line modulation circuit, includes:

lowering an inverted word line voltage of the inverted word line signal to turn on the first P-type transistor of the inverter, and precharging the word line voltage of the word line signal on the word line to a power supply voltage in advance;

increasing a voltage rise of a boost signal to inject charge into an internal node, wherein the inverter is coupled to a first capacitor via the word line, and the inverter and the power switch circuit are coupled to a second capacitor at the internal node;

transferring charge on the internal node to the word line; and

after the write operation is finished, it is determined whether the voltage of the power switch control signal is decreased earlier than the voltage of the inverted word line signal.

13. The method of a capacitively coupled-wordline overdrive scheme of claim 12, further comprising:

when the voltage of the power switch control signal is decreased earlier than the time when the inverted word line voltage of the inverted word line signal is increased, the word line voltage of the word line signal is temporarily decreased to the power supply voltage, and the word line voltage of the word line signal starts to be discharged to 0 after the inverted word line voltage of the inverted word line signal starts to be increased; and