CN112199324A - Reconfigurable acceleration core system for various encryption and decryption calculations and acceleration method thereof - Google Patents
Reconfigurable acceleration core system for various encryption and decryption calculations and acceleration method thereof Download PDFInfo
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- CN112199324A CN112199324A CN202011163743.2A CN202011163743A CN112199324A CN 112199324 A CN112199324 A CN 112199324A CN 202011163743 A CN202011163743 A CN 202011163743A CN 112199324 A CN112199324 A CN 112199324A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
- G06F15/7878—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS for pipeline reconfiguration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
Abstract
The invention provides a reconfigurable acceleration core system for various encryption and decryption calculations and an acceleration method thereof. The acceleration core system comprises a top-level control module for receiving the configuration flow from the external algorithm; an algorithm control module for receiving a configuration data stream from the top-level control module; a number theory operation cluster connected with the algorithm control module through a data processing special interface; a direct memory access control module for receiving a configuration data stream from the top-level control module; and the on-chip source data with the security processing unit, the result data storage module and the key storage module. According to the method, after the top-level control module receives the external algorithm configuration flow, the interconnection relationship between the algorithm control module and the number theory operation cluster and between the source data, the result data and the secret key storage module is reconstructed according to the configuration flow.
Description
Technical Field
The invention relates to a hardware architecture aiming at intensive computation, in particular to a reconfigurable acceleration core system aiming at various encryption and decryption computation and an acceleration method thereof.
Background
With the rapid development of information technology, the progress of cloud computing and the progress of the internet of things are gradually accelerated, and the data security problem is particularly important. In recent years, large-scale data leakage events are frequent and show an outbreak trend. 1/2019 to 30/2019, 5183 data leakage events are disclosed globally, and the leaked data amount reaches 79.95 hundred million records. For example, in 7 months 2019, database leaks for smart home company eurobo (orivibo) involve over 20 hundred million IoT logs. Therefore, a hardware acceleration core supporting various encryption algorithms is designed, and the method has important significance for playing the characteristics of different encryption algorithms in actual production life, and protecting data safety efficiently and flexibly.
An existing general-purpose processor, such as a Central Processing Unit (CPU), may also run encryption and decryption operations, but because the general-purpose processor adopts a method for executing a calculation task based on an instruction stream in an architectural design in order to achieve generality, time and power consumption consumed in running encryption and decryption calculations are large, and intensive encryption and decryption operations cannot be handled, which is not favorable for popularization of a high-performance encryption and decryption algorithm.
Another design idea for improving the computing performance is to design an asic for a specific algorithm, such as a dedicated RSA algorithm acceleration module, but different encryption/decryption algorithms are applied to different scenarios, and there are multiple encryption/decryption algorithms that need to be accelerated in one system, but integrating too many algorithm acceleration modules in a certain system results in a large chip area and high production cost.
Disclosure of Invention
The purpose of the invention is as follows: one purpose is to provide a reconfigurable acceleration core system for various encryption and decryption calculations, which uses the same set of computing resources for various different encryption and decryption algorithms, and changes the internal logic of a reconfigurable control core through configuration information to support acceleration of different algorithms, thereby solving the problems in the prior art. A further object is to propose an acceleration method based on the above system.
The technical scheme is as follows: a reconfigurable acceleration core system for multiple encryption and decryption calculations changes the calculation sequence of a calculation unit by changing the mode of in-chip connection through a reconfiguration unit, so that the same hardware resource is multiplexed to realize multiple encryption and decryption algorithms.
In a further embodiment, the acceleration core system includes a top level control module for receiving configuration streams from external algorithms and parsing associated content configuration algorithm control modules and direct memory access control modules; an algorithm control module for receiving a configuration data stream from the top-level control module; a number theory operation cluster connected with the algorithm control module through a data processing special interface; a direct memory access control module for receiving a configuration data stream from the top-level control module; and the on-chip source data with the security processing unit, the result data storage module and the key storage module. The acceleration core system further includes an AXI bus interface that connects the reconfigurable acceleration core for cryptographic computation with a processor that provides an externally supplied algorithm configuration stream.
In a further embodiment, the top-level control module is configured to parse the configuration data stream to obtain a corresponding configuration data stream, and send the configuration data stream to the algorithm control module and the direct storage access control module;
the algorithm control module reconstructs a connection line between the algorithm control module and the number theory operation cluster and the storage module according to the configuration data stream from the top control module to realize various different algorithms, specifically reads and distributes an encryption key and source data, and stores result data to corresponding positions after operation is finished;
the number theory operation cluster comprises a large number multiplication operation unit, a Montgomery algorithm-based modular exponentiation operation unit, a modular addition/subtraction calculation unit and other operation acceleration units inside, and is connected with the algorithm control module through a data processing special interface and used for finishing related calculation in the algorithm;
the direct storage access control module reconstructs a connection line between the direct storage access control module and the storage module according to the configuration data stream from the top control module, so that source data and a secret key in external storage are moved into a corresponding storage unit in the chip, and after encryption is finished, result data are transmitted back to the external storage;
the chip source data, result data storage module and key storage module are used for storing data required by operation, generated intermediate data and calculation encryption and decryption results.
In a further embodiment, the transmission parameters of the top-level control module when the data stream is transmitted to the algorithm control module and the direct memory access control module include the type of algorithm, encryption/decryption selection, encryption/decryption data length, data storage header address and grouping method, and the top-level control module includes a state machine unit and an algorithm sub-controller.
The algorithm types include, but are not limited to, RSA algorithm, SM2 cryptographic algorithm, BGV/BFV algorithm, etc.
In a further embodiment, the connection mode of the number-theory operation cluster and the algorithm control module is calculated according to the configuration flow to obtain the connection mode reconstruction of the multi-path selector, and the connection mode between the interiors of the number-theory operation clusters is calculated according to the configuration flow to obtain the connection mode reconstruction of the multi-path selector. A large number multiplication operation unit, a modular addition/modular subtraction unit, a Montgomery algorithm-based modular exponentiation operation unit and other acceleration operation units are integrated on a bus inside the number theory operation cluster and are connected with an algorithm control module through a data processing special interface.
In a further embodiment, the connection mode of the direct memory access control module and the on-chip source data with the security processing unit, the result data storage module and the key storage module is reconstructed according to the connection mode of the multiplexer calculated by the configuration flow.
In a further embodiment, the number theory operation cluster further includes a plurality of multiplexers and operation configuration registers, and the multiplexers and the operation configuration registers are respectively linked with the number theory operation cluster.
In a further embodiment, the chip source data, the result data storage module and the key storage module respectively include at least one security processing unit, and the security processing unit automatically clears the data stored therein after each batch of calculation is finished to ensure data security.
In a further embodiment, the top-level control module includes a device configuration register, and the device configuration register is used for storing the algorithm type, the algorithm-related parameters, the encryption/decryption data length, and the start address of the data stored in the external storage.
In a further embodiment, a plurality of on-chip source data storage modules with security processing units and key storage modules are integrated on the chip, and are used for temporarily storing the source data and the keys and clearing the data stored in the source data and the keys when called by different users to ensure data security. And a plurality of on-chip result data storage modules are integrated on the chip to ensure the calculation throughput rate.
A reconfigurable acceleration method for a plurality of encryption and decryption calculations comprises the following steps:
step 1, after a hardware device is powered on and initialized, an external general processor sends a configuration information stream to a top-level control module through an AXI bus, and the top-level control module analyzes the configuration information stream after determining that the configuration information stream is valid, and generates and transmits a data stream of a configuration algorithm control module and a direct storage access control module;
step 2, after the direct storage access control module receives the configuration data stream from the top control module, reconstructing a connection mode of a bus and a storage unit to complete transmission work of source data and a secret key from outside to inside;
and 3, starting calculation after data transmission is finished: the algorithm control module receives the configuration data stream from the top control module after the transmission of source data and a secret key required by encryption and decryption calculation is finished, and reconstructs the connection mode of the configuration data stream with an operation cluster and the source data, result data and a secret key storage unit to finish the realization of different algorithms;
step 4, after the calculation is finished, carrying out the result data, and at the moment, sending the corresponding configuration data stream to the storage access control module by the top control module again; after receiving the new configuration data stream, the direct memory access control module reconstructs the connection mode of the bus and the memory cell again to finish the transmission work of the result data from the inside to the outside of the chip;
and 5, after the algorithm of one batch is finished, emptying the data stored in the source data, the result data and the key storage unit to prepare for the encryption and decryption calculation of the next batch.
The invention has the beneficial effects that:
1. the method has high computing performance, and compared with a general computing platform, the method can achieve higher efficiency and energy efficiency. Compared with mainstream products in the market, the energy efficiency ratio is improved by more than 100 times, and after the top-level control module receives the external algorithm configuration stream, the interconnection relationship between the algorithm control module and the number theory operation cluster and between the source data, the result data and the secret key storage module is reconstructed according to the configuration stream. Aiming at the resource condition in the operation cluster, the invention also can carry out optimization processing aiming at different sub-algorithms to ensure the overall performance.
2. The hardware cost is less, and further, the chip area is small, and the production cost is low. Compared with the FPGA realized based on a lookup table, the FPGA can complete the same function, and the area of the special integrated circuit adopting hard wiring is smaller. Compared with an ASIC (application specific integrated circuit) framework with one set of computing resources, the framework provided by the invention can enable a plurality of different algorithms to use the same set of hardware resources, and reduce the expenditure of the hardware resources, thereby further reducing the area and the production cost of a chip and having great advantages in the field of chip design with severe area requirements.
3. The reconstruction time is short, further the time required for switching between different algorithms is short. The reconstruction time required by the current mainstream FPGA product for realizing different algorithms is 50-300 milliseconds, the reconstruction time of the framework in the invention is less than 100 clock cycles, and the reconstruction time is less than 1 microsecond taking 1GHz clock frequency as an example.
Drawings
Fig. 1 is a schematic diagram of an encryption/decryption computation-oriented reconfigurable acceleration core architecture in the present invention.
Fig. 2 is a schematic diagram of a work flow of an encryption/decryption calculation-oriented reconfigurable acceleration core architecture in the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
The applicant believes that when the existing general-purpose processor runs encryption and decryption operations, because the general-purpose processor adopts a method for executing calculation tasks based on instruction streams in order to realize universality, the time and power consumption spent in running the encryption and decryption operations are large, intensive encryption and decryption operations cannot be dealt with, and the popularization of a high-performance encryption and decryption algorithm is not facilitated. While a specific algorithm is designed with a dedicated integrated circuit, such as a dedicated RSA algorithm acceleration module, but different encryption and decryption algorithms are applied to different scenes, and there are multiple encryption and decryption algorithms that need to be accelerated in one system, but integrating too many algorithm acceleration modules in a certain system results in a large chip area and high production cost.
Therefore, the invention provides a reconfigurable acceleration core system for various encryption and decryption calculations and an acceleration method thereof, which are used for deeply researching a certain algorithm, extracting common operators in the algorithm and multiplexing computing resources through ingenious design, so that different algorithms can use the same set of computing resources, hardware resources and area overhead are effectively reduced, and the manufacturing cost of a chip is reduced.
The acceleration core system comprises a top-level control module, a plurality of mathematical operation clusters, an algorithm control module, a direct storage access control module, a communication interface, a result data storage module, an on-chip source data storage module with a safety processing unit and a secret key storage module. The top control module receives the configuration flow from the external algorithm, calculates to obtain the corresponding configuration data flow and transmits the corresponding configuration data flow to the algorithm control module and the direct storage access control module. The internal bus of the number theory operation cluster is integrated with acceleration operation units such as a large number multiplication operation unit, a Montgomery algorithm-based modular exponentiation operation unit and the like, and is connected with the algorithm control module through a data processing special interface. The algorithm control module is responsible for receiving the configuration data stream from the top control module, reading and distributing the encryption key and the source data according to the configuration data stream, and storing the result data to a corresponding position after the operation is finished. The direct storage access control module receives the configuration data stream from the top control module, accordingly loads the source data and the secret key in the external storage into the corresponding storage unit in the chip, and transmits the result back to the external storage after the encryption/decryption is finished. The hardware equipment corresponding to the architecture is started, and an external general-purpose processor is required to input corresponding configuration. The configuration data stream containing control information is transmitted from the AXI bus and stored in the corresponding register of the top control module. The top control module comprises a configuration register, an operation configuration register, a data transmission parameter register, a state register and an abnormal interruption register. The register is used for receiving configuration information flow from the outside, a configuration algorithm control module and a direct storage access control module.
The configuration data stream includes the type of algorithm, encryption and decryption selection, the length of encryption/decryption data, the grouping method of source data and the data storage head address. The state register is developed to be readable, so that the external general processor can obtain the current working mode of the hardware equipment corresponding to the architecture, whether the hardware equipment effectively receives the configuration information, whether the hardware equipment is busy or not, and whether the hardware equipment generates error interrupt or not, and therefore the external general processor can judge whether a new configuration data stream is sent or not.
As shown in fig. 2, after the hardware device is powered on and initialized, the external general processor sends a configuration information stream to the top control module through the AXI bus, and the top control module analyzes the configuration information stream after determining that the configuration information stream is valid, and generates and transmits data streams of the configuration algorithm control module and the direct memory access control module.
And the direct storage access control module reconstructs a connection mode of a bus and a storage unit after receiving the configuration data stream from the top control module, and completes transmission work of source data and a secret key from outside to inside.
After the data transmission is finished, the calculation can be started. The algorithm control module is a core module for completing algorithm hardware realization in the whole framework, receives the configuration data stream from the top control module after the transmission of source data and a secret key required by encryption and decryption calculation is finished, and reconstructs the connection mode of the configuration data stream with the operation cluster, the source data, the result data and the secret key storage unit according to the configuration data stream to complete the realization of different algorithms.
And after the calculation is finished, carrying out the result data, and sending the corresponding configuration data stream to the storage access control module by the top control module again. And after receiving the new configuration data stream, the direct storage access control module reconstructs the connection mode of the bus and the storage unit again to finish the transmission work of the result data from the inside of the chip to the outside of the chip.
After one batch of algorithms is finished, the encryption and decryption calculation of the next batch is carried out only when the source data, the result data and the key storage unit empty the data stored in the source data, the result data and the key storage unit so as to ensure the security of the data.
Each submodule has a corresponding feedback signal after completing corresponding operation, the algorithm control module feeds back a calculation completion signal to the top-level control module after calculation is finished, and the direct storage access control module feeds back a transmission completion signal after data transmission is finished.
As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited thereto. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A reconfigurable acceleration core system for various encryption and decryption calculations is characterized in that a calculation sequence of a calculation unit is changed by changing an in-chip connection mode through a reconfiguration unit, so that the same hardware resource is multiplexed to realize various encryption and decryption algorithms.
2. The reconfigurable acceleration core system for various encryption and decryption calculations according to claim 1, characterized by the following modules:
a top level control module for receiving a configuration stream from an external algorithm;
an algorithm control module for receiving a configuration data stream from the top-level control module;
a number theory operation cluster connected with the algorithm control module through a data processing special interface;
a direct memory access control module for receiving a configuration data stream from the top-level control module;
the system comprises on-chip source data with a safety processing unit, a result data storage module and a key storage module.
3. The reconfigurable acceleration core system for various encryption and decryption calculations according to claim 1, wherein the top control module is configured to parse the configuration data stream to obtain a corresponding configuration data stream, and send the configuration data stream to the algorithm control module and the direct storage access control module;
the algorithm control module reads and distributes an encryption key and source data according to the configuration data stream from the top control module, and stores result data to a corresponding position after operation is finished;
the number theory operation cluster comprises a large number multiplication operation unit, a Montgomery algorithm-based modular exponentiation operation unit, a modular addition/subtraction calculation unit and other operation acceleration units inside, and is connected with the algorithm control module through a data processing special interface and used for finishing related calculation in the algorithm;
the direct storage access control module loads source data and a secret key in external storage into a corresponding storage unit in the chip according to the configuration data stream from the top control module, and transmits result data back to the external storage after encryption is finished;
the chip source data, result data storage module and key storage module are used for storing data required by operation, generated intermediate data and calculation encryption and decryption results.
4. The reconfigurable acceleration core system for multiple encryption and decryption calculations according to claim 1, wherein the transmission parameters of the top control module when the top control module transmits the data stream to the algorithm control module and the direct memory access control module include the type of algorithm, encryption and decryption selection, encryption/decryption data length, data storage header address and grouping method.
5. The reconfigurable acceleration core system for multiple encryption and decryption calculations according to claim 1, characterized in that the connection mode of the number theory operation cluster and the algorithm control module is calculated according to the configuration flow to obtain the connection mode reconfiguration of the multiplexer, and the connection mode between the insides of the number theory operation cluster is calculated according to the configuration flow to obtain the connection mode reconfiguration of the multiplexer.
6. The reconfigurable acceleration core system for multiple encryption and decryption calculations according to claim 1, characterized in that the connection mode of the direct memory access control module and the on-chip source data with the security processing unit, the result data storage module and the key storage module is reconstructed according to the configuration flow calculation to obtain the connection mode of the multiplexer.
7. The reconfigurable acceleration core system for multiple encryption and decryption computations according to claim 1, wherein the number-theoretic computation cluster further comprises a plurality of multiplexers and computation configuration registers, and the multiplexers and the computation configuration registers are respectively linked with the number-theoretic computation cluster.
8. The reconfigurable acceleration core system for various encryption and decryption calculations according to claim 1, wherein the chip source data, the result data storage module and the key storage module respectively comprise at least one security processing unit, and the security processing unit automatically clears the data stored in each batch of calculation to ensure data security after each batch of calculation is finished.
9. The reconfigurable acceleration core system for multiple encryption and decryption calculations according to claim 1, wherein the top control module comprises a device configuration register, and the device configuration register is used for storing the algorithm type, the algorithm-related parameters, the encryption and decryption data length, and the start address of the data stored externally.
10. A reconfigurable acceleration method for various encryption and decryption calculations is characterized by comprising the following steps:
step 1, after a hardware device is powered on and initialized, an external general processor sends a configuration information stream to a top-level control module through an AXI bus, and the top-level control module analyzes the configuration information stream after determining that the configuration information stream is valid, and generates and transmits a data stream of a configuration algorithm control module and a direct storage access control module;
step 2, after the direct storage access control module receives the configuration data stream from the top control module, reconstructing a connection mode of a bus and a storage unit to complete transmission work of source data and a secret key from outside to inside;
and 3, starting calculation after data transmission is finished: the algorithm control module receives the configuration data stream from the top control module after the transmission of source data and a secret key required by encryption and decryption calculation is finished, and reconstructs the connection mode of the configuration data stream with an operation cluster and the source data, result data and a secret key storage unit to finish the realization of different algorithms;
step 4, after the calculation is finished, carrying out the result data, and at the moment, sending the corresponding configuration data stream to the storage access control module by the top control module again; after receiving the new configuration data stream, the direct memory access control module reconstructs the connection mode of the bus and the memory cell again to finish the transmission work of the result data from the inside to the outside of the chip;
and 5, after the algorithm of one batch is finished, emptying the data stored in the source data, the result data and the key storage unit to prepare for the encryption and decryption calculation of the next batch.
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