CN112199076B - Flight control software architecture and design method thereof - Google Patents
Flight control software architecture and design method thereof Download PDFInfo
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Abstract
A flight control software architecture and a design method thereof comprise the following steps: the core number N of the multi-core processor satisfies the following conditions: the number N of the cores is more than or equal to 2 and less than or equal to the maximum number HMax of the cores of the hardware processor, and the number N of the cores is less than or equal to PMax/P0; at least one core is used for external communication, and at least one core is used for flow scheduling; when the primary resolving time TGen of the general algorithm is larger than or equal to the control period T, at least one core is used for resolving the general algorithm; when a special algorithm is required and the primary resolving time TSpec of the special algorithm is more than or equal to T, at least one core is used for resolving the special algorithm; when a special algorithm is required and the primary resolving time TSpec of the special algorithm is less than T, completing the resolving of the special algorithm by a core for flow scheduling; and when the redundancy is needed, the core for flow scheduling determines the core for redundancy processing according to the redundancy mode. The method and the device can effectively utilize processing resources of the multi-core processor, and conveniently and quickly realize the multi-core flight control software architecture design.
Description
Technical Field
The present application relates to flight control technologies, and in particular, to a flight control software architecture and a design method thereof.
Background
Along with the intelligent development of the carrier rocket, the digitization of on-missile sensing and control information is faster and faster, the information integration level is higher and higher, the software scale of the carrier rocket is larger and larger, and higher requirements are provided for information core-level integration and fusion processing and high-efficiency software architecture. The rocket-borne application of the multi-core processor and the high-speed Ethernet greatly improves the parallel computing performance of the processor, improves the data communication efficiency of the internuclear/external interface, realizes multi-core resource sharing, reduces power consumption and cost, but has great advantages and brings practical problems of load balance distribution of flight control software tasks, high-speed data communication, real-time bus monitoring, real-time interrupt processing and the like to software developers. In order to meet the application requirements of rocket-borne multi-core processors, a general carrier rocket flight software architecture is a key technology for designing a control system.
The traditional single-core flight control software architecture is complex in design, is relatively tightly coupled with a hardware system and a transmission flow, and is not beneficial to maintenance and expansion.
Disclosure of Invention
The embodiment of the application provides a flight control software architecture and a design method thereof, so as to solve the technical problems.
According to a first aspect of embodiments of the present application, there is provided a flight control software architecture, comprising a multi-core processor, wherein,
the core number N of the processor satisfies the following conditions: the core number N is more than or equal to 2 and less than or equal to the maximum core number HMax of the hardware processor, the core number N is less than or equal to PMax/P0, PMax is the upper power consumption limit of the whole rocket-borne computer, and P0 is the running power consumption of a single core;
at least one core is used for external communication, and at least one core is used for flow scheduling;
when the primary resolving time TGen of the general algorithm is larger than or equal to the control period T, at least one core is used for resolving the general algorithm;
when a special algorithm is required and the primary resolving time TSpec of the special algorithm is more than or equal to T, at least one core is used for resolving the special algorithm; when a special algorithm is required and the primary resolving time TSpec of the special algorithm is less than T, completing the resolving of the special algorithm by a core for flow scheduling;
and when the redundancy is needed, the core for flow scheduling determines the core for redundancy processing according to the redundancy mode.
According to a second aspect of the embodiments of the present application, there is provided a flight control software architecture design method, including:
determining that the kernel number N of the flight control software satisfies: the core number N is more than or equal to 2 and less than or equal to the maximum core number HMax of the hardware processor, the core number N is less than or equal to PMax/P0, PMax is the upper power consumption limit of the whole rocket-borne computer, and P0 is the running power consumption of a single core;
at least one core is used for external communication, and at least one core is used for flow scheduling; when the primary resolving time TGen of the general algorithm is larger than or equal to the control period T, at least one core is used for resolving the general algorithm; when a special algorithm is required and the primary resolving time TSpec of the special algorithm is more than or equal to T, at least one core is used for resolving the special algorithm; when a special algorithm is required and the primary resolving time TSpec of the special algorithm is less than T, completing the resolving of the special algorithm by a core for flow scheduling; and when the redundancy is needed, the core for flow scheduling determines the core for redundancy processing according to the redundancy mode.
According to the flight control software architecture and the design method thereof provided by the embodiment of the application, hardware type selection, power consumption limitation, software functions, a general algorithm and a redundancy algorithm are used as design input, a top-layer framework of the multi-core flight control software of the carrier rocket is preliminarily determined according to the input, namely, a plurality of cores are required to run the flight control software, and each core runs which part of functions of the flight control software.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram illustrating a flight control software architecture in an embodiment of the present application.
Detailed Description
Aiming at the technical problems in the prior art, the embodiment of the application provides a multi-core flight control software architecture method, which shortens the software development period, optimizes the launch control flow, improves the expansibility and maintainability, solves the problems of low operation efficiency and low expansibility of flight control software, and can be widely applied to the design of the flight control software of a carrier rocket.
The scheme in the embodiment of the application can be implemented by adopting various computer languages, such as object-oriented programming language Java and transliterated scripting language JavaScript.
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Example one
FIG. 1 is a schematic diagram illustrating a flight control software architecture in an embodiment of the present application.
As shown, the flight control software architecture includes: a multi-core processor, wherein,
the core number N of the processor satisfies the following conditions: the core number N is more than or equal to 2 and less than or equal to the maximum core number HMax of the hardware processor, the core number N is less than or equal to PMax/P0, PMax is the upper power consumption limit of the whole rocket-borne computer, and P0 is the running power consumption of a single core;
at least one core is used for external communication, and at least one core is used for flow scheduling;
when the primary resolving time TGen of the general algorithm is larger than or equal to the control period T, at least one core is used for resolving the general algorithm;
when a special algorithm is required and the primary resolving time TSpec of the special algorithm is more than or equal to T, at least one core is used for resolving the special algorithm; when a special algorithm is required and the primary resolving time TSpec of the special algorithm is less than T, completing the resolving of the special algorithm by a core for flow scheduling;
and when the redundancy is needed, the core for flow scheduling determines the core for redundancy processing according to the redundancy mode.
According to the flight control software architecture provided by the embodiment of the application, hardware type selection, power consumption limitation, software functions, a general algorithm and a redundancy algorithm are used as design input, a top-layer framework of the multi-core flight control software of the carrier rocket is preliminarily determined according to the input, namely, several cores are required to run the flight control software, and each core runs the function of the part of the flight control software.
In one embodiment, the redundancy modes include a primary/secondary redundancy mode and a tertiary redundancy mode, and if the redundancy mode is the primary/secondary redundancy mode, at least one core is used for redundancy processing; if the redundancy mode is three-machine redundancy, at least three cores are used for redundancy processing.
In one embodiment, further comprising:
dividing a shared memory provided by a multi-core processor into N block memory areas; each block memory region is written with data by its corresponding core and read with data by other cores.
In one embodiment, the interactive data protocol among the plurality of cores comprises at least a source core number, a destination core number, a data type, a data length, a write valid flag, a checksum and valid data content; wherein the content of the first and second substances,
a source core number indicating the number of a core that transmits a protocol, the range being 0 to (N-1);
a destination core number indicating the number of a core receiving a protocol, the range being 0 to (N-1);
data types representing data classes of the protocol frames, each data type representing an operation or data;
a data length indicating the length of the protocol frame;
a write valid flag indicating whether the current protocol frame is the latest valid data;
a checksum representing the checksum of the valid data content of the protocol frame;
and the effective data content represents the effective data content transmitted at this time.
In one embodiment, the interaction data logic between the plurality of cores comprises:
any core writes prepared inter-core communication data used by other cores to a specified memory space, and informs other cores to read the inter-core communication data; performing write protection in a write process in a mutual exclusion lock mode; the notifying other cores to read the inter-core communication data includes: writing a write-valid flag in a fixed field in the inter-core communication data;
other cores read inter-core communication data and use the inter-core communication data to carry out corresponding algorithm calculation; reading protection is carried out in a mutual exclusion lock mode in the reading process; the other cores read inter-core communication data, including: inquiring whether the write-valid flag is valid; verifying the protocol stack data; copying data and clearing original data after the verification is passed; otherwise, the discard is not used.
In one embodiment, the functionality of a core for out-of-bound communication includes:
completing the loading of the core, including: initializing FLASH and RAM, and moving the code from FLASH to RAM;
completing the loading of other cores, including: moving the codes of other cores from the FLASH to the RAM, and sending an inter-core communication interrupt instruction;
completing hardware initialization of the kernel, including: hardware initialization of external memory, CACHE, timers, inter-core communication, or communication buses;
completing the initialization of the kernel software, comprising: initializing global variables, hardware interrupts, software interrupts, tasks, semaphores, mutexes, mailboxes, or events of the kernel;
finishing the bus data processing of external interaction, comprising: ethernet, 1553B, or RS 422.
In one embodiment, the functionality of a core for flow scheduling includes:
completing hardware initialization of the kernel, including: hardware initialization of CACHE, a timer and inter-core communication;
finishing the initialization of the kernel software;
according to different test states, a core for navigation processing is scheduled to select the original data of the inertial measurement unit read from the inertial measurement unit simulator or the real inertial measurement unit and the original data of the receiver read from the receiver simulator or the real receiver;
according to different flight time sequences of the current position, scheduling a core for resolving a general algorithm and a core for resolving a special algorithm for resolving;
the acquisition and format conversion of the telemetering information, the external time sequence instruction or the external control instruction of other cores are completed, and the information is respectively framed and then sent to the core for external communication;
and running a dynamic load balancing algorithm to supervise the running conditions of other cores.
In one embodiment, the functionality for resolving the cores of a generic algorithm includes:
finishing hardware initialization of the kernel;
finishing the initialization of the kernel software;
acquiring inertial data according to a minimum control period, if the inertial data is an optical fiber inertial data, performing temperature compensation on the acquired data, and performing filtering processing, wherein the last beat of data is used if the acquired inertial data is abnormal;
according to the minimum period required by the combined navigation algorithm, data acquisition of the navigation receiver is realized, filtering processing is carried out, and the navigation receiver is not suitable for the previous beat of data due to abnormal data reception;
the single-item test of the inertial measurement unit and the navigation receiver is realized;
fusion processing of inertial measurement unit and navigation data is realized, and speed, position and attitude information is output;
reading the data solidified in the FLASH for navigation guidance attitude control calculation;
according to the position, speed, attitude angle and time sequence information of the carrier rocket subjected to navigation calculation, guidance calculation is carried out in different modes at different stages, and three-channel pitch angle deviation and time sequence information are output;
and according to the three-channel pitch angle deviation and the time sequence information which are resolved by guidance, attitude control resolving is carried out in different modes at different stages, and a control execution mechanism instruction is output.
In one embodiment, the functionality for resolving the cores of the dedicated algorithm includes:
completing hardware initialization of the kernel;
finishing the initialization of the kernel software;
reading the metadata solidified in the FLASH for the calculation of the special algorithm;
blocking to wait for receiving inter-core communication data of the flow scheduling core flight control software, and returning the self-checking state of the core if the inter-core communication data is a self-checking instruction; if the data is the special algorithm initial data, storing the frame data for subsequent special algorithm calculation; if the instruction is a special algorithm calculation starting instruction, scheduling and executing a special algorithm function for calculation;
a special algorithm calculates a set timeout and a timeout exit mechanism;
and after the special algorithm is calculated, returning a calculation result to a core for flow scheduling, if the calculation is successful, returning a correct calculation result, and if the calculation is abnormal, returning fault abnormal information.
Example two
Based on the same inventive concept, the embodiment of the application provides a design method of a flight control software architecture, the principle of the method for solving the technical problem is similar to that of the flight control software architecture, and repeated parts are not repeated.
The flight control software architecture design method comprises the following steps:
determining that the kernel number N of the flight control software satisfies: the core number N is more than or equal to 2 and less than or equal to the maximum core number HMax of the hardware processor, the core number N is less than or equal to PMax/P0, PMax is the upper power consumption limit of the whole rocket-borne computer, and P0 is the running power consumption of a single core;
at least one core is used for external communication, and at least one core is used for flow scheduling; when the primary resolving time TGen of the general algorithm is larger than or equal to the control period T, at least one core is used for resolving the general algorithm; when a special algorithm is required and the primary resolving time TSpec of the special algorithm is more than or equal to T, at least one core is used for resolving the special algorithm; when a special algorithm is required and the primary resolving time TSpec of the special algorithm is less than T, completing the resolving of the special algorithm by a core for flow scheduling; and when the redundancy is needed, the core for flow scheduling determines the core for redundancy processing according to the redundancy mode.
According to the design method of the flight control software architecture, hardware type selection, power consumption limitation, software functions, a general algorithm and a redundancy algorithm are used as design input, a top-layer framework of the multi-core flight control software of the carrier rocket is preliminarily determined according to the input, namely, a plurality of cores are needed to run the flight control software, and each core runs the function of the flight control software.
EXAMPLE III
In order to facilitate the implementation of the present application, the embodiments of the present application are described with a specific example.
Design multi-core flight control software top-level architecture
The design function of the top-level architecture is realized by the following steps:
1) judging according to hardware type selection, and if the number of cores N in the design of a multi-core flight control software architecture is assumed, and the maximum number of cores of a hardware processor is HMax, then N < (HMax);
2) judging according to the power consumption limit, and if the running power consumption of a single core is P0 and the power consumption upper limit of the whole rocket-borne computer is PMax, designing the number N of cores in the multi-core flight control software architecture as PMax/P0;
3) judging according to software functions, wherein the multi-core architecture is at least 2 cores, namely N > -2, one core is used for external communication, the other core is used for flow scheduling, the flow scheduling comprises a pre-ignition emission flow and a post-ignition flight flow, and the external communication comprises but is not limited to Ethernet and 1553B, RS422 bus communication;
4) judging according to the processing time of a general algorithm, wherein the general algorithm comprises navigation, guidance and attitude control algorithms, assuming a control period T, the general algorithm solves the time TGen once, if TGen > is T, a processing core is required to be used for solving the general algorithm, otherwise, the general algorithm is finished in the core for flow scheduling;
5) judging according to whether a special algorithm processing requirement exists, if the special algorithm processing requirement does not exist, a special core does not need to be designed for special algorithm calculation; if a special algorithm is required, if the special algorithm is supposed to solve the time TSpec once, and TSpec > is T, a processing core is required to be used for the special algorithm to solve; if the special algorithm is required, TSpec is less than T, the special algorithm is completed in a core for flow scheduling;
6) judging according to whether redundancy is needed, wherein the redundancy has two types: 1. the method comprises the steps that main and standby redundancy is achieved, one core serves as a main core, the other core serves as a standby core, the same program is operated, the flow scheduling core judges that the standby core result is used when the main core fails, the strategy needs to be used, and the other core is used for algorithm processing; 2. the three-machine redundancy is realized, three processing cores run the same program, part of the main processing cores and the standby processing cores are judged by flow scheduling core software, a strategy of taking two out of three is adopted to output a final result, and the strategy needs to use 3 cores for algorithm processing.
Through the above steps, the basic architecture design of the multi-core flight control software can be determined, i.e., what the functions of each core are used for, using several cores.
(II) designing a data interaction mechanism between cores of multi-core flight control software
The data interaction between the cores of the multi-core flight control software is realized through the following steps:
a) and (3) planning a multi-core interactive data area: assuming that an N-core flight control software architecture is determined according to the step (a), by using a shared memory provided by a multi-core processor, N-block memory areas need to be divided on the shared memory, each core flight control software is responsible for writing, and other core flight control software is responsible for reading;
b) carrying out multi-core interactive data protocol design:
1) the multi-core interactive data protocol at least comprises a source core number, a destination core number, a data type, a data length, a write valid flag, a checksum and valid data content;
2) "Source core number" indicates the number of cores of the sending protocol, and the range is 0- (N-1);
3) the destination core number represents the number of the core of the sending protocol, the range is 0- (N-1), and the destination core number cannot be the same as the source core number;
4) "data type" indicates a data category of a protocol frame, each data type indicating an operation or a data;
5) "data length" means the length of a protocol frame;
6) the 'write valid flag' indicates whether the current protocol frame is the latest valid data;
7) "checksum" means the checksum of the valid data content of the protocol frame, and checksum methods include, but are not limited to, a sum, a CRC check;
8) the "valid data content" indicates the valid data content of the present transmission.
c) Carrying out multi-core interactive data logic design:
1) some inter-core communication data that is approved for use by other cores: the format of the inter-core communication data should meet the above requirements;
2) writing inter-core communication data to a set memory space by a certain core: writing the inter-core communication data to the address determined in the step a, protecting in a mutual exclusion lock mode in the writing process, preventing reading and writing conflicts caused by data reading of other cores at the moment, and if the shared memory area is mapped to CACHE, performing CACHE effective writing operation to prevent the situation that CACHE is inconsistent with the memory data;
3) and a core informs other cores to read inter-core communication data: there are two ways, one is query, by writing "write active flag" in fixed field in inter-core communication data, query once per minimum control cycle by other cores; one is interruption, by triggering the inter-core communication interruption of other cores, the other core flight control software sets an interruption service function, and the response of each interruption is regarded as the arrival of one effective data;
4) other core checking cores read inter-core communication data: other cores perform read protection in a mutual exclusion lock mode in the process of reading data and perform CACHE effective read operation, and if the core is in a query mode, each minimum control cycle performs data processing; if the interrupt mode is adopted, data processing is carried out through a special interrupt processing function;
5) other check inter-core communication data: firstly, inquiring whether a 'write valid flag' is valid, then verifying protocol stack data, copying data after the verification is passed, and removing original data, otherwise, discarding the data which is not applicable;
6) other cores use inter-core communication data: and using inter-core communication data sent by other cores for flow control core algorithm solution.
(III) design external communication core architecture
The core mainly completes the following functions:
a) and completing the loading of the kernel:
1) the initialization of the FLASH and the RAM is completed, the FLASH stores data which cannot be lost after the communication core flight control software is powered off, and the RAM is used as an operating memory space of the communication core flight control software;
2) completing the moving of codes of the communication core flight control software, and moving the codes from the FLASH to the RAM;
3) the communication core flight control software executes the jump instruction and starts to run at the entry function in the running memory.
b) Completing the loading of other cores:
1) completing the moving of codes of the flow scheduling core flight control software, and moving the codes from the FLASH to the RAM;
2) if the general algorithm core exists, the code of the general algorithm core flight control software is moved to the RAM from the FLASH;
3) if the special algorithm core exists, the code of the special algorithm core flight control software is moved to the RAM from the FLASH;
4) if the redundancy algorithm core exists, the code of the flight control software of the redundancy algorithm core is moved to the RAM from the FLASH;
5) sending an inter-core communication interrupt instruction, executing a program jump instruction after other core flight control software receives the interrupt, and starting to run at an entry function in a running memory;
6) the communication core flight control software executes the jump instruction and starts to run at the entry function in the running memory.
c) And (4) finishing hardware initialization of the kernel:
1) hardware initialization of external memory is completed, including but not limited to FLASH, RAM, storage for data and program;
2) completing hardware initialization of CACHE for data storage of the flight control software of the core;
3) completing hardware initialization of a timer for timing of the local flight control software;
4) completing hardware initialization of inter-core communication, and performing data interaction with other cores;
5) hardware initialization of the communication bus is accomplished, including but not limited to ethernet, 1553B, RS422 for bus communication with external devices.
d) And (4) finishing the initialization of the kernel software:
1) and finishing the initialization of the global variables of the cost core, and storing intermediate variables of flow processing and algorithm calculation.
2) If the interrupt exists, finishing the initialization of the hardware interrupt, wherein the hardware interrupt is used for responding to an external asynchronous event;
3) if the software interrupt exists, the initialization of the software interrupt is completed, and the software interrupt is used for responding to the internal asynchronous time;
4) if the task exists, the initialization of the task is completed, and the task is used for completing flow processing and algorithm calculation;
5) if the semaphore, the mutex lock, the mailbox and the event exist, the initialization of the semaphore, the mutex lock, the mailbox and the event is completed, and the method is used for realizing data interaction among tasks, software interrupts and interrupts.
e) Completing single tests such as bus access test, time synchronization test and the like;
f) completing comprehensive flow tests such as polarity test, mold flying test and the like;
g) completing a real arrow launching simulation test;
h) and bus data processing of Ethernet, 1553B, RS422 and the like for external interaction is completed.
(IV) design flow scheduling core architecture
The core performs the following basic functions:
a) finishing hardware initialization of the kernel;
1) completing hardware initialization of CACHE for data storage of the core flight control software;
2) completing hardware initialization of a timer for timing of the local flight control software;
3) and completing hardware initialization of inter-core communication for data interaction with other cores.
b) Finishing the initialization of the kernel software, and giving details about the initialization content of the communication processing kernel software;
c) according to different test states, the scheduling navigation processing core selects the original data of the inertial set read from the inertial set simulator or the real inertial set and the original data of the receiver read from the receiver simulator or the real receiver;
d) according to different flight time sequences of the current position, scheduling a general algorithm core and a special algorithm core for resolving;
e) completing the acquisition and format conversion of the telemetering information of other cores, framing and then sending to a communication processing core;
f) finishing the acquisition and format conversion of an external time sequence instruction, framing and then sending to a communication processing core;
g) finishing the acquisition and format conversion of an external control instruction, framing and then sending to a communication processing core;
h) and running a dynamic load balancing algorithm to supervise the running conditions of other cores.
(V) design general algorithm processing core architecture
If the top architecture is designed and planned, the general algorithm processor core at least comprises the following basic functions, otherwise, the following functions are completed in the flow scheduling core:
a) completing initialization of hardware of the core, and referring to initialization content of software of a flow scheduling core in detail;
b) finishing the initialization of the kernel software, and giving details about the initialization content of the communication processing kernel software;
c) acquiring inertial data according to a minimum control period, if the inertial data is an optical fiber inertial data, performing temperature compensation on the acquired data, and performing filtering processing, wherein the last beat of data is used if the acquired inertial data is abnormal;
d) according to the minimum period required by the combined navigation algorithm, data acquisition of the navigation receiver is realized, filtering processing is carried out, and the navigation receiver is not suitable for the previous beat of data due to abnormal data reception;
e) the single test of the inertial measurement unit and the navigation receiver is realized:
1) calculating the rotational angular velocity, the gravitational acceleration and the non-levelness of the earth, and measuring the functions and the performances of the inertial measurement unit;
2) completing the polarity test of the inertial measurement unit, solving a three-channel attitude angle of the rocket, and measuring the installation polarity of the inertial measurement unit;
3) reading the data elements and the self-checking content of the inertial measurement unit, and measuring the factory state of the inertial measurement unit.
4) Reading the original data content of the navigation receiver, and measuring the function and performance of the navigation receiver;
5) and reading ephemeris and self-checking content of the navigation receiver, and measuring the factory state of the navigation receiver.
f) And the fusion processing of the inertial measurement unit and navigation data is realized, and speed, position and attitude information is output.
1) According to the inertia group data, completing calculation of an initial value of the attitude angle of the rocket in the horizontal state before ignition;
2) according to the inertia group data, completing the tracking of the attitude angle when the rocket is erected before ignition;
3) according to the inertial data, operating an inertial navigation algorithm to complete the calculation of the position, the speed and the attitude angle of the launching inertial system after the rocket is ignited;
4) according to the inertial data and navigation receiver data, operating a combined navigation algorithm to complete the calculation of the position, speed, attitude angle, time sequence and other telemetering data after the rocket is ignited and the inertial system is launched and combined;
5) finishing the sorting of the telemetering data and sending to the flow scheduling nuclear flight control software.
g) Reading the data solidified in the FLASH for navigation guidance attitude control calculation;
h) according to the position, speed, attitude angle and time sequence information of the carrier rocket subjected to navigation calculation, guidance calculation is carried out in different modes at different stages, and three-channel pitch angle deviation and time sequence information are output;
i) and according to the three-channel pitch angle deviation and the time sequence information which are resolved by guidance, attitude control resolving is carried out in different modes at different stages, and control executing mechanism instructions are output, wherein the control executing mechanism instructions include but are not limited to rudder deviation instructions and attitude control spray pipe switching instructions.
(VI) design-specific algorithm processing core architecture
If the core is planned during the design of the top-level architecture, the special algorithm processor core at least comprises the following basic functions:
a) completing initialization of hardware of the core, and referring to initialization content of software of a flow scheduling core in detail;
b) finishing the initialization of the kernel software, and giving details about the initialization content of the communication processing kernel software;
c) reading the metadata solidified in the FLASH for the calculation of the special algorithm;
d) blocking to wait for receiving inter-core communication data of the flow scheduling core flight control software, and returning the self-checking state of the core if the inter-core communication data is a self-checking instruction; if the data is the special algorithm initial data, storing the frame data for subsequent special algorithm calculation; if the instruction is a special algorithm calculation starting instruction, scheduling and executing a special algorithm function for calculation;
e) a special algorithm calculates a set timeout and a timeout exit mechanism, so that the situation that flight control software is jammed due to hardware faults or logic design errors is prevented;
f) and after the special algorithm is calculated, returning a calculation result to the flow scheduling core, if the calculation is successful, returning a correct calculation result, and if the calculation is abnormal, returning fault abnormal information.
(VII) design redundancy algorithm processing core architecture
If the top architecture is designed with the core planned, the redundancy algorithm processor core at least comprises the following basic functions:
a) if the core runs a redundant general algorithm, all general algorithm core contents are contained;
b) if the core runs a redundant special algorithm, all the special algorithm core contents are contained;
c) the redundant algorithm core should design a heartbeat mechanism, and periodically sends the heartbeat mechanism to the process scheduling core for process monitoring of the process scheduling core.
The embodiment of the application has the following advantages:
1) the application provides a design method of a top-level architecture of multi-core flight control software, wherein hardware selection, power consumption limitation, software functions, a general algorithm and a redundancy algorithm are used as design input, a top-level framework of the multi-core flight control software of a carrier rocket is preliminarily determined according to the input, namely, a plurality of cores are required to run the flight control software, and each core runs which part of functions of the flight control software;
2) the embodiment of the application also provides a data interaction method among the cores of the multi-core flight control software, the data area of the multi-core flight control software is divided from the top layer, the unique data area and the common data area of each core are determined, then the data interaction protocol of the multi-core flight control software is designed, and finally the data interaction flow is described;
3) the method is characterized in that the architecture of each core flight control software is designed aiming at a multi-core flight control software architecture, and mainly comprises an external communication core, a process scheduling core, a general algorithm core, a special algorithm core and a redundant algorithm core, wherein the external communication core and the process scheduling core are basic components of the multi-core flight control software, and the general algorithm core, the special algorithm core and the redundant algorithm core are expanded according to needs, so that the expansibility and the maintainability of the flight control software can be remarkably improved.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. Flight control software architecture, comprising a multi-core processor, wherein,
the core number N of the processor satisfies the following conditions: the core number N is more than or equal to 2 and less than or equal to the maximum core number HMax of the hardware processor, the core number N is less than or equal to PMax/P0, PMax is the upper power consumption limit of the whole rocket-borne computer, and P0 is the running power consumption of a single core;
at least one core is used for external communication, and at least one core is used for flow scheduling;
when the primary resolving time TGen of the general algorithm is larger than or equal to the control period T, at least one core is used for resolving the general algorithm; otherwise, the general algorithm is completed in the core for flow scheduling; the general algorithm comprises navigation, guidance and attitude control algorithms;
when a special algorithm is required and the one-time resolving time TSpec of the special algorithm is larger than or equal to T, at least one core is used for resolving the special algorithm; when a special algorithm is required and the primary resolving time TSpec of the special algorithm is less than T, completing the resolving of the special algorithm by a core for flow scheduling; the dedicated algorithms comprise algorithms having algorithm processing requirements in addition to the generic algorithms;
and when the redundancy is needed, the core for flow scheduling determines the core for redundancy processing according to the redundancy mode.
2. The flight control software architecture of claim 1, wherein the redundancy modes include primary and secondary redundancy and tertiary redundancy, and if the redundancy mode is primary and secondary redundancy, at least one core is used for redundancy processing; if the redundancy mode is three-machine redundancy, at least three cores are used for redundancy processing.
3. The flight control software architecture of claim 1, further comprising:
dividing a shared memory provided by a multi-core processor into N block memory areas; each block memory region is written by its corresponding core and read by other cores.
4. The flight control software architecture of claim 1, wherein the interactive data protocols between the plurality of cores include at least a source core number, a destination core number, a data type, a data length, a write valid flag, a checksum, and a valid data content; wherein the content of the first and second substances,
a source core number indicating the number of a core that transmits a protocol, the range being 0 to (N-1);
a destination core number indicating the number of a core receiving a protocol, the range being 0 to (N-1);
data types representing data classes of the protocol frames, each data type representing an operation or data;
a data length indicating the length of the protocol frame;
a write valid flag indicating whether the current protocol frame is the latest valid data;
a checksum representing the checksum of the valid data content of the protocol frame;
and the effective data content represents the effective data content transmitted at this time.
5. The flight control software architecture of claim 1, wherein the interaction data logic between the plurality of cores comprises:
any core writes prepared inter-core communication data used by other cores to a specified memory space, and informs other cores to read the inter-core communication data; performing write protection in a write process in a mutual exclusion lock mode; the notifying other cores to read the inter-core communication data includes: writing a write-valid flag in a fixed field in the inter-core communication data;
other cores read inter-core communication data and use the inter-core communication data to carry out corresponding algorithm calculation; reading protection is carried out in a mutual exclusion lock mode in the reading process; the other cores read inter-core communication data, including: inquiring whether the write-valid flag is valid; verifying the protocol stack data; copying data and clearing original data after the verification is passed; otherwise, the discard is not used.
6. The flight control software architecture according to claim 1, characterized in that the functions of the core for external communication comprise:
completing the loading of the core, including: initializing FLASH and RAM, and moving the code from FLASH to RAM;
completing the loading of other cores, including: moving the codes of other cores from the FLASH to the RAM, and sending an inter-core communication interrupt instruction;
completing hardware initialization of the kernel, including: hardware initialization of external memory, CACHE, timers, inter-core communication, or communication buses;
completing the initialization of the kernel software, comprising: initializing global variables, hardware interrupts, software interrupts, tasks, semaphores, mutexes, mailboxes, or events of the kernel;
finishing the bus data processing of external interaction, comprising: ethernet, 1553B, or RS 422.
7. The flight control software architecture of claim 1, wherein the functionality of the core for flow scheduling comprises:
completing hardware initialization of the kernel, including: hardware initialization of CACHE, a timer and inter-core communication;
completing the initialization of the kernel software;
according to different test states, a core for navigation processing is scheduled to select the original data of the inertial measurement unit read from the inertial measurement unit simulator or the real inertial measurement unit and the original data of the receiver read from the receiver simulator or the real receiver;
according to different flight time sequences of the current position, scheduling a core for resolving a general algorithm and a core for resolving a special algorithm for resolving;
the acquisition and format conversion of the telemetering information, the external time sequence instruction or the external control instruction of other cores are completed, and the information is respectively framed and then sent to the core for external communication;
and running a dynamic load balancing algorithm to supervise the running conditions of other cores.
8. The flight control software architecture according to claim 1, characterized in that the functions of the core for resolving the general algorithm comprise:
finishing hardware initialization of the kernel;
finishing the initialization of the kernel software;
acquiring inertial data according to a minimum control period, if the inertial data is an optical fiber inertial data, performing temperature compensation on the acquired data, and performing filtering processing, wherein the last beat of data is used if the acquired inertial data is abnormal;
according to the minimum period required by the combined navigation algorithm, data acquisition of the navigation receiver is realized, filtering processing is carried out, and the navigation receiver is not suitable for the previous beat of data due to abnormal data reception;
realizing single-item test of the inertial measurement unit and the navigation receiver;
fusion processing of inertial measurement unit and navigation data is realized, and speed, position and attitude information is output;
reading the data solidified in the FLASH for navigation guidance attitude control calculation;
according to the position, the speed, the attitude angle and the time sequence information of the carrier rocket subjected to navigation resolving, guidance resolving is carried out in different modes at different stages, and three-channel pitch angle deviation and time sequence information are output;
and according to the three-channel pitch angle deviation and the time sequence information which are resolved by guidance, attitude control resolving is carried out in different modes at different stages, and a control execution mechanism instruction is output.
9. The flight control software architecture of claim 1, wherein the functions of the cores to solve the dedicated algorithm include:
finishing hardware initialization of the kernel;
completing the initialization of the kernel software;
reading the metadata solidified in the FLASH for the calculation of the special algorithm;
blocking to wait for receiving inter-core communication data of flow scheduling core flight control software, and returning the self-checking state of the core if the inter-core communication data is a self-checking instruction; if the data is the special algorithm initial data, storing the frame data for subsequent special algorithm calculation; if the instruction is a special algorithm calculation starting instruction, scheduling and executing a special algorithm function for calculation;
a special algorithm calculates a set timeout and a timeout exit mechanism;
and after the special algorithm is calculated, returning a calculation result to a core for flow scheduling, if the calculation is successful, returning a correct calculation result, and if the calculation is abnormal, returning fault abnormal information.
10. A flight control software architecture design method is characterized by comprising the following steps:
determining that the kernel number N of the flight control software satisfies: the core number N is more than or equal to 2 and less than or equal to the maximum core number HMax of the hardware processor, the core number N is less than or equal to PMax/P0, PMax is the upper power consumption limit of the whole rocket-borne computer, and P0 is the running power consumption of a single core;
at least one core is used for external communication, and at least one core is used for flow scheduling; when the primary resolving time TGen of the general algorithm is larger than or equal to the control period T, at least one core is used for resolving the general algorithm; when a special algorithm is required and the primary resolving time TSpec of the special algorithm is more than or equal to T, at least one core is used for resolving the special algorithm; when a special algorithm is required and the primary resolving time TSpec of the special algorithm is less than T, completing the resolving of the special algorithm by a core for flow scheduling; and when the redundancy is needed, the core for flow scheduling determines the core for redundancy processing according to the redundancy mode.
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