CN106775659B - Embedded dual-core flight control software architecture method based on high-speed Linkport interface - Google Patents
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Abstract
The invention discloses an embedded dual-core flight control software architecture method based on a high-speed Linkport interface, which comprises the following steps of task division of dual-core flight control software, step two of flight control software dual-core communication mechanism design, step three of flight control software dual-core data sharing mechanism, and step four of flight control software dual-core reliability design.
Description
Technical Field
The invention relates to the field of unmanned aerial vehicle flight control software, in particular to an embedded dual-core flight control software architecture method based on a high-speed Linkport interface.
Background
The flight control computer is a core part of the flight control system of the unmanned aerial vehicle, new higher requirements are provided for the performance of a hardware platform and a software platform of the flight control computer along with the expansion of a flight envelope of the unmanned aerial vehicle and the increasing complexity of a task environment, and the performance of the flight control computer directly determines whether the unmanned aerial vehicle can reliably complete a flight task or not.
With the continuous push of the application of the dual-core architecture, the dual-core microprocessor technology is gradually mature, and how to design a stable and efficient dual-core system software architecture to overcome the problems of the single core becomes the key point of the current research.
Disclosure of Invention
The invention overcomes the defects of the prior art and provides embedded dual-core flight control software architecture methods based on a high-speed Linkport interface.
In order to solve the technical problems, the invention adopts the following technical scheme:
embedded dual-core flight control software architecture method based on high-speed Linkport interface, the method includes the following steps:
step , dual-core flight control software task division
The primary core in the dual cores is used for flight control, and the secondary core is used for realizing navigation calculation;
step two, designing a dual-core communication mechanism of flight control software
Designing a reliable communication protocol and a non-reply communication protocol on the basis of Linkport interface communication;
third step, flight control software dual-core data sharing mechanism
Setting a double-buffer semaphore mechanism;
step four, designing dual-core reliability of flight control software
Reliable inter-core communication is guaranteed by monitoring communication faults in real time and restarting inter-core communication;
the dual-core reliable start is ensured through a program operation start calibration mechanism;
and the reliable operation of the dual cores is ensured by monitoring the operation monitoring mechanism of the slave cores through the master core.
The technical scheme of step is that step includes that the master core completes slave core integrated navigation data, control rule calculation and steering engine control rule calculation, and the slave core completes IMU data, GPS data acquisition, integrated navigation calculation and navigation data output to the master core.
, the second step includes that the dual core communication communicates through a high speed Linkport interface and cooperates with data transmission interruption, when the main core needs to transmit data to the slave core, the main core packages the fixed 2K data into the Linkport data interface, after the transmission is completed, the slave core sends out data transmission interruption, after the slave core receives the interruption, the data is considered to be transmitted, the fixed 2K data is read from the Linkport interface, and the transmission process is completed.
The technical solution of step is that the slave core transmits data to the master core in the same manner as the master core transmits data to the slave core.
, the reliable transmission communication protocol in the second step is to perform data sub-packaging on the data to be sent, divide the data into data packets of fixed 2K size, frame the data according to the frame protocol, after receiving the data, the receiver first performs frame head check judgment, if the frame head check is wrong, the receiver sends an error receiving instruction to request the sender to resend the data, if the judgment is correct, the receiver sends a correct data receiving instruction to the receiver, and after receiving and sending the correct instruction, the receiver starts sending down packet data, if the frame head check of the data received by the receiver is correct, the frame content judgment is wrong, the receiver sends a data request instruction, after receiving the instruction, the receiver sends the data frame pointed by the request frame, after all data transmission is completed, the sender requests the receiver to send back total data CRC codes, the sender receives CRC codes and calculates the CRC codes of the total data, and after the comparison is correct, the transmission is completed.
The technical solution of step is that the non-reply communication protocol in step two is that the communication data transmits data according to 2K data frame format, and the receiver only judges the frame header and the checksum.
The technical solution of step is that the double-buffer semaphore mechanism in step three includes setting A, B double buffers, a lock flag bit and an access flag bit, when a thread is written to access a critical area, determining whether to lock the critical area, if the lock state indicates that the master function is reading the contents of the critical area, writing another areas of the access flag bit, and setting the access flag bit as a mark of the just-written area, when the thread is read, firstly locking the critical area, and then reading the data indicated by the access flag bit and then unlocking the critical area.
And , after entering the flight task flow, sending the combined navigation data and the intermediate result data to the master core at intervals by the slave core, setting the master core to interrupt to receive the slave core data, resetting the counter if the interrupt and the received data are correct, and simultaneously monitoring the interrupt by paths to accumulate the counter, if the accumulated amount of the counter is greater than the limit, considering the communication fault, executing the communication interface restart code of the master core and the slave core, restarting the inter-core communication, and ensuring the inter-core reliable communication.
And , the fourth step includes that after the program is powered on, another program needs to be waited for to run, and after the two programs pass through simultaneously, the dual-core flight program starts to run, otherwise, the two programs do not run, thereby ensuring the dual-core reliable start.
The technical scheme of step is that the fourth step includes that the master core monitors a preset operation signal of the slave core for a preset time, if the preset signal of the slave core cannot be received in 5 consecutive periods, the slave core is considered to have abnormal operation, the master core sends a slave core restart signal to force the slave core to restart, after the restart, the prestored data of the slave core operation is sent to the slave core, the slave core uses the prestored data to recover to a state before the restart, combined navigation calculation is recovered, and reliable dual-core operation is guaranteed.
Compared with the prior art, of the embodiment of the invention has the advantages that firstly, the dual-core CPU software function division is carried out, the design result shows that the multi-core CPU function division is reasonable, the inter-core communication data volume is effectively reduced, the real-time performance and accuracy of inter-core data after takeoff are less dependent on the inter-core data, the reliability of the system can be effectively improved, secondly, two inter-core communication modes, namely a reliable communication mode and a non-reply communication mode, are set for the inter-core communication, the former is suitable for transmission of inter-core key data, the latter is suitable for asynchronous running dual-core communication, the real-time performance of transmission is effectively improved although the communication reliability is reduced, and finally, double-cache locking mechanisms are designed aiming at an inter-core data interaction critical area, the problem of double-thread conflict is solved, the problem that data caused by double threads is not is solved, the real-time performance of the system can be effectively improved.
The method has the advantages that the reliability design is carried out aiming at the characteristics of multiple cores, the technology similar to ' dog' is designed for inter-core communication, the inter-core communication reliability is improved, the dual-core starting verification is designed to prevent unknown errors from occurring in single core starting, the dual-core operation monitoring mechanism is designed, the inter-core operation monitoring reliability design is designed, the main core monitors the secondary core operation design, and the problem of system failure under the condition of the secondary core operation errors is effectively solved.
After testing, the flight control software respectively tests the main core and the secondary core according to the dual-core function division, and the dual-core function meets the requirement. Finally, the space performance is analyzed in detail and compared with the space performance in the traditional single-core mode, and the result shows that the program space of a single core can be obviously reduced by designing the flight control software architecture according to the method under the condition of dual-core hardware, so that the use of the memory space is more reasonable, and the program obtains better space performance. The time performance is analyzed in detail and compared with the time performance in the traditional single-core mode, and the result shows that the utilization rate of a single core can be obviously reduced by designing the flight control software architecture according to the method under the condition of dual-core hardware, the occupancy rate of a dual-core CPU tends to be average, and a program obtains better time performance.
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Fig. 1 is a functional architecture diagram of dual-core flight control software according to embodiments of the present invention.
FIG. 2 is a diagram illustrating an embodiment of a dual cache mechanism for resolving multi-thread conflicts.
Fig. 3 is a data flow diagram of a monitoring mechanism for a master core to monitor the operation of a slave core in embodiments of the present invention.
Detailed Description
All of the features disclosed in this specification, or all of the steps in any method or process so disclosed, may be combined in any combination, except combinations of features and/or steps that are mutually exclusive.
Any of the features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise, i.e. each feature is simply examples of a series of equivalent or similar features, unless expressly stated otherwise.
The following detailed description of embodiments of the invention refers to the accompanying drawings and examples.
The embodiment discloses embedded dual-core flight control software architecture methods based on a high-speed Linkport interface, wherein an unmanned aerial vehicle dual-core flight control system adopts two chips with dual-precision floating point capability based on DSP6713B kernel, and dual CPU data exchange is realized by using the high-speed Linkport interface.
Specifically, the embedded dual-core flight control software architecture method based on the high-speed Linkport interface comprises the following steps:
step , dual-core flight control software task division design
The traditional single-core flight control software framework mainly operates in a single CPU and communicates with each subsystem by adopting a communication protocol determined by a certain hardware interface , the subsystems execute corresponding actions according to the communication protocol to complete the whole function, the traditional flight control software operates on the single CPU and mainly has the functions of collecting sensor data in a strict control period, resolving a control rule to form a control quantity, completing control quantity transmission through each subsystem communication protocol, and finally completing servo mechanism control through self control of each subsystem resolving communication protocol content.
The task division method can effectively solve the performance problem of a single core, improves the time performance and the space performance of the system, and quantifies the improved time performance and the space performance through the performance test.
As shown in fig. 1, it can be seen from fig. 1 that the master core mainly completes slave core integrated navigation data, control rule calculation, steering engine control rule calculation, and the like, and the slave core mainly completes IMU data, GPS data acquisition, integrated navigation calculation, and outputs navigation data to the master core; this functional division has the following advantages:
1) the combined navigation module with relatively independent functions is placed into the slave core, so that the running time of the main core program is effectively shortened, and the occupied space of the main core program is reduced.
2) The transmission data among the cores is relatively small, and the data volume of communication among the cores is effectively reduced.
3) The dual cores operate asynchronously, synchronous operation is not needed, and the use difficulty is reduced.
4) The combined navigation data is transmitted to the main core, and the system can also operate if communication occasionally has an error condition, so that the reliability of system operation is effectively improved.
Step two, designing a dual-core communication mechanism of flight control software
dual-core communication mechanisms based on interrupt signals and high-speed Linkport interfaces are designed in the embodiment, and meanwhile, two communication protocols, namely a reliable communication protocol and a non-reply communication protocol, are designed for Linkport, wherein the reliable communication protocol guarantees the reliability of data by full-text reply and data verification of transmitted data, so that the real-time performance of data transmission is reduced, and the non-reply communication protocol does not need reliable transmission but has high real-time performance, so that various communication scenes under the dual-core architecture are met.
Specifically, dual-core communication is carried out through a high-speed Linkport interface and is matched with data transmission interruption for communication, when a main core needs to transmit data to a slave core, the main core encapsulates fixed 2K data into the Linkport data interface, after transmission is completed, the slave core sends out data transmission completion interruption, after the slave core receives the interruption, the data is considered to be transmitted completely, the fixed 2K data is read from the Linkport interface, and the transmission process is completed. The case of transferring data from the slave core to the master core is the same as the above case.
LVDS refers to Low Voltage Differential Signaling and is an on-line transmission mode with Low power consumption, Low noise, Low Voltage and high speed, for standard I/O signals, data access depends on actual Voltage values, the Voltage values are influenced by the length of a transmission line (due to the resistance of the transmission line and Voltage drop), and the transmission of the LVDS only depends on the difference value of the positive end and the negative end of the transmission line and can effectively filter out common mode noise, so that the long-distance high-speed transmission can be realized.
The inter-core communication mainly completes the transmission of an integrated navigation initial coordinate point, integrated navigation parameter setting, GPS ephemeris, a GPS starting instruction and the like from the master core to the slave core; the slave core sends a combined navigation result, IMU and GPS data, a GPS starting state, a GPS ephemeris forwarding state and the like to the master core; the reliability and correctness of transmission must be ensured by looking at data such as GPS ephemeris data, GPS commands, combined navigation initial coordinates and the like from the communication characteristics, the requirement on real-time performance is not high, and the communication traffic is small; the combined navigation data and the like have high real-time requirement on required data, and the communication data volume is large; in order to meet the requirements, two communication protocols are designed on the basis of communication based on a Linkport interface, namely a reliable transmission communication protocol and a non-reply communication protocol; the former mainly completes data transmission of GPS ephemeris, combined navigation initial coordinate points and the like which need to ensure data correctness, and the latter mainly completes data transmission of combined navigation results which have high requirements on real-time performance.
The reliable transmission communication protocol in this embodiment is to perform data packetization on data to be sent, divide the data into data packets with fixed size of 2K, perform framing according to a frame protocol, including data types, total length of data to be transmitted, current frame count, effective length of current packet data, frame check and the like, perform frame header check judgment first after a receiver receives the data, send an error receiving instruction to request a sender to resend the data if the frame header check is wrong, send a data receiving correct instruction (including the data type, total length, frame number and CRC check code of the frame) to the receiver if the judgment is correct, start sending packet data after receiving the correct instruction, send a data request instruction (including the request data type and frame number) if the frame header check of the data received by the receiver is correct, send a data frame pointed by the request frame after the receiver receives the instruction, when all data transmission is completed, the sender requests the receiver to send a total data CRC check code, receive the CRC code and calculate the CRC code of the total data to be sent, and complete the transmission after the comparison is correct,
in the non-reply communication protocol in this embodiment, the communication data is unilaterally transmitted according to the 2K data frame format, and the receiver only determines the frame header and the checksum without waiting for another party to reply and retransmit.
Third step, flight control software dual-core data sharing mechanism
The embodiment designs double-cache semaphore mechanisms, solves the problem of access conflict under dual-core asynchronous operation, is different from the traditional semaphore mechanism, and multithreading access needs to wait for the release of a locked cache, so that the real-time performance of the system is reduced.
The process that the main core interrupts and receives the slave core data and runs the main flow to analyze the slave core data is equivalent to two threads simultaneously accessing the slave core data area, namely the problem that two threads simultaneously access the same storage area exists, the program segment of reading the slave core data from the main core and writing the slave core data into the main core is a critical area, locking access is needed, and data is prevented from being caused by the fact that multiple threads simultaneously access the critical area and the like is .
The embodiment designs double-cache locking mechanisms to solve the problem of double-thread conflict, and is different from traditional locking conflict prevention , wherein when threads operate a critical section in traditional locking, another threads wait for threads to quit accessing if accessing the critical section, and because flight control software requires real-time performance, thread waiting cannot occur, so the double-cache mechanism is designed, A, B double caches, a locking flag bit and an access flag bit are set, when the threads access the critical section, whether locking is performed is judged, if the locking state indicates that a main function is reading the content of the critical section, another areas of the access flag bit are written, and the access flag bit is set as a mark of a just written area, when the threads are read, the threads are firstly locked, then the data indicated by the access flag bit is read and unlocked, when the threads are operated by a multithreading, another threads do not need to wait for occupying the critical section, and the schematic diagram of the double-cache mechanism for solving the conflict is shown in fig. 2.
Step four, designing dual-core reliability of flight control software
The dual-core operation design is compared with the dual-core flight control reliability design specific to the traditional single-core flight control software, the dual-core operation reliability design mainly comprises the inter-core communication reliability design, the dual-core starting reliability design, the dual-core operation reliability design and the like of the flight control software, and the reliability of a dual-core software architecture is better improved.
The which is a key problem when the dual-core controller operates mainly completes the receiving of IMU data and GPS data by the slave core, completes the integrated navigation calculation and transmits the calculation result to the master core even if the communication between the cores is carried out, so if the communication between the cores is in a problem and the master core cannot receive the integrated navigation data of the slave core, the whole control will be invalid, and how to improve the communication reliability between the cores becomes a key problem.
After entering a flight task flow, the slave core sends combined navigation data and intermediate result data to the master core at intervals for 2ms, the master core is set to interrupt and receive the slave core data, if the interrupt and the received data are received correctly, the counter is cleared by 0, meanwhile, paths of monitoring interrupt are responsible for counter accumulation, if the accumulated amount of the counter is more than the limit, the counter is set to 20ms at present, the communication fault is considered, the master core and the slave core communication interface are executed to restart the code, the inter-core communication is restarted, and through experimental verification, when errors such as forced LINKPORT interrupt stop, LINKPROT buffer overflow and the like occur, the inter-core communication problem which may occur after takeoff can be effectively solved by using the method.
The whole system needs dual-core operation, program operation starting and checking mechanisms are designed, namely after the equation sequence is electrified, another equation program needs to wait for operation, after two hands are simultaneously held by two parties, the dual-core flight program starts to operate, otherwise, the two programs do not operate, unknown errors caused by the fact that the equation sequence operates the other equation program and the equation sequence is not burnt are prevented from occurring.
, as shown in fig. 3, for the dual-core operation reliability design part, the dual-core controller flight control software program is divided into a master core and a slave core program, the master core is mainly responsible for the test binding and flight control of the flight program, the slave core mainly completes the reading of IMU and GPS data to complete the combined navigation solution, the dual-core architecture is used and the dual-core asynchronous operation is adopted, master core monitoring slave core operation monitoring mechanisms are designed herein, the master core monitors the operation heartbeat signal of the slave core for 2ms, if the heartbeat signal of the slave core cannot be received in 5 continuous periods, the slave core is considered to have abnormal operation, the master core sends a slave core restart signal to force the slave core to restart, the key data of the slave core operation is sent to the slave core after the restart, the slave core uses the key data to recover to the state before the restart, the combined navigation solution is recovered, and the whole recovery process is not more than 500 ms.
Reference throughout this specification to " embodiments," "another embodiments," "embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least embodiments generally described herein, the appearances of the same phrase in various places in the specification are not necessarily limited to but rather to embodiments, and further , when particular features, structures, or characteristics are described in connection with any embodiments, it is intended that such features, structures, or characteristics be implemented in connection with other embodiments as well as within the scope of the present invention.
Although the invention has been described herein with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More specifically, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the claims of the present disclosure. In addition to variations and modifications in the component parts and/or arrangements, other uses will also be apparent to those skilled in the art.
Claims (8)
1, embedded dual-core flight control software architecture method based on high-speed Linkport interface, characterized in that the method comprises the following steps:
step , dual-core flight control software task division
The primary core in the dual cores is used for flight control, and the secondary core is used for realizing navigation calculation;
step two, designing a dual-core communication mechanism of flight control software
Designing a reliable communication protocol and a non-reply communication protocol on the basis of Linkport interface communication;
the reliable communication protocol is that data to be sent is subjected to data subpackaging, the data is divided into data packets with the fixed size of 2K, data framing is carried out according to a frame protocol, after a receiver receives the data, frame header check judgment is carried out firstly, if frame header check is wrong, an error receiving instruction is sent to request the sender to resend the data, if the judgment is correct, a data receiving correct instruction is sent to the receiver, data package is sent after the correct instruction is received, if the frame header check of the data received by the receiver is correct, a data request instruction is sent if the frame content judgment is wrong, the receiver sends a data frame pointed by the request frame after receiving the instruction, after all data transmission is finished, the sender requests the receiver to send a total data CRC code, the sender receives the CRC code and calculates the CRC code of the total data, and after the comparison is correct, the transmission is finished;
the non-reply communication protocol is that the communication data transmits data according to a 2K data frame format, and the receiver only judges a frame header and a check sum;
third step, flight control software dual-core data sharing mechanism
Setting a double-buffer semaphore mechanism;
step four, designing dual-core reliability of flight control software
Reliable inter-core communication is guaranteed by monitoring communication faults in real time and restarting inter-core communication;
the dual-core reliable start is ensured through a program operation start calibration mechanism;
and the reliable operation of the dual cores is ensured by monitoring the operation monitoring mechanism of the slave cores through the master core.
2. The embedded dual-core flight control software architecture method based on the high-speed Linkport interface according to claim 1, wherein the step comprises the master core completing slave core integrated navigation data, control rule calculation and steering engine control rule calculation, and the slave core completing IMU data, GPS data acquisition, integrated navigation calculation and navigation data output to the master core.
3. The embedded dual-core flight control software architecture method based on the high-speed Linkport interface according to claim 1, wherein the second step comprises: the dual-core communication is carried out through a high-speed Linkport interface and is matched with data transmission interruption for communication, when a main core needs to transmit data to a slave core, the main core encapsulates fixed 2K data into the Linkport data interface, after the transmission is completed, the slave core sends out data transmission completion interruption, after the slave core receives the interruption, the data is considered to be transmitted completely, the fixed 2K data is read from the Linkport interface, and the transmission process is completed.
4. The high-speed Linkport interface-based embedded dual-core flight control software architecture method according to claim 3, wherein the slave core transmits data to the master core in the same manner as the master core transmits data to the slave core.
5. The method of claim 1, wherein the dual-cache semaphore mechanism in step three comprises A, B dual caches, a lock flag bit and an access flag bit, when a write thread accesses a critical area, determining whether to lock the critical area, if the lock state indicates that the master function is reading the contents of the critical area, writing another areas of the access flag bit, and setting the access flag bit as a mark of the just written area, when the thread is read, firstly locking the critical area, and then reading the data indicated by the access flag bit and then unlocking the critical area.
6. The embedded dual-core flight control software architecture method based on the high-speed Linkport interface according to claim 1, wherein the fourth step includes that after entering the flight task process, the slave core sends the combined navigation data and the intermediate result data to the master core at intervals, the master core is set to interrupt the reception of the slave core data, if the reception of the interrupt and the reception of the data are correct, the counter is cleared, meanwhile, paths of monitoring interrupt are in charge of the accumulation of the counter, if the accumulation amount of the counter is larger than the limit, the communication fault is considered, the restart code of the communication interfaces of the master core and the slave core is executed, the inter-core communication is restarted, and the inter-core reliable communication is guaranteed.
7. The embedded dual-core flight control software architecture method based on the high-speed Linkport interface according to claim 1, wherein the fourth step includes waiting for another program to run after program is powered on, and after both sides pass through simultaneously, the dual-core flight program starts to run, otherwise, both programs do not run, thereby ensuring dual-core reliable start.
8. The embedded dual-core flight control software architecture method based on the high-speed Linkport interface according to claim 1, wherein the fourth step comprises: the method comprises the steps that a master core monitors a preset running signal of a slave core in preset time, if the preset signal of the slave core cannot be received in 5 continuous periods, the slave core is considered to be abnormal in running, the master core sends a slave core restarting signal to force the slave core to restart, prestored data running by the slave core is sent to the slave core after restarting, the slave core recovers to a state before restarting by using the prestored data, combined navigation resolving is recovered, and reliable running of dual cores is guaranteed.
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| CN107463126A (en) * | 2017-07-25 | 2017-12-12 | 四川航天系统工程研究所 | Unmanned plane double-core control system and digital independent and wiring method |
| US10353767B2 (en) * | 2017-09-14 | 2019-07-16 | Bae Systems Controls Inc. | Use of multicore processor to mitigate common mode computing faults |
| CN109697767B (en) * | 2018-12-29 | 2021-11-19 | 华为技术有限公司 | Data processing method, related device and computer storage medium |
| CN110262440B (en) * | 2019-07-26 | 2021-05-04 | 中车青岛四方车辆研究所有限公司 | Data monitoring and collecting system and method for rail vehicle traction system |
| CN110986929B (en) * | 2019-11-25 | 2023-05-02 | 四川航天系统工程研究所 | Software implementation method of flight control scheme with asynchronous navigation and control period |
| CN111158796B (en) * | 2019-12-25 | 2023-05-23 | 中国航空工业集团公司西安飞机设计研究所 | Data processing method of hydraulic control software |
| CN111427821B (en) * | 2020-03-19 | 2021-10-01 | 深圳震有科技股份有限公司 | Method, system and storage medium for sharing SPI interface by dual-core AMP system |
| CN111323839B (en) * | 2020-04-07 | 2023-04-07 | 中国人民解放军国防科技大学 | Embedded control system for photoelectric detection mechanism |
| CN111857980A (en) * | 2020-07-10 | 2020-10-30 | 北京星途探索科技有限公司 | Rocket flight control computing architecture implementation method under dual-core mode |
| CN112182770A (en) * | 2020-10-10 | 2021-01-05 | 中国运载火箭技术研究院 | Online iterative computation method and device, computer storage medium and electronic equipment |
| CN112199076B (en) * | 2020-10-10 | 2022-08-09 | 中国运载火箭技术研究院 | Flight control software architecture and design method thereof |
| CN112783197B (en) * | 2020-12-23 | 2024-05-28 | 湖北航天飞行器研究所 | Integrated solution method for aircraft guidance control system |
| CN114338515B (en) * | 2021-12-09 | 2023-08-22 | 中汽创智科技有限公司 | Data transmission method, device, equipment and storage medium |
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