CN112363816B - Deterministic scheduling method, system and medium for embedded multi-core operating system - Google Patents
Deterministic scheduling method, system and medium for embedded multi-core operating system Download PDFInfo
- Publication number
- CN112363816B CN112363816B CN202011347260.8A CN202011347260A CN112363816B CN 112363816 B CN112363816 B CN 112363816B CN 202011347260 A CN202011347260 A CN 202011347260A CN 112363816 B CN112363816 B CN 112363816B
- Authority
- CN
- China
- Prior art keywords
- scheduling
- current
- processor core
- event
- partition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000005192 partition Methods 0.000 claims abstract description 69
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 230000001960 triggered effect Effects 0.000 claims description 6
- 238000004590 computer program Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 2
- 230000008447 perception Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000000269 nucleophilic effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/48—Indexing scheme relating to G06F9/48
- G06F2209/483—Multiproc
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/48—Indexing scheme relating to G06F9/48
- G06F2209/484—Precedence
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/5012—Processor sets
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/5021—Priority
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
Abstract
The invention provides a deterministic scheduling method, a system and a medium for an embedded multi-core operating system, which comprise the following steps: step M1: releasing all the processor cores and synchronizing the processor cores by using a global clock; step M2: triggering preset partition scheduling, and scheduling a scheduling event in the partition scheduling according to a preset scheduling table; and after the preset time is operated, ending the current partition scheduling event, re-triggering the preset partition scheduling, and repeatedly executing the step M2 until the preset requirement is met, and ending the operation. The invention isolates the interference between the cores through the space partition during the multi-core scheduling.
Description
Technical Field
The invention relates to the technical field of multi-core processors, in particular to a deterministic scheduling method and a system of an embedded multi-core operating system, and more particularly to a safe, predictable and deterministic task scheduling scheme supporting SMP, AMP and BMP scheduling modes based on a partition architecture.
Background
The multi-core processor improves the processing performance of the equipment, brings a series of uncertain problems, directly influences the real-time performance and the reliability of the equipment, and compared with a single-core system, the multi-core parallel system has the advantages that the resource synchronization among a plurality of cores such as buses and memories and the high concurrency of tasks on different cores, so that the multi-core parallel system has higher challenges in the technology of certainty guarantee.
The operating system realizes the time-space domain isolation among the applications through the concept of partition, and achieves the purposes of fault tolerance and simplified verification; the method provides basic support of safety and reliability for the system, prevents an access control mechanism in an operating system from being tampered and bypassed, enables each safety key task to run independently, and effectively ensures independent safety of each application and each part of data through interaction of a controlled message mechanism.
From the software perspective, the multi-core processor has three operating modes, including: (1) asymmetric Multiprocessing (AMP), in which each core runs one completely independent application; (2) symmetric Multiprocessing (SMP), where an application may continue to use multiple cores simultaneously; (3) bundled Multiprocessing (BMP), like SMP, differs in that a developer may specify that a task is to be performed only on a specified core.
During multi-core scheduling initialization, a typical implementation is to associate a processor group formed by one or more processor cores with one or more applications based on a nucleophilic scheduling manner, the processor cores in such applications are not shared among the processor groups, and the new applications cannot use the processor core resources outside the current processor group. Other implementations may not associate a kernel with an application, such as defining a scheduling domain where there is no association of a processor core, and in such implementations, reservation of processor core resources (including resources reserved for future use, resources needed for application errors) is not mandatory.
Patent document CN111090506A (application number: 201911132567.3) discloses a heterogeneous multi-core scheduling method based on soft error correlation, the method at least comprising: predicting a local AVF value and running time of an application program according to a local sampling rule, and quickly obtaining the reliability characteristics of each program expressed on different core structures, wherein the program arrives at the same time and comprises a plurality of subtasks, and the number of the programs is more than or equal to the number of cores of a system; according to a relevance perception scheduling rule, calculating and comparing local relevance of programs simultaneously running on different core structures, and thus obtaining a combination with high relevance, wherein the higher the relevance among the programs is, the lower the global AVF value is; and evaluating the global reliability of the combination running on the heterogeneous multi-core processor based on the program combination obtained by the correlation perception scheduling according to a predefined global reliability evaluation index cAVF, so as to quickly obtain a soft error optimization method with high reliability and less performance loss.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a deterministic scheduling method, a system and a medium for an embedded multi-core operating system.
The deterministic scheduling method of the embedded multi-core operating system provided by the invention comprises the following steps:
step M1: releasing all the processor cores and synchronizing the processor cores by using a global clock;
step M2: triggering preset partition scheduling, and scheduling a scheduling event in the partition scheduling according to a preset scheduling table; and after the preset time is operated, ending the current partition scheduling event, re-triggering the preset partition scheduling, and repeatedly executing the step M2 until the preset requirement is met, and ending the operation.
Preferably, the step M2 includes:
step M2.1: triggering preset partition scheduling, scheduling a scheduling event in the partition scheduling according to a preset scheduling table, judging whether a current processor core is used in the current partition scheduling event, and waiting for the partition scheduling event starting at the next time synchronization point after the current partition scheduling event is ended when the current processor core is not used; when used, determining whether the processor core scheduling event is associated with one or more affinity groups;
step M2.2: when the processor core scheduling event is associated with one or more affinity groups, the task performs priority scheduling in a scheduling domain specified by the affinity groups; when the processor core scheduling event is not associated with one or more affinity groups, the current processor core is associated to a scheduling domain which can be used by all the processor cores and is not used by the affinity groups;
step M2.3: when the processor core schedules the event to be associated with one or more affinity groups, after the preset time is operated, the association with the current affinity group is removed, and the steps from M2.1 to M2.3 are repeatedly executed; and when the processor core scheduling event is not associated with one or more affinity groups, after running for a preset time, repeatedly executing the steps M2.1 to M2.3.
Preferably, said step M2.2 comprises: when the processor core scheduling event is associated with one or more affinity groups, the current processor core is associated with one or more affinity groups, and the processor cores in the affinity groups associated with the current processor core are synchronized; and the task carries out task priority scheduling in the scheduling domain allocated by the current affinity group by using the related processor cores in the current affinity group, and continuously schedules until the current affinity group is scheduled completely.
Preferably, the schedule includes SMP, AMP, and SMP hybrid AMP scheduling configurations.
The invention provides an embedded multi-core operating system deterministic scheduling system, which comprises:
module M1: releasing all the processor cores and synchronizing the processor cores by using a global clock;
module M2: triggering preset partition scheduling, and scheduling a scheduling event in the partition scheduling according to a preset scheduling table; and after the preset time is operated, ending the current partition scheduling event, re-triggering the preset partition scheduling, and repeating the execution of the triggering module M2 until the preset requirement is met, and ending the operation.
Preferably, said module M2 comprises:
module M2.1: triggering preset partition scheduling, scheduling a scheduling event in the partition scheduling according to a preset scheduling table, judging whether a current processor core is used in the current partition scheduling event, and waiting for the partition scheduling event starting at the next time synchronization point after the current partition scheduling event is ended when the current processor core is not used; when used, determining whether the processor core scheduling event is associated with one or more affinity groups;
module M2.2: when the processor core scheduling event is associated with one or more affinity groups, the task performs priority scheduling in a scheduling domain specified by the affinity groups; when the processor core scheduling event is not associated with one or more affinity groups, the current processor core is associated to a scheduling domain which can be used by all the processor cores and is not used by the affinity groups;
module M2.3: when the processor core schedules events to be associated with one or more affinity groups, after running for a preset time, the association with the current affinity group is removed, and the modules M2.1 to M2.3 are repeatedly triggered to execute; when the processor core scheduling event is not associated with one or more affinity groups, the execution of the modules M2.1 to M2.3 is repeatedly triggered after running for a preset time.
Preferably, said module M2.2 comprises: when the processor core scheduling event is associated with one or more affinity groups, the current processor core is associated with one or more affinity groups, and the processor cores in the affinity groups associated with the current processor core are synchronized; and the task carries out task priority scheduling in the scheduling domain allocated by the current affinity group by using the related processor cores in the current affinity group, and continuously schedules until the current affinity group is scheduled completely.
Preferably, the schedule includes SMP, AMP, and SMP hybrid AMP scheduling configurations.
According to the present invention, a computer-readable storage medium is provided, in which a computer program is stored, which, when being executed by a processor, carries out the steps of the method as described above.
Compared with the prior art, the invention has the following beneficial effects:
1. the method isolates the interference among the cores through the space partition during the multi-core scheduling;
2. the invention enhances the certainty and the predictability of the system through the synchronization of the time partition and the time partition;
3. the invention uses the mode of combining the affinity group and the scheduling domain, simultaneously supports the scheduling modes of SMP, AMP and BMP, and flexibly uses various scheduling modes to fully utilize the resources of the processor core.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a flow chart of a deterministic scheduling method of an embedded multi-core operating system;
FIG. 2 is a sample affinity group configuration;
FIG. 3 is a data structure and configuration of a schedule control affinity group;
FIG. 4 is an overall schedule preview diagram;
FIG. 5 is a diagram of task allocation scheduling;
FIG. 6 is a diagram of the main data structure and its dependencies.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Example 1
The deterministic scheduling method of the embedded multi-core operating system provided by the invention comprises the following steps:
step M1: releasing all the processor cores and synchronizing the processor cores by using a global clock;
step M2: triggering preset partition scheduling, and scheduling a scheduling event in the partition scheduling according to a preset scheduling table; and after the preset time is operated, ending the current partition scheduling event, re-triggering the preset partition scheduling, and repeatedly executing the step M2 until the preset requirement is met, and ending the operation.
Specifically, the step M2 includes:
step M2.1: triggering preset partition scheduling, scheduling a scheduling event in the partition scheduling according to a preset scheduling table, judging whether a current processor core is used in the current partition scheduling event, and waiting for the partition scheduling event starting at the next time synchronization point after the current partition scheduling event is ended when the current processor core is not used; when used, determining whether the processor core scheduling event is associated with one or more affinity groups;
step M2.2: when the processor core scheduling event is associated with one or more affinity groups, the task performs priority scheduling in a scheduling domain specified by the affinity groups; when the processor core scheduling event is not associated with one or more affinity groups, the current processor core is associated to a scheduling domain which can be used by all the processor cores and is not used by the affinity groups;
step M2.3: when the processor core schedules the event to be associated with one or more affinity groups, after the preset time is operated, the association with the current affinity group is removed, and the steps from M2.1 to M2.3 are repeatedly executed; and when the processor core scheduling event is not associated with one or more affinity groups, after running for a preset time, repeatedly executing the steps M2.1 to M2.3.
In particular, said step M2.2 comprises: when the processor core scheduling event is associated with one or more affinity groups, the current processor core is associated with one or more affinity groups, and the processor cores in the affinity groups associated with the current processor core are synchronized; and the task carries out task priority scheduling in the scheduling domain allocated by the current affinity group by using the related processor cores in the current affinity group, and continuously schedules until the current affinity group is scheduled completely.
Specifically, the schedule includes SMP, AMP, and SMP hybrid AMP scheduling configurations.
The deterministic scheduling system of an embedded multi-core operating system provided by the present invention, as shown in fig. 1 to 6, includes:
module M1: releasing all the processor cores and synchronizing the processor cores by using a global clock;
module M2: triggering preset partition scheduling, and scheduling a scheduling event in the partition scheduling according to a preset scheduling table; and after the preset time is operated, ending the current partition scheduling event, re-triggering the preset partition scheduling, and repeating the execution of the triggering module M2 until the preset requirement is met, and ending the operation.
Specifically, the module M2 includes:
module M2.1: triggering preset partition scheduling, scheduling a scheduling event in the partition scheduling according to a preset scheduling table, judging whether a current processor core is used in the current partition scheduling event, and waiting for the partition scheduling event starting at the next time synchronization point after the current partition scheduling event is ended when the current processor core is not used; when used, determining whether the processor core scheduling event is associated with one or more affinity groups;
module M2.2: when the processor core scheduling event is associated with one or more affinity groups, the task performs priority scheduling in a scheduling domain specified by the affinity groups; when the processor core scheduling event is not associated with one or more affinity groups, the current processor core is associated to a scheduling domain which can be used by all the processor cores and is not used by the affinity groups;
module M2.3: when the processor core schedules events to be associated with one or more affinity groups, after running for a preset time, the association with the current affinity group is removed, and the modules M2.1 to M2.3 are repeatedly triggered to execute; when the processor core scheduling event is not associated with one or more affinity groups, the execution of the modules M2.1 to M2.3 is repeatedly triggered after running for a preset time.
In particular, said module M2.2 comprises: when the processor core scheduling event is associated with one or more affinity groups, the current processor core is associated with one or more affinity groups, and the processor cores in the affinity groups associated with the current processor core are synchronized; and the task carries out task priority scheduling in the scheduling domain allocated by the current affinity group by using the related processor cores in the current affinity group, and continuously schedules until the current affinity group is scheduled completely.
Specifically, the schedule includes SMP, AMP, and SMP hybrid AMP scheduling configurations.
According to the present invention, a computer-readable storage medium is provided, in which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the method as described above.
Example 2
Example 2 is a modification of example 1
The invention belongs to multi-core processors, and particularly relates to a safe, predictable and determined task scheduling scheme supporting SMP (symmetric multi-processor), AMP (AMP) and BMP (BMP) scheduling modes based on a partition architecture. The method comprises the following steps:
step 1: initializing, predefining each data structure to be used and its dependency relationship, as shown in fig. 6, releasing all processor cores, and synchronizing each processor core by using a global clock.
Step 2: the processor core waits for the next time synchronization point partition scheduling event to complete.
And step 3: if the core is used in the current partition scheduling event, step 4 is entered, otherwise step 2 is returned.
And 4, step 4: step 5 is entered if the processor core is associated with one or more affinity groups in the next scheduled event, otherwise step 2 is returned.
And 5: a processor core is associated to an affinity group of a core, synchronizing the core with other cores in the core's associated affinity group.
Step 6: and the task utilizes the related cores in the current affinity group to carry out task priority scheduling in the scheduling domain allocated by the current affinity group, and the scheduling is continuously carried out until the scheduling of the current affinity group is completed.
And 7: the core is synchronized with other cores in the same affinity group before the next scheduled event for the core is processed.
And 8: and releasing the association with the last affinity group and returning to the step 2.
And (4) obtaining a global partition scheduling preview graph as shown in FIG. 4 by integrating the scheduling.
Three ways of scheduling tasks among cores are shown in fig. 5.
Wherein, step 2 includes the following steps:
step 2.1: according to the system scheduling configuration table (such as scheduling configuration of SMP, AMP, SMP mixed AMP, etc.), such as the affinity group configuration of fig. 2, the scheduling configuration control of fig. 3 determines whether the current processor core is used in the scheduling event, and if not, it is ended to wait for the next time synchronization point partition scheduling event to occur.
Step 2.2: is there a predefined affinity group for a processor core to schedule? If so, a predefined next affinity group is selected.
Step 2.3: if the core does not have a predefined affinity group for scheduling, then it is associated with the core that all cores are available and that the scheduling domain of the core is not currently used by another affinity group.
Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (5)
1. A deterministic scheduling method of an embedded multi-core operating system is characterized by comprising the following steps:
step M1: releasing all the processor cores and synchronizing the processor cores by using a global clock;
step M2: triggering preset partition scheduling, and scheduling a scheduling event in the partition scheduling according to a preset scheduling table; after the preset time is operated, ending the current partition scheduling event, re-triggering the preset partition scheduling, and repeatedly executing the step M2 until the preset requirement is met, and ending the operation;
the step M2 includes:
step M2.1: triggering preset partition scheduling, scheduling a scheduling event in the partition scheduling according to a preset scheduling table, judging whether a current processor core is used in the current partition scheduling event, and waiting for the partition scheduling event starting at the next time synchronization point after the current partition scheduling event is ended when the current processor core is not used; when used, determining whether the processor core scheduling event is associated with one or more affinity groups;
step M2.2: when the processor core scheduling event is associated with one or more affinity groups, the task performs priority scheduling in a scheduling domain specified by the affinity groups; when the processor core scheduling event is not associated with one or more affinity groups, the current processor core is associated to a scheduling domain which can be used by all the processor cores and is not used by the affinity groups;
step M2.3: when the processor core schedules the event to be associated with one or more affinity groups, after the preset time is operated, the association with the current affinity group is removed, and the steps from M2.1 to M2.3 are repeatedly executed; when the processor core scheduling event is not associated with one or more affinity groups, after running for a preset time, repeatedly executing the steps M2.1 to M2.3;
the schedule includes SMP, AMP, and SMP hybrid AMP scheduling configurations.
2. The embedded multi-core operating system deterministic scheduling method according to claim 1, characterized in that said step M2.2 comprises: when the processor core scheduling event is associated with one or more affinity groups, the current processor core is associated with one or more affinity groups, and the processor cores in the affinity groups associated with the current processor core are synchronized; and the task carries out task priority scheduling in the scheduling domain allocated by the current affinity group by using the related processor cores in the current affinity group, and continuously schedules until the current affinity group is scheduled completely.
3. An embedded multi-core operating system deterministic scheduling system, comprising:
module M1: releasing all the processor cores and synchronizing the processor cores by using a global clock;
module M2: triggering preset partition scheduling, and scheduling a scheduling event in the partition scheduling according to a preset scheduling table; after the preset time is operated, ending the current partition scheduling event, re-triggering the preset partition scheduling, and repeating the execution of the triggering module M2 until the preset requirement is met, and ending the operation;
the module M2 includes:
module M2.1: triggering preset partition scheduling, scheduling a scheduling event in the partition scheduling according to a preset scheduling table, judging whether a current processor core is used in the current partition scheduling event, and waiting for the partition scheduling event starting at the next time synchronization point after the current partition scheduling event is ended when the current processor core is not used; when used, determining whether the processor core scheduling event is associated with one or more affinity groups;
module M2.2: when the processor core scheduling event is associated with one or more affinity groups, the task performs priority scheduling in a scheduling domain specified by the affinity groups; when the processor core scheduling event is not associated with one or more affinity groups, the current processor core is associated to a scheduling domain which can be used by all the processor cores and is not used by the affinity groups;
module M2.3: when the processor core schedules events to be associated with one or more affinity groups, after running for a preset time, the association with the current affinity group is removed, and the modules M2.1 to M2.3 are repeatedly triggered to execute; when the scheduling event of the processor core is not associated with one or more affinity groups, the execution of the modules M2.1 to M2.3 is repeatedly triggered after the preset time is run;
the schedule includes SMP, AMP, and SMP hybrid AMP scheduling configurations.
4. The embedded multi-core operating system deterministic scheduling system according to claim 3, characterized in that said module M2.2 comprises: when the processor core scheduling event is associated with one or more affinity groups, the current processor core is associated with one or more affinity groups, and the processor cores in the affinity groups associated with the current processor core are synchronized; and the task carries out task priority scheduling in the scheduling domain allocated by the current affinity group by using the related processor cores in the current affinity group, and continuously schedules until the current affinity group is scheduled completely.
5. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011347260.8A CN112363816B (en) | 2020-11-26 | 2020-11-26 | Deterministic scheduling method, system and medium for embedded multi-core operating system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011347260.8A CN112363816B (en) | 2020-11-26 | 2020-11-26 | Deterministic scheduling method, system and medium for embedded multi-core operating system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112363816A CN112363816A (en) | 2021-02-12 |
| CN112363816B true CN112363816B (en) | 2022-08-16 |
Family
ID=74532949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011347260.8A Active CN112363816B (en) | 2020-11-26 | 2020-11-26 | Deterministic scheduling method, system and medium for embedded multi-core operating system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112363816B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104090826A (en) * | 2014-06-30 | 2014-10-08 | 中国电子科技集团公司第三十二研究所 | Task optimization deployment method based on correlation |
| CN110825506A (en) * | 2019-10-31 | 2020-02-21 | 湖南智领通信科技有限公司 | Task scheduling method and device of embedded operating system and storage medium |
| CN111625338A (en) * | 2020-05-28 | 2020-09-04 | 广东浪潮大数据研究有限公司 | Affinity rule scheduling method, device and related equipment |
| CN111796921A (en) * | 2020-06-30 | 2020-10-20 | 西安微电子技术研究所 | Embedded multi-core operating system scheduling method, scheduling device, electronic equipment and storage medium |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101706742B (en) * | 2009-11-20 | 2012-11-21 | 北京航空航天大学 | Method for dispatching I/O of asymmetry virtual machine based on multi-core dynamic partitioning |
-
2020
- 2020-11-26 CN CN202011347260.8A patent/CN112363816B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104090826A (en) * | 2014-06-30 | 2014-10-08 | 中国电子科技集团公司第三十二研究所 | Task optimization deployment method based on correlation |
| CN110825506A (en) * | 2019-10-31 | 2020-02-21 | 湖南智领通信科技有限公司 | Task scheduling method and device of embedded operating system and storage medium |
| CN111625338A (en) * | 2020-05-28 | 2020-09-04 | 广东浪潮大数据研究有限公司 | Affinity rule scheduling method, device and related equipment |
| CN111796921A (en) * | 2020-06-30 | 2020-10-20 | 西安微电子技术研究所 | Embedded multi-core operating system scheduling method, scheduling device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112363816A (en) | 2021-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Axer et al. | Response-time analysis of parallel fork-join workloads with real-time constraints | |
| Cerqueira et al. | PROSA: A case for readable mechanized schedulability analysis | |
| US20190196881A1 (en) | Deterministic parallelization through atomic task computation | |
| US20100223213A1 (en) | System and method for parallelization of machine learning computing code | |
| Davis | A review of fixed priority and EDF scheduling for hard real-time uniprocessor systems | |
| EP3151116A1 (en) | Vehicle control apparatus | |
| Thekkilakattil et al. | The global limited preemptive earliest deadline first feasibility of sporadic real-time tasks | |
| Xu | On inspection and verification of software with timing requirements | |
| Pazzaglia et al. | Optimizing the functional deployment on multicore platforms with logical execution time | |
| Negrean et al. | Response-time analysis for non-preemptive scheduling in multi-core systems with shared resources | |
| Giannopoulou et al. | DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems | |
| Thilakasiri et al. | An exact schedulability analysis for global fixed-priority scheduling of the aer task model | |
| CN112363816B (en) | Deterministic scheduling method, system and medium for embedded multi-core operating system | |
| Hasanagić et al. | Optimizing inter-core data-propagation delays in industrial embedded systems under partitioned scheduling | |
| Osborne et al. | Simultaneous multithreading applied to real time | |
| Biondi et al. | Moving from single-core to multicore: Initial findings on a fuel injection case study | |
| Chang et al. | From Java to real-time Java: A model-driven methodology with automated toolchain | |
| Ittershagen et al. | Hierarchical real-time scheduling in the multi-core era—An overview | |
| US9223637B1 (en) | Method and apparatus to advise spin and yield decisions | |
| Cai et al. | An improved formalization analysis approach to determine schedulability of global multiprocessor scheduling based on symbolic safety analysis and statistical model checking in smartphone systems | |
| Ficek et al. | Schedule design to guarantee freedom of interference in mixed criticality systems | |
| Nhat-Hoa et al. | Sspinja: Facilitating schedulers in model checking | |
| Li et al. | Reducing worst case reaction time of synchronous programs on chip-multiprocessors with application-specific TDMA scheduling | |
| Serrano | A time-predictable parallel programing model for real-time systems | |
| JP2017076156A (en) | Parallelization method, parallelization tool, and on-vehicle device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |