CN112199045A - Storage device and data operation method - Google Patents
Storage device and data operation method Download PDFInfo
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- CN112199045A CN112199045A CN202011083896.6A CN202011083896A CN112199045A CN 112199045 A CN112199045 A CN 112199045A CN 202011083896 A CN202011083896 A CN 202011083896A CN 112199045 A CN112199045 A CN 112199045A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a storage device, which comprises a first memory and a second memory, wherein the first memory is arranged in the second memory and has a higher writing speed than the second memory; the second memory is provided with a special storage area and is a nonvolatile memory; the second memory also has a controller for writing the received data into the first memory in a quick-access manner when the programming program is running, and writing the data into the special memory area when the power abnormal event of the storage device is detected, so that the data stored when the programming program in the storage device runs can be stored into the nonvolatile memory area when the power abnormal event of the storage device occurs, and the programming program in the storage device can be continued after the power-on reset of the storage device is completed.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a memory device and a data operating method.
Background
In enterprise solid state storage devices, the system uses super-capacitors or battery backups to prevent data loss from sudden power failure events. As the system caches data, the amount of data to be cached is increasing, and the cost for preventing data loss is also increasing.
However, in the storage device in the prior art, when a power abnormal event occurs, data stored during the operation of the programming program in the storage device is easily lost, and then, after the storage device is powered on and reset, the programming program cannot be continued due to the loss of the data.
Disclosure of Invention
The invention provides a storage device and a data operation method, which effectively prevent the problem that data stored when a programming program runs is easy to lose when a power abnormal event occurs in the storage device.
In order to solve the above problem, the present invention provides a storage apparatus including a first memory and a second memory, wherein:
the first memory is arranged in the second memory and used for storing data when a programming program runs, and the first memory has a faster writing speed than the second memory;
the second memory is provided with a special storage area which is used for saving data written into the first memory when the programming program runs when a power abnormal event occurs, and the second memory is a nonvolatile memory;
the second memory also has a controller for writing the received data cache to the first memory when the programming program is running; and writing the data into the special storage area when the power abnormal event of the storage device is detected.
Further preferably, the controller is further configured to write back the data stored in the special storage area to the first memory when detecting that the storage device is powered on and reset.
Further preferably, the first memory is a static random access memory, and the second memory is a NAND flash memory.
Further preferably, the data includes a program address of a program.
Further preferably, the controller is further configured to suspend the programming program according to a special control instruction and save the programming address when the power abnormality event is detected in the storage device.
Further preferably, the second memory further has a general memory area, and the controller is further configured to write the data into the general memory area after the controller writes the received data cache into the first memory.
Further preferably, the general memory area is used for multi-bit storage, and the special memory area is a memory area formed by single-bit memory cells.
Further preferably, when the data stored in the special memory area is written back to the first memory, the controller is further configured to search for a last page in the special memory area for storing the data, and write the data on the last page back to the first memory.
Further preferably, the controller is further configured to resume running the programming program according to the data written back to the first memory after the power-on reset is completed.
Further preferably, the storage device further includes an external controller having a first interface and a second interface, the external controller is electrically connected to an external host through the first interface and is electrically connected to the second memory through the second interface, and the external controller is configured to correct data of the programming program when the programming program is running.
Further preferably, the storage device further comprises a storage capacitor for supplying emergency power to the storage device when the power abnormality occurs.
In another aspect, the present invention further provides a data operation method applied to a storage device, where the storage device includes a first memory and a second memory, and the second memory is a nonvolatile memory, the first memory has a faster writing speed than the second memory, and the data operation method includes:
a general writing step, writing the data cache received by the program during operation into the first memory;
a first detection step of detecting that the storage device is power-abnormal;
and a power-off writing step, namely writing the data stored in the first memory when the programming program runs into a special storage area of the second memory.
Further preferably, after the power-off writing step, the method further includes:
a second detection step of detecting that the storage device starts power-on reset;
and a power-on writing step, namely writing the data stored in the special storage area back to the first memory.
Further preferably, the first memory is a static random access memory, and the second memory is a NAND flash memory.
Further preferably, after the first detecting step, the method further includes:
a receiving step of receiving a special control instruction;
a pause step of pausing the programming program according to a special control instruction;
and a saving step of saving the programming address of the programming program to the special memory area.
Further preferably, the step of writing by re-electrifying specifically includes:
a searching step, namely searching the last page used for storing the data in the special storage area;
and writing the data on the last page back to the first memory.
Further preferably, after the step of writing by means of the multiple current, the method further includes:
and a restoring step of restoring the program according to the data written back to the first memory.
Further preferably, the second memory further has a general storage area, and after the general writing step, the second memory further includes:
and writing the data into the general storage area.
The invention has the beneficial effects that: the invention provides a storage device, which comprises a first memory and a second memory, wherein the first memory is arranged in the second memory and has a higher writing speed than the second memory; the second memory is provided with a special storage area and is a nonvolatile memory; the second memory also has a controller for writing the received data into the first memory in a quick-access manner when the programming program is running, and writing the data into the special memory area when the power abnormal event of the storage device is detected, so that the data stored when the programming program in the storage device runs can be stored into the nonvolatile memory area when the power abnormal event of the storage device occurs, and the programming program in the storage device can be continued after the power-on reset of the storage device is completed.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments according to the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a memory device according to an embodiment of the present invention.
Fig. 2 is another schematic structural diagram of a memory device according to an embodiment of the invention.
FIG. 3 is a first flowchart of a data manipulation method according to an embodiment of the present invention.
FIG. 4 is a second flowchart of a data manipulation method according to an embodiment of the present invention.
FIG. 5 is a third flowchart of a data manipulation method according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention is used for solving the problem that data stored when a programming program runs is easy to lose in a storage device in the prior art when a power abnormal event occurs.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a memory device 100 according to an embodiment of the invention, and fig. 1 shows components and relative positions of the components according to the embodiment of the invention.
As shown in fig. 1, the storage apparatus 100 includes a first memory 110 and a second memory 120, wherein:
the first memory 110 is disposed in the second memory 120 for storing data during the operation of the programming program, and the first memory 110 has a faster writing speed than the second memory 120;
the second memory 120 has a special storage area 121, the special storage area 121 is used for saving data written into the first memory 110 when a programming program runs when a power abnormal event occurs, and the second memory 120 is a non-volatile memory;
the second memory 120 further has a controller 122, the controller 122 is used for writing the received data cache into the first memory 110 when the programming program is running; upon detecting a power abnormality event of the storage apparatus 100, data is written into the special storage area 121.
Specifically, the controller 122 is further configured to write back the data stored in the special storage area 121 to the first memory 110 when detecting that the memory device 100 is power-on reset.
Specifically, the first memory 110 is disposed in a die of the second memory 120 by way of on-chip integration, and the first memory 110 and the second memory 120 are electrically connected by way of on-chip integration, which can effectively reduce the volume of the memory device 100.
Further, since the special storage area 121 of the second memory 120 is used for saving the data written in the first memory 110 during the operation of the programming program when the power abnormality occurs in the storage apparatus 100, so that the storage apparatus 100 can retrieve the data and continue to operate the programming program after the subsequent power-on reset is completed, the second memory 120 should be a non-volatile memory, that is, a memory in which the saved data is not lost during the occurrence of the power abnormality. For example, the second memory 120 may be a NAND Flash memory, i.e., a NAND Flash. Also, because the first Memory 110 has a faster writing speed than the second Memory 120, so that the program can run faster, the first Memory 110 may be a Static Random-Access Memory (SRAM).
Further, the data of the program during operation includes a program address of the program, when the power abnormality of the memory device 100 is detected, the controller 122 suspends the program according to the special control instruction and stores the program address, and then, after the power-on reset of the memory device 100 is completed, the controller 122 resumes the operation of the program according to the data (including the program address) written back to the first memory 110.
Specifically, the controller 122 writes the data stored in the special memory area 121 back to the first memory 110 by searching the last page of the special memory area 121 for storing the data and writing the data on the last page back to the first memory 110.
Referring to fig. 2, fig. 2 is another schematic structural diagram of the memory device 100 according to the embodiment of the invention, and fig. 2 shows components and relative positions of the components according to the embodiment of the invention.
As shown in fig. 2, the second memory 120 further has a general memory area 123, and after the controller 122 writes the received data cache into the first memory 110, the controller 122 writes the data cache into the general memory area 123.
Specifically, the general memory area 123 is configured to perform Multi-bit storage, that is, each memory Cell on the general memory area 123 may store Multi-bit data, and specifically may include, but is not limited to, MLC (Multi-Level Cell), TLC (ternary-Level Cell), QLC (Quad-Level Cell), etc., taking TLC as an example, one memory Cell may store 3-bit data, and each memory Cell may have 8 different storage states. The special memory area 121 is a memory area formed by Single-Level cells (SLC), each memory Cell in the special memory area 121 can only store 1bit of data, and each memory Cell can have 2 different memory states.
Referring to fig. 2, the memory device 100 further includes an external controller 130 and a storage capacitor 140, wherein:
the external controller 130 has a first interface 131 and a second interface 132, the external controller 130 is electrically connected to the external host 200 through the first interface 131, and is electrically connected to the second memory 120 through the second interface 132, the external controller 130 is used for performing data correction on the programming program when the programming program runs;
the storage capacitor 140 is used for emergency power supply of the storage device 100 when an abnormal power event occurs, and further, the storage capacitor 140 may be an Electrochemical capacitor (Electrochemical Capacitors), which is a power source with special performance between a conventional capacitor and a battery, and has the outstanding advantages of high power density, short charging and discharging time, long cycle life and wide working temperature range.
Different from the prior art, the present invention provides a storage apparatus 100, comprising a first memory 110 and a second memory 120, wherein the first memory 110 is disposed in the second memory 120, and the first memory 110 has a faster writing speed than the second memory 120; the second memory 120 has a special storage area 121, and the second memory 120 is a nonvolatile memory; the second memory 120 further has a controller 122, the controller 122 is configured to write the received data cache into the first memory 110 during the operation of the programming program, and write the data into the special storage area 121 when the power abnormality of the storage device 100 is detected, so that the data stored during the operation of the programming program in the storage device 100 is stored into the non-volatile storage area when the power abnormality of the storage device 100 occurs, and the programming program in the storage device 100 can continue after the power-on reset of the storage device 100 is completed.
Referring to fig. 3, fig. 3 is a first flowchart of a data operation method according to an embodiment of the invention, the data operation method is applied to a memory device 100, the memory device 100 includes a first memory 110 and a second memory 120, the second memory 120 is a non-volatile memory, the first memory 110 has a faster write speed than the second memory 120, and the specific flow of the data operation method may be as follows:
a general writing step S1O1, writing the data cache received when the programming program runs into a first memory;
a first detection step S1O2, detecting that the power of the storage device is abnormal;
and a power-off writing step S1O3, writing the data saved in the first memory when the programming program runs into a special storage area of the second memory.
Further, referring to fig. 4, fig. 4 is a second flowchart of the data operation method according to the embodiment of the present invention, as shown in fig. 4, after the step S1O3 of writing power off, the method further includes:
a second detection step S1O4, detecting that the storage device starts power-on reset;
and a power-on writing step S1O5, writing the data stored in the special storage area back to the first memory.
It is easy to understand that, since the data saved during the operation of the programming program in the memory device 100 is saved to a non-volatile memory area, i.e. the special memory area 121 of the second memory 120, when the power-on reset of the memory device 100 is completed, the programming program in the memory device 100 can continue. For example, the second memory 120 may be a NAND Flash memory, that is, a NAND Flash, in which data stored in the NAND Flash is not lost when a power abnormality occurs.
Further, in order to enable the program to run faster, the first Memory 110 should have a faster writing speed than the second Memory 120, and when the second Memory 120 is a NAND Flash, the first Memory 110 may be a Static Random-Access Memory (SRAM).
Referring to fig. 5, fig. 5 is a third flow chart of the data operation method according to the embodiment of the invention, and as shown in fig. 5, after the first detecting step S1O2, the method further includes:
a receiving step S1O6, receiving a special control instruction;
a pause step S1O7, pausing the programming program according to the special control instruction;
saving step s1o8. save the programming address of the programming program to the special storage area.
It is easily understood that the data of the program during the operation includes the programming address of the program, and because it is ensured that the program in the memory device 100 can continue after the memory device 100 completes the power-on reset, the programming address of the program needs to be saved, specifically, needs to be saved in the special storage area 121 of the second memory 120, where the second memory 120 is a non-volatile memory, and then, in the power-on write step S1O5, the programming address is written back to the first memory 110, and the memory device 100 can resume the operation of the program according to the programming address written back to the first memory 110.
Referring to fig. 5, the step S1O5 of electrical reset writing includes:
a searching step S1O51, searching the last page used for storing data in the special storage area;
write step s1o52. write the data on the last page back to the first memory.
When performing the power-on-reset writing, the memory device 100 searches the last page of the special memory area 121 for storing data, writes the data on the last page back to the first memory 110, and writes the data stored in the special memory area 121 back to the first memory 110.
With reference to fig. 5, after the step S1O5 of electrical reset writing, the method further includes:
a restoring step s1o9. the program is restored to run according to the data written back to the first memory.
With continuing reference to FIG. 5, the second memory 120 further has a general storage area 123, and after the general writing step S1O1, further includes:
write general memory step s110. write data to general memory.
It should be noted that the general memory area 123 may perform Multi-bit storage, that is, each memory Cell on the general memory area 123 may store Multi-bit data, and specifically may include, but is not limited to, MLC (Multi-Level Cell), TLC (ternary-Level Cell), QLC (Quad-Level Cell), etc., taking TLC as an example, one memory Cell may store 3-bit data, and each memory Cell may have 8 different storage states. The special memory area 121 is a memory area formed by Single-Level cells (SLC), each memory Cell in the special memory area 121 can only store 1bit of data, and each memory Cell can have 2 different memory states.
Different from the prior art, the present invention provides a data operation method applied to a storage device 100, where the storage device 100 includes a first memory 110 and a second memory 120, and the second memory 120 is a nonvolatile memory, the first memory 110 has a faster writing speed than the second memory 120, and the data operation method includes: the data cache received during the operation of the programming program is written into the first memory 110, and when the power abnormality of the storage device 100 is detected, the data stored in the first memory 110 during the operation of the programming program is written into the special storage area 121 of the second memory 120, so that when the power abnormality occurs in the storage device 100, the data stored during the operation of the programming program in the storage device 100 is stored into the nonvolatile storage area, and when the power-on reset of the storage device 100 is completed, the programming program in the storage device 100 can continue.
In addition to the above embodiments, the present invention may have other embodiments. All technical solutions formed by using equivalents or equivalent substitutions fall within the protection scope of the claims of the present invention.
In summary, although the preferred embodiments of the present invention have been described above, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (18)
1. A memory device, comprising a first memory and a second memory, wherein:
the first memory is arranged in the second memory and used for storing data when a programming program runs, and the first memory has a faster writing speed than the second memory;
the second memory is provided with a special storage area which is used for saving data written into the first memory when the programming program runs when a power abnormal event occurs, and the second memory is a nonvolatile memory;
the second memory also has a controller for writing the received data cache to the first memory when the programming program is running; and writing the data into the special storage area when the power abnormal event of the storage device is detected.
2. The memory device according to claim 1, wherein the controller is further configured to write back the data stored in the special memory area to the first memory when detecting that the memory device is power-on reset.
3. The memory device according to claim 1, wherein the first memory is a static random access memory and the second memory is a NAND flash memory.
4. The memory device of claim 1, wherein the data comprises a program address of a programming program.
5. The storage device of claim 4, wherein the controller is further configured to suspend the programming procedure according to a special control instruction and save the programming address when the power abnormality event of the storage device is detected.
6. The storage device of claim 1, wherein the second memory further has a general storage area, and the controller is further configured to write the data into the general storage area after the controller writes the received data cache into the first memory.
7. The memory device according to claim 6, wherein the general memory area is used for multi-bit storage, and the special memory area is a memory area composed of single-bit memory cells.
8. The memory device according to claim 1, wherein when the data stored in the special memory area is written back to the first memory, the controller is further configured to search a last page of the special memory area for storing the data, and write the data on the last page back to the first memory.
9. The memory device according to claim 1, wherein the controller is further configured to resume running the programming program according to the data written back to the first memory after the power-on reset is completed.
10. The memory device according to claim 1, further comprising an external controller having a first interface and a second interface, the external controller being electrically connected to an external host through the first interface and electrically connected to the second memory through the second interface, the external controller being configured to perform data correction on the programming program when the programming program is running.
11. The storage device of claim 1, further comprising a storage capacitor for emergency powering of the storage device in the event of the power anomaly.
12. A data operation method is applied to a storage device, the storage device comprises a first memory and a second memory, the second memory is a nonvolatile memory, the first memory has a faster writing speed than the second memory, and the data operation method comprises the following steps:
a general writing step, writing the data cache received by the program during operation into the first memory;
a first detection step of detecting that the storage device is power-abnormal;
and a power-off writing step, namely writing the data stored in the first memory when the programming program runs into a special storage area of the second memory.
13. The data manipulation method of claim 12, further comprising, after the step of writing to power down:
a second detection step of detecting that the storage device starts power-on reset;
and a power-on writing step, namely writing the data stored in the special storage area back to the first memory.
14. The data operation method of claim 12, wherein the first memory is a static random access memory and the second memory is a NAND flash memory.
15. The data manipulation method of claim 12, further comprising, after the first detecting step:
a receiving step of receiving a special control instruction;
a pause step of pausing the programming program according to a special control instruction;
and a saving step of saving the programming address of the programming program to the special memory area.
16. The data manipulation method of claim 12, wherein the step of complex electrical writing specifically comprises:
a searching step, namely searching the last page used for storing the data in the special storage area;
and writing the data on the last page back to the first memory.
17. The data manipulation method of claim 12, further comprising, after the step of complex electrical writing:
and a restoring step of restoring the program according to the data written back to the first memory.
18. The data manipulation method of claim 12 wherein the second memory further has a general storage area, and further comprising, after the general writing step:
and writing the data into the general storage area.
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| CN202011083896.6A CN112199045A (en) | 2020-10-12 | 2020-10-12 | Storage device and data operation method |
| CN202210472876.0A CN114895847A (en) | 2020-10-12 | 2020-10-12 | Nonvolatile memory, storage device, and method of operating nonvolatile memory |
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| CN202011083896.6A CN112199045A (en) | 2020-10-12 | 2020-10-12 | Storage device and data operation method |
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