CN112198471A - Real-time state detection device of efficient test system - Google Patents
Real-time state detection device of efficient test system Download PDFInfo
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- CN112198471A CN112198471A CN202010957410.0A CN202010957410A CN112198471A CN 112198471 A CN112198471 A CN 112198471A CN 202010957410 A CN202010957410 A CN 202010957410A CN 112198471 A CN112198471 A CN 112198471A
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Abstract
The invention discloses a real-time state detection device of an efficient test system, which relates to the technical field of semiconductor test and comprises a comparator L1, a comparator L2, a buffer Q1, a buffer Q2, an AND gate U1, an AND gate U2, an AND gate U3, an AND gate U4, an AND gate U5, an AND gate U6, a trigger T1, a trigger T2 and a trigger T3; the invention is used for detecting the running state of the test system, only reading the system level state flag bit once to judge whether the system function is normal or not in each detection, and reading the lower level state flag bit if the system function is abnormal, thereby avoiding time waste caused by reading all the state bits each time; the state recognition can be accurately and rapidly carried out, the protection function of the response system is triggered, and the state recognition code is generated through the read state bit and is used as the basis of system diagnosis; the state detection module has an enabling preset function and is used for debugging and overhauling the test system in the later period.
Description
Technical Field
The invention relates to the technical field of semiconductor testing, in particular to a real-time state detection device of an efficient testing system.
Background
The existing test system state detection circuit can only realize simple state monitoring of a power supply, temperature and the like, and cannot detect complex states. The detection coverage is insufficient, so that the test system can work with diseases, system faults or the tested device has misdetection risks, the good product is detected into a defective product, the defective product is detected into a good product, and if the faults can not be found in time, unnecessary loss can be caused when the mass production test of a test factory is applied.
In addition, the existing state detection mode usually adopts a polling sampling mode to perform state detection, the process is to collect the actual state of one parameter to perform comparison and judgment, if the judgment is normal, the next parameter state is collected until the abnormal state is detected to trigger interruption, when the number of state parameters or board cards is large, the total state collection time is very long, in order to reduce the false detection risk caused by system faults, the sampling detection time interval of function detection is reduced as much as possible in the actual test process, the total test time is inevitably increased, the test efficiency of the system is seriously influenced, and the test cost is increased.
Disclosure of Invention
The invention aims to solve the technical problem of providing a real-time state detection device of an efficient test system aiming at the problems of insufficient detection coverage and low detection efficiency in the background technology.
The invention adopts the following technical scheme for solving the technical problems:
a real-time state detection device of an efficient test system comprises a comparator L1, a comparator L2, a buffer Q1, a buffer Q2, an AND gate U1, an AND gate U2, an AND gate U3, an AND gate U4, an AND gate U5, an AND gate U6, a trigger T1, a trigger T2, a trigger T3 and a trigger C,
Wherein the content of the first and second substances,
the non-inverting input end of the comparator L1 is connected with VCH;
the inverting input end of the comparator L2 is connected with VCL;
the Monitor1 is respectively connected to the inverting input terminal of the comparator L1 and the non-inverting input terminal of the comparator L2;
the output end of the comparator L1 is connected with the input end of the buffer Q1;
the output end of the comparator L2 is connected with the input end of the buffer Q2;
the output end of the buffer Q1 is connected with the 0 port of the AND gate U1;
the output end of the buffer Q2 is connected with the 1 port of the AND gate U2;
the output end of the AND gate is connected with the S end of the trigger T1;
the S end of the trigger T2 is connected into a Monitor 2;
the Q end of the trigger T1 is connected with the 0 port of the AND gate U2;
the Q end of the trigger T2 is connected with the 1 port of the AND gate U2;
the 0 port of the AND gate U3 is connected with a Monitor n-1;
a port 1 of the AND gate U3 is accessed to a Monitor n;
the output end of the AND gate U2 is connected with the 0 port of the AND gate U4;
the output end of the AND gate U3 is connected with the 1 port of the AND gate U4;
the output end of the AND gate U4 is connected with the 0 port of the AND gate U6;
the Q end of the trigger T3 accesses an interrupt response;
the output of the and gate U6 is connected to the S terminal of the flip-flop T3 and to the computer via a data bus.
As a further preferred scheme of the real-time state detection device of the high-efficiency test system, the device comprises a detection state parameter setting module, a state parameter database module, a test operation module, a system state detection module, a system state bit judgment module, a board card state bit judgment module, a unit state bit judgment module, a function level state identification and interrupt response module, a state parameter display module and an AD sampling circuit,
wherein the content of the first and second substances,
the detection state parameter setting module is used for setting parameters and design results,
the state parameter database module is used for storing parameters and design results,
the test run module is used for mass production testing,
the system state detection module is used for reading the system level state data bit in real time
The system status bit judging module is used for judging the system data bit,
the board card status bit judging module is used for judging the data bit of the board card,
the unit state bit judging module is used for judging unit data bits,
the function level state recognition and interrupt response module is used for starting an interrupt response mechanism and a state identification bit recognition mechanism when the state identification bit is read to be abnormal,
the state parameter display module is used for displaying the detailed information of the abnormal state parameters,
the detection state parameter setting module is used for setting an upper limit level, a lower limit level, an initial state bit and an enabling bit for judging whether the monitoring function is started or not,
the AD sampling circuit is used for reading the actual value of the state parameter.
As a further preferred scheme of the real-time state detection device of the high-efficiency test system, the AD sampling circuit comprises a buffer L, an operational amplifier U, an analog-digital converter J and a data bus;
wherein the content of the first and second substances,
the input end of the buffer L is connected with a Monitor, and the Monitor represents a monitoring point;
the output end of the buffer L is connected with the non-inverting input end of the operational amplifier U;
the output end of the operational amplifier is connected with a Vin port of the analog/digital converter J;
b of A/D converter J1To B8The pins are all connected to the data bus;
the data bus is connected to the computer.
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
1. the invention has the advantages of easy use and good portability, and the detection state parameters adopt a database format, thereby facilitating the parameter function increase and decrease setting and version update management;
2. the invention has high detection efficiency, the system only reads the state bit data of the system level in the running process of the system, the service time is very short, and the influence on the test time is reduced;
3. the fault positioning method and the fault positioning system have high fault positioning precision, only when the system identifies the abnormal state bit, the system can trigger an interrupt mechanism, identify the state bit of the fault board card according to the read system-level state bit, further read the board-level state bit to identify the state bit of the fault functional unit, and finally read the state parameter of the functional unit module to identify and judge the fault part, thereby realizing the fault reporting precision positioning capability.
Drawings
FIG. 1 is a block diagram of a state sampling latch module of the present invention;
FIG. 2 is a process control diagram of the present invention;
FIG. 3 is a schematic diagram of the structure of the present invention;
fig. 4 is an AD sampling circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, a real-time status detection device for an efficient test system is characterized in that: comprises a comparator L1, a comparator L2, a buffer Q1, a buffer Q2, an AND gate U1, an AND gate U2, an AND gate U3, an AND gate U4, an AND gate U5, an AND gate U6, a trigger T1, a trigger T2, a trigger T3, a trigger Q1,
Wherein the content of the first and second substances,
the non-inverting input end of the comparator L1 is connected with VCH;
the inverting input end of the comparator L2 is connected with VCL;
the Monitor1 is respectively connected to the inverting input terminal of the comparator L1 and the non-inverting input terminal of the comparator L2;
the output end of the comparator L1 is connected with the input end of the buffer Q1;
the output end of the comparator L2 is connected with the input end of the buffer Q2;
the output end of the buffer Q1 is connected with the 0 port of the AND gate U1;
the output end of the buffer Q2 is connected with the 1 port of the AND gate U2;
the output end of the AND gate is connected with the S end of the trigger T1;
the S end of the trigger T2 is connected into a Monitor 2;
the Q end of the trigger T1 is connected with the 0 port of the AND gate U2;
the Q end of the trigger T2 is connected with the 1 port of the AND gate U2;
the 0 port of the AND gate U3 is connected with a Monitor n-1;
a port 1 of the AND gate U3 is accessed to a Monitor n;
the output end of the AND gate U2 is connected with the 0 port of the AND gate U4;
the output end of the AND gate U3 is connected with the 1 port of the AND gate U4;
the output end of the AND gate U4 is connected with the 0 port of the AND gate U6;
the Q end of the trigger T3 accesses an interrupt response;
the output of the and gate U6 is connected to the S terminal of the flip-flop T3 and to the computer via a data bus.
As shown in FIG. 2, a real-time status detecting device for high-efficiency testing system comprises a detecting status parameter setting module, a status parameter database module, a testing operation module, a system status detecting module, a system status bit judging module, a board status bit judging module, a unit status bit judging module, a function level status recognizing and interrupt response module, a status parameter display module, and an AD sampling circuit,
wherein the content of the first and second substances,
the detection state parameter setting module is used for setting parameters and design results,
the state parameter database module is used for storing parameters and design results,
the test run module is used for mass production testing,
the system state detection module is used for reading the system level state data bits in real time,
the system status bit judging module is used for judging the system data bit,
the board card status bit judging module is used for judging the data bit of the board card,
the unit state bit judging module is used for judging unit data bits,
the function level state recognition and interrupt response module is used for starting an interrupt response mechanism and a state identification bit recognition mechanism when the state identification bit is read to be abnormal,
the state parameter display module is used for displaying the detailed information of the abnormal state parameters,
the detection state parameter setting module is used for setting an upper limit level, a lower limit level, an initial state bit and an enabling bit for judging whether the monitoring function is started or not,
the AD sampling circuit is used for reading the actual value of the state parameter.
The test system performs initial setup via a state parameter setup software interface before initiating the test,
the parameter design result after setting and saving is updated to the state parameter database,
the user then initiates the test run software to begin the production test,
in the process of mass production test, each hardware function module of the system can acquire and latch the status bit of the function module in real time, the status bits of the function modules are combined into board card status bits, and then the board card status bits are combined into system status bits,
as shown in fig. 1, each state parameter is converted into a state bit by a detection sampling circuit, and then latched by a state register in the FPGA, and finally collected into a group of 16 or 32-bit system state bit data;
the system level state detection module reads the data bits of the system level state in real time, judges the data bits according to the read data bits of the system state,
all 1 bits are normal, one 0 bit is abnormal,
if the state is normal, continuing the next test;
if the system level status flag bit is read abnormally, the system will start the interrupt response mechanism and the status flag bit recognition mechanism.
Finally, the detailed information testing system of the novel system abnormal state parameters can be popped up in the software interface to read the system state bits in real time according to the preset detection interval time,
as shown in fig. 3, the system level status flag bit is read first, the read abnormal data bit determines the corresponding board card according to the bit sequence of the 0 value,
and reading the state data bit of the fault board card, judging the corresponding fault functional unit module according to the 0 value position in the state data bit and the functional module code in the board, and finally reading the actual value of the state parameter through an AD sampling circuit real-time acquisition circuit.
The user can remove the system fault according to the error prompt and then can continue working.
As shown in fig. 4, the AD sampling circuit includes a buffer L, an operational amplifier U, an analog-to-digital converter J, and a data bus;
wherein the content of the first and second substances,
the input end of the buffer L is connected with a Monitor, and the Monitor represents a monitoring point;
the output end of the buffer L is connected with the non-inverting input end of the operational amplifier U;
the output end of the operational amplifier is connected with a Vin port of the analog/digital converter J;
b of A/D converter J1To B8The pins are all connected to the data bus;
the data bus is connected to the computer.
The points to be finally explained are: first, in the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounted," "connected," and "connected" should be understood broadly, and may be a mechanical connection or an electrical connection, or a communication between two elements, and may be a direct connection, and "upper," "lower," "left," and "right" are only used to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed;
secondly, the method comprises the following steps: in the drawings of the disclosed embodiments of the invention, only the structures related to the disclosed embodiments are referred to, other structures can refer to common designs, and the same embodiment and different embodiments of the invention can be combined with each other without conflict;
and finally: the above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that are within the spirit and principle of the present invention are intended to be included in the scope of the present invention.
Claims (3)
1. The utility model provides a high-efficient test system real-time status detection device which characterized in that: the circuit comprises a comparator L1, a comparator L2, a buffer Q1, a buffer Q2, an AND gate U1, an AND gate U2, an AND gate U3, an AND gate U4, an AND gate U5, an AND gate U6, a trigger T1, a trigger T2 and a trigger T3;
the non-inverting input end of the comparator L1 is connected with the VCH; the inverting input end of the comparator L2 is connected with VCL; the Monitor1 is respectively connected to the inverting input terminal of the comparator L1 and the non-inverting input terminal of the comparator L2; the output end of the comparator L1 is connected with the input end of the buffer Q1; the output end of the comparator L2 is connected with the input end of the buffer Q2; the output end of the buffer Q1 is connected with the 0 port of the AND gate U1; the output end of the buffer Q2 is connected with the 1 port of the AND gate U2; the output end of the AND gate is connected with the S end of the trigger T1; the S end of the trigger T2 is connected into a Monitor 2; the Q end of the trigger T1 is connected with the 0 port of the AND gate U2; the Q end of the trigger T2 is connected with the 1 port of the AND gate U2; the 0 port of the AND gate U3 is connected with a Monitor n-1; a port 1 of the AND gate U3 is accessed to a Monitor n; the output end of the AND gate U2 is connected with the 0 port of the AND gate U4; the output end of the AND gate U3 is connected with the 1 port of the AND gate U4; the output end of the AND gate U4 is connected with the 0 port of the AND gate U6; the Q end of the trigger T3 accesses an interrupt response; the output of the and gate U6 is connected to the S terminal of the flip-flop T3 and to the computer via a data bus.
2. The real-time status detection device of an efficient test system as claimed in claim 1, wherein: comprises a detection state parameter setting module, a state parameter database module, a test operation module, a system state detection module, a system state bit judgment module, a board state bit judgment module, a unit state bit judgment module, a function level state identification and interrupt response module, a state parameter display module and an AD sampling circuit,
wherein, the detection state parameter setting module is used for setting parameters and design results,
the state parameter database module is used for storing parameters and design results, the test operation module is used for volume production test,
the system state detection module is used for reading the system level state data bits in real time,
the system status bit judging module is used for judging the system data bit,
the board card status bit judging module is used for judging the data bit of the board card,
the unit state bit judging module is used for judging unit data bits,
the function level state recognition and interrupt response module is used for starting an interrupt response mechanism and a state identification bit recognition mechanism when the state identification bit is read to be abnormal,
the state parameter display module is used for displaying the detailed information of the abnormal state parameters,
the detection state parameter setting module is used for setting an upper limit level, a lower limit level, an initial state bit and an enabling bit for judging whether the monitoring function is started or not,
the AD sampling circuit is used for reading the actual value of the state parameter.
3. The real-time status detection device of an efficient test system as claimed in claim 2, wherein: the AD sampling circuit comprises a buffer L, an operational amplifier U, an analog-digital converter J and a data bus;
wherein the content of the first and second substances,
the input end of the buffer L is connected with a Monitor, and the Monitor represents a monitoring point;
the output end of the buffer L is connected with the non-inverting input end of the operational amplifier U;
the output end of the operational amplifier is connected with a Vin port of the analog/digital converter J;
b of A/D converter J1To B8The pins are all connected to the data bus;
the data bus is connected to the computer.
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| CN202010957410.0A CN112198471A (en) | 2020-09-13 | 2020-09-13 | Real-time state detection device of efficient test system |
| PCT/CN2020/124076 WO2022052231A1 (en) | 2020-09-13 | 2020-10-27 | Efficient real-time status detection device for test system |
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| CN202010957410.0A CN112198471A (en) | 2020-09-13 | 2020-09-13 | Real-time state detection device of efficient test system |
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