CN109408339A - A kind of CPLD/FPGA register control method and system - Google Patents
A kind of CPLD/FPGA register control method and system Download PDFInfo
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- CN109408339A CN109408339A CN201811306239.6A CN201811306239A CN109408339A CN 109408339 A CN109408339 A CN 109408339A CN 201811306239 A CN201811306239 A CN 201811306239A CN 109408339 A CN109408339 A CN 109408339A
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- 238000007726 management method Methods 0.000 description 7
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- 238000004519 manufacturing process Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/3476—Data logging
Abstract
The present invention provides a kind of CPLD/FPGA register control methods, comprising the following steps: is received by the first register and deposits abnormal electricity condition signal；Normal electricity condition signal, abnormal electricity condition signal and malfunction mark bit level from the first register are received by selector；Based on malfunction mark bit level, abnormal electricity condition signal or normal electricity condition signal are transmitted to the second register optionally through selector；And second register the abnormal electricity condition signal received or normal electricity condition signal are deposited and are transferred to BMC to show.The present invention both ensure that BMC obtained necessary signals information, while increase transmitting information, and perfect mainboard CPLD/FPGA management information has important references value for debugging and fault location.
Description
Technical field
Present invention relates in general to computer fields, and more particularly, to a kind of CPLD/FPGA register controlling party
Method and system.
Background technique
In server system, the usual power-on and power-off timing control for passing through the entire server of CPLD/FPGA chip controls,
LED indication control, communication control, key detection, detection of power loss and fan control, hard disk instruction control etc., wherein be based on
CPLD/FPGA chip realizes signal monitoring, and it is the important content of server design that collaboration BMC, which realizes that signal is shown,.
BMC is the important component of server system, independently of system hardware, also not dependent on operating system, therefore
Can be cooperateed with other component systems carry out whole system platform management, as remote diagnosis, console support, configuration management,
Hardware management and troubleshooting.BMC can be communicated by I2C interface with CPLD/FPGA, to be obtained by CPLD/FPGA
Version information, CPU model, system such as report an error at the information.Based on above-mentioned thought, BMC can obtain all available letters from CPLD/FPGA
Power supply status indication signal in breath, such as the booting of offer server and operational process is believed with power supply when circuit failure occurs
Number, this is of great significance for the booting debugging in server volume production stage with fault location, can save the plenty of time.But
CPLD/FPGA, which provides a large amount of available signals, to be meaned to consume a large amount of logical resource, this becomes the principle in molded design stage
It is even more unallowable；Meanwhile the product for being still in design initial stage, increase CPLD/FPGA to realize BMC overall monitor
Therefore logical resource brings the increase of production cost, and do not recommend.BMC and CPLD/FPGA realizes information by register
Interaction is the important content of server design, the information of entire server is shown, control and fault location etc. have it is important
Meaning.
Summary of the invention
In consideration of it, the purpose of the embodiment of the present invention is to propose and realize a kind of server master board CPLD-FPGA register
Control method and system, and in particular to by CPLD/FPGA programmable chip specification CPLD/FPGA register address, facilitate item
Purpose unification and later development.
Based on above-mentioned purpose, the one side of the embodiment of the present invention provides a kind of CPLD/FPGA register control method, packet
Include following steps:
It is received by the first register and deposits abnormal electricity condition signal；
Normal electricity condition signal, the abnormal electricity condition signal from the first register and malfunction are received by selector
Indicate bit level；
Based on the malfunction mark bit level, optionally through the selector to described in the transmitting of the second register
Abnormal electricity condition signal or the normal electricity condition signal；And
Second register deposits the abnormal electricity condition signal received or the normal electricity condition signal
And BMC is transferred to be shown.
In some embodiments, further includes:
Other register informations that CPLD/FPGA is transmitted to BMC are defined, which includes the address CPLD/FPGA
Information, version information, warning message, board information, ADR record, UID information and booting timing information.
In some embodiments, the malfunction mark bit level is configured to the failure shape in response to server power supply
State and switch between high low state.
In some embodiments, further includes: provide reservation register resource to expand according to the specific demand of disparity items
Open up register.
In some embodiments, the register is communicated with the BMC by I2C data.
In some embodiments, being received by the first register and depositing abnormal electricity condition signal includes: described first
Register deposits aberrant electrical signals status information under the driving of CPLD/FPGA clock.
In some embodiments, based on the identified malfunction mark bit level, optionally through described
Selector transmits the abnormal electricity condition signal to the second register or the normal electricity condition signal includes: when the failure
When state flag bit is 0, the normal electrical signal status information is deposited and transmitted, when the malfunction flag bit is 1, is posted
It deposits and transmits the aberrant electrical signals status information.
In some embodiments, second register by the abnormal electricity condition signal received or it is described just
It includes: when the BMC sends I2C clock signal described second that normal electricity condition signal, which is deposited and is transferred to BMC to carry out display,
Electricity condition signal to be shown is passed to the BMC by register.
In some embodiments, the malfunction mark bit level is the electricity condition up and down by designing entire engineering
Machine is realized.
The one side of the embodiment of the present invention provides a kind of CPLD/FPGA register controlled system, the system comprises:
Processor；With
Memory, is stored with the program code that processor can be run, and said program code executes institute as above when being run
The method stated.
The present invention has following advantageous effects: the embodiment of the present invention is based on existing CPLD/FPGA chip and realizes service
The control method and system of device mainboard CPLD/FPGA register address, the perfect pipe of mainboard CPLD/FPGA register address
Reason increases ADR record, UID information, booting clock signal, electric signal shape while guaranteeing to have important register information
State etc. is of great significance for the debugging and fault location of server.Meanwhile server master board according to the present invention
The control method and system of CPLD/FPGA register address are the designs realized on existing CPLD/FPGA chip basis, because
This, will not bring the increase of server production cost.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Other embodiments are obtained according to these attached drawings.
Fig. 1 is schematic diagram of the CPLD/FPGA according to an embodiment of the present invention to the BMC register information transmitted；
Fig. 2 is according to an embodiment of the present invention for selecting and showing the circuit diagram of electrical signal status.
Specific embodiment
The following describe embodiment of the disclosure.It should be appreciated, however, that the disclosed embodiments are only example, and
Other embodiments can take various alternative forms.The drawings are not necessarily drawn to scale；Certain functions may be exaggerated or minimum
Change the details to show particular elements.Therefore, specific structure and function details disclosed herein are not necessarily to be construed as restrictive,
And it is merely possible to for instructing those skilled in the art to use representative basis of the invention in various ways.As this field is general
It is logical the skilled person will understand that, the various features with reference to shown or described by any one attached drawing can with it is one or more other
Feature shown in the drawings is combined to produce the embodiment for not being explicitly illustrated or describing.The group of shown feature is combined into typical case
Provide representative embodiment.However, the various combinations and modification of the feature consistent with the introduction of the disclosure are for certain spies
Fixed application or embodiment may be desired.
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
The embodiment of the present invention is further described in attached drawing.
CPLD/FPGA is the specific integrated circuit of a semi-custom, have it is programmable, erasable, be easy to verifying, integrated level
The number of advantages such as high and rich hardware resource, have been more and more widely used in early development verifying and application controls field.
Based on above-mentioned advantage, realize that bottom circuit design realizes that logic control is got in server system by CPLD/FPGA
To be more widely applied.
In order to solve the above problem, the present invention proposes and realizes that a kind of CPLD/FPGA register control method, feature exist
In, comprising the following steps:
It is received by the first register and deposits abnormal electricity condition signal；
Normal electricity condition signal, the abnormal electricity condition signal from the first register and malfunction are received by selector
Indicate bit level；
Based on the malfunction mark bit level, optionally through the selector to described in the transmitting of the second register
Abnormal electricity condition signal or the normal electricity condition signal；And
Second register deposits the abnormal electricity condition signal received or the normal electricity condition signal
And BMC is transferred to be shown.
In some embodiments, this method further includes other register informations for defining CPLD/FPGA and transmitting to BMC, should
Register information include CPLD/FPGA address information, version information, warning message, board information, ADR record, UID information with
And booting timing information.In some embodiments, a kind of server master board CPLD-FPGA register control method is related to a kind of clothes
It has been shown that, monitoring and the protection of business device system register signal, and in particular to pass through CPLD/FPGA programmable chip specification CPLD/
FPGA register address facilitates unification and the later development of project；The register information that the CPLD/FPGA of definition is transmitted to BMC
When except comprising CPLD/FPGA address information, version information, CPU warning message, board information, ADR record, UID information and booting
Outside sequential signal, while increasing electrical signal status information, especially the power supply status indication signal in server normal course of operation
And the power supply status indication signal when abnormal conditions such as server generation power supply short circuit, the former is for booting debugging and volume production rank
The fault location of section is of great significance, and the latter is for timely disengagement failure power supply and all power supplys, protection in the event of a failure
Server Device prevents unnecessary loss, records abort situation in time simultaneously, has important meaning to later period fault location
Justice.
In some embodiments, the malfunction mark bit level of introducing in response to server power supply malfunction and
Switch between high low state.When malfunction flag bit is 0, register is deposited and is transmitted in normal boot-strap and operational process
Electricity condition signal, the electricity condition signal when malfunction flag bit is 1, when register is deposited and transmits failure.
It in some embodiments, further include that reservation register resource is provided to be posted according to the specific demand of disparity items extension
Storage.Wherein register control method proposed by the invention is the register address defined according to four road Servers standards, this
The management application of kind normal address is equally applicable to two road servers；In some embodiments, register and BMC pass through I2C data
It is communicated, register deposit simultaneously provides I2C data to BMC, and communication format meets I2C communication specification, and each address includes
The register of 8bits；In addition to available signal is provided, reservation register resource is provided, also to meet disparity items different demands
Register extensions application；Xilinx/Altera/Lattice address administration method is each provided, most of CPLD/ can be met
The application demand of FPGA.
In one embodiment, the register information that BMC is communicated with CPLD/FPGA is defined as described above, while pre-
Component register resource is reserved, corresponding signal is then assigned to register, wherein malfunction mark bit level is by setting
The power-on and power-off state machine for counting entire engineering is realized.After designed engineering comprehensive, recordable paper is generated, then can be downloaded to
In CPLD/FPGA, and can be wrong taking human as note, check BMC record case.Server master board CPLD-FPGA register address
Management method can be applied in a plurality of two tunnels and four road servers.
In some embodiments, according to above method definition register resource, corresponding signal is assigned to and is posted accordingly
Memory resource.Malfunction flag bit (Err_Flag) signal is increased for deposit electrical signal status first, is based on malfunction
Flag bit selects the signal deposited and transmitted: when malfunction flag bit is 0, depositing and transmits normal boot-strap and operational process
In electrical signal status, the electrical signal status when malfunction flag bit is 1, when depositing and transmitting failure.Electrical signal status
Selection display rule is as shown in Fig. 2, wherein REG refers to that register, MUX refer to selector.Wherein aberrant electrical signals status information
(PWRGD_Abnormal) the first register REG1 is accessed, selector MUX, normal electrical signal shape are deposited and be transmitted to by REG1
State information (PWRGD_Normal) accesses selector MUX.REG1 is needed to aberrant electrical signals Status register, this is examined for safety
Consider, when there is unknown electric signal exception, CPLD/FPGA needs shutdown trouble power and primary power in time, for later period side
Just positioning failure needs to deposit electrical signal status in the case where CPLD/FPGA clock drives；Aberrant electrical signals and normal electrical signal pass through
Signal to be shown is obtained after the selection of MUX selector, wherein the standard selected is the level state of malfunction flag bit；It shows
The signal shown is deposited by the second register REG2, and when BMC sends I2C_SCK clock signal, which is passed to BMC.
Other electric signal selection modes are identical.
Technically in feasible situation, it can be combined with each other above in relation to technical characteristic cited by different embodiments,
Or change, add and omit etc., to form the additional embodiment in the scope of the invention.
From above-described embodiment as can be seen that the embodiment of the present invention, which is based on existing CPLD/FPGA chip, realizes server master board
The control method and system of CPLD/FPGA register address, the perfect management of mainboard CPLD/FPGA register address, are being protected
While card has important register information, ADR record, UID information, booting clock signal, electrical signal status etc. are increased, it is right
It is of great significance in the debugging of server with fault location.Meanwhile server master board CPLD/FPGA according to the present invention is posted
The control method and system of storage address are therefore the design realized on existing CPLD/FPGA chip basis will not bring clothes
The increase of business device production cost.
Based on above-mentioned purpose, the second aspect of the embodiment of the present invention proposes a kind of CPLD-FPGA register control system
One embodiment of system.The system comprises processors and memory, are stored with the program code that processor can be run, the journey
Sequence code executes method as described above when being run.
From above-described embodiment as can be seen that a kind of server master board CPLD/FPGA register that the embodiment of the present invention proposes
Control system defines the report such as the server info shown by BMC, including CPLD/FPGA address information, version information, CPU
Alert information, board information, ADR record, UID information, booting timing information, electrical signal status information.Both it ensure that BMC acquisition must
Signal message is wanted, while increasing transmitting information, perfect mainboard CPLD/FPGA management information, for debugging and fault location
It is worth with important references.
Those skilled in the art will also understand is that, various illustrative logical blocks, mould in conjunction with described in disclosure herein
Block, circuit and algorithm steps may be implemented as the combination of electronic hardware, computer software or both.It is hard in order to clearly demonstrate
This interchangeability of part and software, with regard to various exemplary components, square, module, circuit and step function to its into
General description is gone.This function is implemented as software and is also implemented as hardware depending on concrete application and application
To the design constraint of whole system.Those skilled in the art can realize described in various ways for every kind of concrete application
Function, but this realization decision should not be interpreted as causing a departure from range disclosed by the embodiments of the present invention.
It is exemplary embodiment disclosed by the invention above, it should be noted that in the sheet limited without departing substantially from claim
Under the premise of inventive embodiments scope of disclosure, it may be many modifications and modify.According to open embodiment described herein
The function of claim to a method, step and/or movement be not required to the execution of any particular order.In addition, although the present invention is implemented
Element disclosed in example can be described or be required in the form of individual, but be unless explicitly limited odd number, it is understood that be multiple.
It should be understood that it is used in the present context, unless the context clearly supports exceptions, singular " one
It is a " it is intended to also include plural form.It is to be further understood that "and/or" used herein refers to including one or one
Any and all possible combinations of a above project listed in association.
It is for illustration only that the embodiments of the present invention disclose embodiment sequence number, does not represent the advantages or disadvantages of the embodiments.
Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware
It completes, relevant hardware can also be instructed to complete by program, the program can store in a kind of computer-readable
In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..
Above-described embodiment is the possibility example of embodiment, and is mentioned just to be clearly understood that the principle of the present invention
Out.It should be understood by those ordinary skilled in the art that: the discussion of any of the above embodiment is exemplary only, it is not intended that dark
Show that range disclosed by the embodiments of the present invention (including claim) is limited to these examples；Under the thinking of the embodiment of the present invention,
It can also be combined, and exist present invention as described above between technical characteristic in above embodiments or different embodiments
Many other variations of the different aspect of embodiment, for simplicity, they are not provided in details.Therefore, all of the invention real
It applies within the spirit and principle of example, any omission, modification, equivalent replacement, improvement for being made etc. should be included in implementation of the present invention
Within the protection scope of example.
Claims (10)
1. a kind of CPLD/FPGA register control method, which comprises the following steps:
It is received by the first register and deposits abnormal electricity condition signal；
Normal electricity condition signal, abnormal electricity condition signal and malfunction mark from the first register are received by selector
Bit level；
Based on the malfunction mark bit level, the exception is transmitted to the second register optionally through the selector
Electricity condition signal or the normal electricity condition signal；And
The abnormal electricity condition signal received or the normal electricity condition signal are deposited and are passed by second register
BMC is handed to be shown.
2. the method according to claim 1, wherein further include:
Other register informations that CPLD/FPGA is transmitted to BMC are defined, the register information includes the address CPLD/FPGA letter
Breath, version information, warning message, board information, ADR record, UID information and booting timing information.
3. the method according to claim 1, wherein the malfunction mark bit level is configured in response to clothes
Be engaged in device power supply malfunction and switch between high low state.
4. the method according to claim 1, wherein further include:
Reservation register resource is provided according to the specific demand extended register of disparity items.
5. the method according to claim 1, wherein the register is led to the BMC by I2C data
Letter.
6. the method according to claim 1, wherein being received by the first register and depositing abnormal electricity condition letter
It number include: that first register deposits aberrant electrical signals status information under the driving of CPLD/FPGA clock.
7. according to the method described in claim 6, it is characterized in that, based on the identified malfunction mark bit level,
Believe optionally through the selector to the second register transmitting abnormal electricity condition signal or the normal electricity condition
It number include: to deposit when the malfunction flag bit is 0 and transmit the normal electrical signal status information, when the failure
When state flag bit is 1, deposits and transmit the aberrant electrical signals status information.
8. the method according to the description of claim 7 is characterized in that the electric shape of the exception that second register will receive
It includes: when the BMC sends I2C that state signal or the normal electricity condition signal, which are deposited and be transferred to BMC to carry out display,
When clock signal, electricity condition signal to be shown is passed to the BMC by second register.
9. the method according to claim 1, wherein the malfunction mark bit level is entire by designing
The power-on and power-off state machine of engineering is realized.
10. a kind of CPLD/FPGA register controlled system characterized by comprising
Processor；With
Memory, is stored with the program code that processor can be run, and said program code executes such as claim when being run
Method described in any one of 1-9.
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| CN110445638B (en) * | 2019-07-05 | 2022-12-27 | 苏州浪潮智能科技有限公司 | Switch system fault protection method and device |
| CN111488175A (en) * | 2019-12-29 | 2020-08-04 | 北京浪潮数据技术有限公司 | Access control method, device, equipment and readable storage medium |
| CN111488175B (en) * | 2019-12-29 | 2023-07-14 | 北京浪潮数据技术有限公司 | Access control method, device, equipment and readable storage medium |
| CN111459545A (en) * | 2020-03-27 | 2020-07-28 | 广东速美达自动化股份有限公司 | Method and device for optimizing register resources of FPGA (field programmable Gate array) |
| CN111459545B (en) * | 2020-03-27 | 2022-07-22 | 广东速美达自动化股份有限公司 | Method and device for optimizing register resources of FPGA (field programmable Gate array) |
| CN112198471A (en) * | 2020-09-13 | 2021-01-08 | 南京宏泰半导体科技有限公司 | Real-time state detection device of efficient test system |
| CN112148515A (en) * | 2020-09-16 | 2020-12-29 | 锐捷网络股份有限公司 | Fault positioning method, system, device, medium and equipment |
| CN112148515B (en) * | 2020-09-16 | 2023-06-20 | 锐捷网络股份有限公司 | Fault positioning method, system, device, medium and equipment |
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