CN109100671B - Monitoring method and monitoring system for testing system in integrated circuit electronic component testing - Google Patents
Monitoring method and monitoring system for testing system in integrated circuit electronic component testing Download PDFInfo
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Abstract
The invention provides a monitoring method and a monitoring system for a test system in the test of an integrated circuit electronic component, comprising the following steps: A. before the mass production test of the integrated circuit electronic components, initializing a test system; B. defining the fault type and fault grade information of the test system, and entering a mass production test stage of the integrated circuit electronic components; C. detecting the working state of the test system in real time based on the defined fault type and fault grade information to judge the fault type, if no fault exists, continuing the test until the test is finished, otherwise, entering the step D; D. and C, judging whether the fault grade is a fatal fault or not, if so, stopping the test, and otherwise, returning to the step C. Therefore, the test system is monitored in real time in the mass production test process, faults are monitored timely, and the test is stopped, so that continuous production in a fault state is avoided, the damage of the tested IC device is reduced to the maximum extent, and meanwhile, the test efficiency is not influenced in the monitoring process.
Description
Technical Field
The invention relates to the technical field of electrical testing, in particular to a monitoring method and a monitoring system for a testing system in the testing of integrated circuit electronic components.
Background
In the testing of Integrated Circuit (IC) electronic devices, the hardware of the testing system can be monitored and controlled by various techniques and methods, such as system power-on self-test, system calibration, and system precision detection. The above measures are implemented together, and the hardware of the IC testing system is basically ensured to be in a normal state before the IC volume production test is started.
However, the above methods are all means that can be implemented before the IC mass production test, and once the IC mass production test stage is entered, how to ensure that the IC test system can be monitored in time after a sudden failure occurs, thereby avoiding the continuous production in the failure state and even possibly causing the damage of the tested IC device due to the failure of the IC test system. Based on this, the monitoring of the test system in the IC test is imperative.
In addition, the test program of the IC test system adopts an open programming mode for users. Through programming, a user can directly write various test programs for operating hardware. During programming, the test system may also operate in an abnormal state due to various reasons, such as unfamiliarity with hardware driver functions or writing of an incorrect test program through human negligence or mistake.
The traditional fault abnormity positioning method has two types: one is a software problem, which can be located by means of generating a log; in addition, the positioning method is to gradually analyze and reverse the cause of the problem according to the fault phenomenon.
In the process of positioning the hardware fault, the reason of the positioning fault can be gradually determined by means of various external instruments. And in some instances no external meter is present. Even if the instrument is used for monitoring in a conditional mode, the case and the cover of the IC testing instrument are required to be opened, and the external instrument can be accessed. The hardware fault locating mode is inconvenient, unsafe and low in efficiency.
The CN201410230062.1 application number "an automatic hardware device monitoring system based on a domestic operating system" provides a monitoring concept, and the monitoring principle is to sequentially check the states of various hardware of a server through active polling according to a predefined sequence. However, if the polling method is used in an IC test, the test system needs to perform response and test simultaneously, so that a hidden danger of hardware conflict exists, and the test efficiency of the IC test is further affected.
Disclosure of Invention
The present invention is directed to a monitoring method and a monitoring system for a testing system in an integrated circuit electronic device testing, so as to solve the above technical problems
The monitoring method for the test system in the integrated circuit electronic component test comprises the following steps:
A. before the mass production test of the integrated circuit electronic components, initializing a test system;
B. defining the fault type and fault grade information of the test system, and entering a mass production test stage of the integrated circuit electronic components;
C. detecting the working state of the test system in real time based on the defined fault type and fault grade information to judge the fault type, if no fault exists, continuing the test until the test is finished, otherwise, entering the step D;
D. and C, judging whether the fault grade is a fatal fault or not, if so, stopping the test, and otherwise, returning to the step C.
By above, real-time monitoring is carried out on the test system in the mass production test process, the occurrence of faults can be monitored in time, and the test process is stopped when the faults occur, so that continuous production under the fault state is avoided, the damage of the tested IC device is reduced to the maximum extent, and meanwhile, the test efficiency is not influenced by the monitoring process.
Before the step C of detecting the working state of the test system in real time to determine the fault type, the method further includes:
judging the validity of the test parameters in the test functions received by the test system, wherein if the test parameters are in a preset range, the test parameters are valid; otherwise, the detection is stopped.
Therefore, the method avoids the writing error of the test function caused by the carelessness of a tester, and ensures the test safety of the electronic component of the tested integrated circuit.
In step C, detecting the working state of the test system in real time to determine the fault type includes:
adopting different detection circuits to detect the working state of the test system in parallel;
and identifying the type of the working state detected by each detection circuit.
Therefore, the situation that the reason of the positioning problem can be determined step by using various external instruments can be avoided by adopting different fault detection circuits. Especially in some situations where no external meter is present. In addition, a parallel testing and monitoring mode is adopted, so that the testing time can be ensured not to be increased due to the existence of the monitoring system, and the testing efficiency is improved. Meanwhile, once any fault occurs, the corresponding reaction can be immediately carried out.
Wherein, the parallel detection of the working state of the test system by adopting different detection circuits comprises at least one of the following steps:
adopting a clamp detection circuit, which detects the working state of the test system comprises: judging whether the V/I source output of the test system is in a clamping range set by a clamping detection circuit;
adopting an undervoltage detection circuit, wherein the detection of the working state of the test system comprises the following steps: judging whether the voltage output by the test system is smaller than the reference voltage set by the undervoltage detection circuit;
adopt the temperature and humidity detection circuit, its detection test system's operating condition includes: detecting whether the temperature and the humidity of the test system exceed a temperature and humidity threshold set by a temperature and humidity detection circuit;
the adoption of the over-range detection circuit detects the working state of the test system and comprises the following steps: detecting whether the range of the test system exceeds a range threshold value set by the over-range detection circuit;
adopting an overcurrent detection circuit, the detection of the working state of the test system comprises: and detecting whether the current of the test system exceeds a current threshold set by the overcurrent detection circuit.
Therefore, the fault condition is judged by comparing each working parameter of the test system with the threshold value, and the detection can be simultaneously carried out aiming at different possible faults of the test system without influencing the test efficiency.
And D, after the step D, recording the fault type and the fault grade information.
Therefore, when the test system is conveniently maintained, the fault position, the fault type and the fault degree can be intuitively and quickly positioned.
Correspondingly, the invention also provides a monitoring system for a test system in the test of the integrated circuit electronic component, which comprises a test control module, a test driving module and the test system which are sequentially connected;
further comprising:
the information definition module is used for setting and outputting the fault type and the fault grade information of the test system;
the working parameter detection module is connected with the test system and used for detecting the working state of the test system in the integrated circuit electronic component mass production stage;
and the abnormal information processing module is respectively connected with the information definition module and the working parameter detection module and is used for judging the fault according to the fault type and the fault grade information and outputting a test stopping instruction to the test control module when a fatal fault is reached.
Compared with the prior art, the fault detection module can monitor the test system in real time in the test process of the integrated circuit electronic component, once the test system has a fatal fault, the abnormal information processing module can control the test control module to stop testing immediately, and the test safety is ensured.
Wherein the working parameter detection module comprises at least one of the following for parallel detection: the device comprises a clamping detection circuit, an undervoltage detection circuit, a temperature and humidity detection circuit, an over-range detection circuit and an overcurrent detection circuit.
Therefore, different possible faults of the test system can be detected.
Wherein the clamp fault detection circuit includes:
the non-inverting input end of the positive clamp amplifier receives clamping upper limit information, and the other end of the positive clamp amplifier is connected with the non-inverting input end of the negative clamp amplifier after being connected with a first resistor R6 and a second resistor R7 in series; the common connection end of the first resistor R6 and the second resistor R7 is used as the input end of the clamping circuit;
one end of the inverting input end of the positive clamping amplifier is connected with the inverting input end of the negative clamping amplifier, and the other end of the inverting input end of the positive clamping amplifier is connected with a clamping control end in the test system after being connected with a third resistor R5 in series;
the connection end of the third resistor R5 and the inverting input end of the positive clamping amplifier is also connected with a fourth resistor R4 and then grounded;
the output end of the forward clamping amplifier is connected with a reverse diode and then connected with a clamping control end in the test system and the abnormal information processing module;
the non-inverting input end of the reverse clamping amplifier receives the clamping lower limit information, and the output end of the reverse clamping amplifier is connected with a forward diode and then connected with a clamping control end in the test system and the abnormal information processing module.
Therefore, when the voltage V (or the current I) received by the test system is within the upper limit and the lower limit of the set clamp, the output diodes of the two clamp amplifiers are in a reverse bias state, and the whole clamp circuit does not work.
When the voltage V (or the current I) of the test system is received to exceed the upper limit range and the lower limit range of the set clamping, the output diode of one clamping amplifier (if the voltage V (or the current I) is clamped in the forward direction, the forward clamping amplifier acts, and if the voltage V (or the current I) is clamped in the reverse direction, the reverse clamping amplifier acts) enters a forward bias state, the control right of the test system is managed by the clamping circuit, the clamping control of the voltage V (or the current I) is realized, and the clamping fault is output.
Wherein, undervoltage fault detection circuit, overrange fault detection circuit or overcurrent fault detection circuit include respectively:
a comparator, two input ends of which are respectively connected with a voltage division circuit;
one input end of the test system receives the actual voltage value, the actual measuring range value or the actual current value of the test system; the other input end receives the threshold value of the voltage value, the range value or the current value;
the output end of the comparator is connected to the abnormal information processing module.
Therefore, by comparing the voltage value, the range value or the current value of the test system with the threshold value, the comparison result outputs a high (or low) level, namely the fault condition, so that different faults can be detected.
Drawings
FIG. 1 is a flow chart of a monitoring method for a test system in the testing of integrated circuit electronic components;
FIG. 2 is a schematic diagram of a monitoring system for a test system in the testing of integrated circuit electronic components;
FIG. 3 is a schematic circuit diagram of a clamp detection circuit;
FIG. 4 is a schematic circuit diagram of the brown-out detection circuit;
fig. 5 is a schematic diagram of monitoring information recorded by the abnormal information processing module.
Detailed Description
The monitoring method and the monitoring system for a test system in the integrated circuit electronic component test according to the present invention will be described in detail with reference to fig. 1 to 5.
Fig. 1 shows a flow chart of a monitoring method, which includes the following steps:
s101: before the mass production test of the integrated circuit electronic components, the test system is initialized.
Before the mass production test of the integrated circuit electronic components, the initialization process of the test system comprises the procedures of test system power-on self-test, test system calibration, test system precision detection and the like. The initialization process is the same as the prior art in the background art, and is not described in detail.
S102: the test control module outputs test parameters.
From this step, the mass production test process of the integrated circuit electronic components is started. To explain with reference to the monitoring system shown in fig. 2, the information definition module 201 defines the driving information and the abnormal information of the test system in advance. The abnormal information comprises various fault types and fault degree grade classifications of all devices in the test system. The failure types include a clamp failure, an overvoltage failure, a temperature and humidity failure, and the like, which will be described later, and the failure levels include a normal prompt message, a warning message, a fatal error message, and the like.
The information definition module 201 sends the drive parameter definition to the test control module 202 and finally to the test driver module 203 connected thereto. In addition, the abnormality information of the test system is sent to the abnormality information processing module 205.
The test system includes a plurality of devices, such as an eight-channel floating voltage current source module 2041(FOVI), a two-channel floating voltage current source module 2042(FPVI), a four-channel full-floating differential voltmeter module 2043(QVM), and the like, and the test control module 202 selects a test target (selects a test object in the test system), and the test control module 202 outputs the test parameters. The test parameters include, but are not limited to, the following categories: voltage value, current value, sampling depth value, sampling frequency value and clamped value.
S103: the abnormal information processing module 205 determines the validity of the test parameter, and if the test parameter is valid, the step S104 is performed, otherwise, the step S112 is performed to stop the test.
In this step, the judgment of the validity of the test parameter includes judging whether the test gear in the test function is matched with the test parameter.
Taking the test parameters as voltage values as examples: when the voltage level is 10V, the range of the voltage which can be output by the constant voltage source is [ -10V,10V ], and if the test parameter is 20V, the test parameter is invalid. Taking the sampling depth value as an example: and if the gear of the sampling depth value is 2K, the sampling depth value of the measurement parameter exceeds 2K and is invalid.
The selection of the voltage gear and the test parameters are compiled through the test function in the early stage, and whether the test function has errors or not can be detected through the judgment on the validity of the test parameters. When the exception handling module 205 determines that the test parameter is valid, it feeds back an authorization message to the test control module 202. Otherwise, when the test parameters are judged to be invalid, the stop control instruction is directly output to the test control module 202, and the test is suspended.
Through the steps, the problem of wrong programming of the test function can be found in time, and the programming error caused by human negligence or error can be found in time, so that the test error is avoided.
S104: the test system responds to the test parameters to test the integrated circuit electronic components.
The test control module 202 issues the received test target to the test driver module 203 connected thereto, and drives the test target in the test system 204 to act after the test driver module 203 performs corresponding processing.
During the process of testing the integrated circuit electronic device by the testing system 204, the working parameter detecting module 206 detects the working state parameters of the testing system 204 in real time, and sends the detection result to the abnormal information processing module 205 to determine whether the testing system 204 is working normally in real time. The operating parameter detection module 206 includes at least one of: the device comprises a clamping fault detection circuit, an undervoltage fault detection circuit, a temperature and humidity abnormal fault detection circuit, an over-range fault detection circuit and an overcurrent fault detection circuit.
S105 to S108 in the subsequent steps are parallel processes, which will be described below.
S105: the clamp detection circuit judges whether or not clamping occurs, and when clamping occurs, it proceeds to step S109, otherwise, it proceeds to step S110.
Fig. 3 is a schematic circuit diagram of the clamp detection circuit, in which the upper half is a test system circuit and the lower half is a clamp circuit.
Taking the test system circuit as the aforementioned eight-channel floating voltage current source module 2041(FOVI) in the test system as an example, the test system circuit includes a Null amplifier (corresponding to Null AMP in fig. 3) and an integrating amplifier, which are connected in sequence. The non-inverting input terminal of the Null amplifier is grounded, one end of the inverting input terminal is connected with an eight-channel floating voltage current source port, which is referred to as a V/I source port (shown as a V/I DAC in FIG. 3) for short, and the other end of the inverting input terminal is connected with a working Mode control terminal (shown as a V/I Mode in FIG. 3). The working mode control terminal is used for selecting the state of the V/I source port to be a current clamping mode or a voltage clamping mode.
The output end of the Null amplifier is connected to the inverting input end of the integrating amplifier, and the non-inverting input end of the integrating amplifier is grounded.
The clamping circuit comprises a forward clamping amplifier + and a reverse clamping amplifier-, one end of the non-inverting input end of the forward clamping amplifier + is connected with a Clamp + DAC port, and the other end of the forward clamping amplifier + is connected with the non-inverting input end of the reverse clamping amplifier after being connected with resistors R6 and R7 in series; the common connection end of the resistors R6 and R7 is used as the input end (shown as V/I Back in FIG. 3) of the clamping detection circuit; the common connection of the diodes D1, D2 serves as the control terminal of the clamping system, while it is connected to the abnormality information processing block 205.
One end of the inverting input end of the positive clamp amplifier + is connected with the inverting input end of the negative clamp amplifier-, and the other end of the inverting input end of the positive clamp amplifier + is connected with the common connecting end of the Null amplifier and the integrating amplifier after being connected with a resistor R5 in series.
The connecting end of the resistor R5, which is connected with the inverting input end of the positive clamp amplifier +, is also connected with a resistor R4 and then grounded.
The output terminal of the forward clamp amplifier + is connected to a reverse diode D1, which is connected to the common connection terminal of the aforementioned Null amplifier and integrating amplifier.
The non-inverting input end of the reverse clamping amplifier is also connected to the Clamp-DAC port, and the output end of the reverse clamping amplifier is connected to the common connection end of the Null amplifier and the integrating amplifier after being connected with a forward diode D2.
The clamp circuit functions to keep the top or bottom of the periodically varying waveform at some determined dc level. In the circuit, the Clamp + DAC port and the Clamp-DAC port are respectively used for setting upper limit and lower limit information of the Clamp, when the voltage V (or the current I) received by the V/I Back port is within the upper limit and the lower limit of the set Clamp, output diodes of the two Clamp amplifiers are in a reverse bias state, and at the moment, the whole Clamp circuit does not work.
When the voltage V (or the current I) received by the V/I Back port exceeds the upper and lower limit ranges of the set clamp, the output diode of one clamp amplifier (if the clamp amplifier is forward clamped, the forward clamp amplifier is + active, and if the clamp amplifier is reverse clamped, the clamp amplifier is-active) enters a forward bias state, and a clamp current passes through the diode to replace the output integrated current of the Null amplifier to control the integrated amplifier, at this time, the Null amplifier will not function, the control right of the V/I source is managed by the clamp circuit, so that the clamp control of the voltage V (or the current I) is realized, and the output end of the clamp detection circuit controls the top or the bottom of the waveform output by the V/I source to be kept at a certain dc level and is output to the abnormal information processing module 205.
Note that, in the above example, the common connection terminal of the Null amplifier and the integrating amplifier serves as the clamp control terminal of the circuit. In other circuits, the position of the clamping control terminal may be different, and is not limited herein, depending on the specific circuit.
S106: when the undervoltage detection circuit detects undervoltage, the method proceeds to step S109, otherwise, the method proceeds to step S110.
Taking the test system circuit as an example of the aforementioned eight-channel floating voltage current source module 2041(FOVI) in the test system, the output terminal thereof is referred to as a VI source. FIG. 4 is a schematic circuit diagram of the under-voltage detection circuit, which includes a comparator P1, one input terminal of which is a V + port, for receiving the actual voltage value of the VI source; the other input terminal is the FVDD port and receives a reference voltage (or referred to as a threshold voltage). The output terminal (ALARM _ V + shown in fig. 4) is output to the abnormality information processing block 205.
And voltage division circuits are connected between the V + port and the input end of the comparator and between the FVDD port and the input end of the comparator.
When the comparator P1 outputs a high level, it indicates that a voltage shortage occurs, otherwise it indicates normal.
S107: the temperature and humidity detection circuit detects temperature and humidity data, and when the temperature and humidity data is higher than a threshold value, the step S109 is performed, otherwise, the step S110 is performed.
The temperature and humidity fault detection circuit is realized by a temperature and humidity sensor. The temperature and humidity sensor is used for detecting the temperature and humidity of the working of the test system. A temperature and humidity threshold is preset, and when the detected temperature and humidity data is higher than the threshold, that is, it indicates that temperature and humidity abnormality may occur, the temperature and humidity data higher than the threshold is output to the abnormality information processing module 205.
S108: when the over-range detection circuit and the over-current detection circuit detect that the over-range or the over-current occurs, the step S109 is performed, otherwise, the step S110 is performed.
The principles of the two circuits are the same as those of the undervoltage fault detection circuit, and both adopt a comparator to compare the received VI source actual value (output by the test system) with a threshold value, so as to judge whether an over-range or over-current condition occurs, and when the over-range or over-current condition occurs, the detection data is output to the abnormal information processing module 205. And will not be described in detail herein.
S109: the abnormal information processing module 205 determines whether the working parameter detection module 206 detects a fatal fault, and if the working parameter detection module detects a fatal fault, the step S112 is performed to stop the test, otherwise, the step S110 is performed.
The abnormality information processing module 205 recognizes the detection data of the operation parameter detection module 206 based on the abnormality information set by the information definition module 201, and confirms whether it is a fatal failure. The recognition results include the following four types of failure types: firstly, Normal prompt Messages (Normal Messages) have no influence on the operation of the test system; warning Messages (Warning Messages), which may have an effect on the operation of the test system; thirdly, error information (failurs) has influence on the operation of the test system; and fourthly, Fatal error information (Fatal Errors) has influence on the operation of the test system and can cause the breakdown of the test system.
If and only if the test result belongs to the fourth category, a control instruction is output to the test control module 202, and the step S112 is entered to stop the test.
Otherwise, when the test data belongs to other non-fourth categories, the step S110 is entered, and the test state is continuously maintained, and meanwhile, the monitoring information is recorded. As shown in fig. 5, the recorded monitoring information includes at least one of the following: firstly, fault types are obtained; an information source, which represents a source of collected information, namely a physical channel connected with the eight-channel floating voltage current source module 2041, the two-channel floating voltage current source module 2042(FPVI), the four-channel full-floating differential voltmeter module 2043, and the like; function name, which represents the test function name used for detecting the working parameters of the test system; the parameter name represents the test parameters contained in the test function; explaining the fault information, and clarifying the specific fault information; sixthly, recording fault information time; seventhly, fault marking; and the error label indicates the label of the current test with fault.
S110: the test state is maintained.
When the determination result in step S109 is no fault or the test is not affected by the fault, the test state is maintained, and the test is continued.
S111: and judging whether the test is finished, if so, entering the step S112 to stop the test, and if not, returning to the step S110.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. A monitoring method for a test system in the test of integrated circuit electronic components is characterized by comprising the following steps:
A. before the mass production test of the integrated circuit electronic components, initializing a test system;
B. defining the fault type and fault grade information of the test system, and entering a mass production test stage of the integrated circuit electronic components;
C. detecting the working state of the test system in real time based on the defined fault type and fault grade information to judge the fault type, if no fault exists, continuing the test until the test is finished, otherwise, entering the step D;
D. judging whether the fault grade is a fatal fault or not, if so, stopping the test, otherwise, returning to the step C;
in step C, detecting the working state of the test system in real time to determine the fault type includes:
adopting different detection circuits to detect the working state of the test system in parallel;
identifying the type of the working state detected by each detection circuit;
the parallel detection of the working state of the test system by adopting different detection circuits comprises the following steps: adopting a clamp detection circuit, which detects the working state of the test system comprises: judging whether the V/I source output of the test system is in a clamping range set by a clamping detection circuit;
the test system includes a floating voltage current source module, which includes: the non-inverting input end of the Null amplifier is grounded, one end of the inverting input end is connected with a floating voltage current source port, the other end of the inverting input end is connected with a working mode control end, and the working mode control end is used for selecting the state of the floating voltage current source port to be a current clamping mode or a voltage clamping mode; the output end of the Null amplifier is connected to the inverting input end of the integrating amplifier, and the non-inverting input end of the integrating amplifier is grounded; the output end of the Null amplifier is a clamping control end;
the clamp fault detection circuit includes:
the non-inverting input end of the positive clamp amplifier receives clamping upper limit information, and the other end of the positive clamp amplifier is connected with the non-inverting input end of the negative clamp amplifier after being connected with a first resistor R6 and a second resistor R7 in series; the common connection end of the first resistor R6 and the second resistor R7 is used as the input end of the clamping circuit;
one end of the inverting input end of the positive clamping amplifier is connected with the inverting input end of the reverse clamping amplifier, and the other end of the inverting input end of the positive clamping amplifier is connected with the clamping control end in the test system after being connected with a third resistor R5 in series;
the connection end of the third resistor R5 and the inverting input end of the positive clamping amplifier is also connected with a fourth resistor R4 and then grounded;
the output end of the forward clamp amplifier is connected with a reverse diode and then connected with a clamp control end and an abnormal information processing module (205) in the test system;
the non-inverting input end of the reverse clamp amplifier receives the clamping lower limit information, and the output end of the reverse clamp amplifier is connected with a forward diode and then connected with a clamping control end and an abnormal information processing module (205) in the test system.
2. The method according to claim 1, before the step C of detecting the working state of the test system in real time for fault type discrimination, further comprising:
judging the validity of the test parameters in the test functions received by the test system, wherein if the test parameters are in a preset range, the test parameters are valid; otherwise, the detection is stopped.
3. The method of claim 1, wherein said detecting an operational state of said test system in parallel using different detection circuits further comprises at least one of:
adopting an undervoltage detection circuit, wherein the detection of the working state of the test system comprises the following steps: judging whether the voltage output by the test system is smaller than the reference voltage set by the undervoltage detection circuit;
adopt the temperature and humidity detection circuit, its detection test system's operating condition includes: detecting whether the temperature and the humidity of the test system exceed a temperature and humidity threshold set by a temperature and humidity detection circuit;
the adoption of the over-range detection circuit detects the working state of the test system and comprises the following steps: detecting whether the range of the test system exceeds a range threshold value set by the over-range detection circuit;
adopting an overcurrent detection circuit, the detection of the working state of the test system comprises: and detecting whether the current of the test system exceeds a current threshold set by the overcurrent detection circuit.
4. The method of claim 1, further comprising the step of recording said fault type and fault class information after step D.
5. A monitoring system aiming at a test system in the test of an integrated circuit electronic component comprises a test control module (202), a test driving module (203) and a test system (204) which are connected in sequence;
it is characterized by also comprising:
the information definition module (201) is used for setting and outputting the fault type and the fault grade information of the test system;
the working parameter detection module (206) is connected with the test system (204) and is used for detecting the working state of the test system in the integrated circuit electronic component mass production stage;
the abnormal information processing module (205) is respectively connected with the information definition module (201) and the working parameter detection module (206), and is used for judging the fault according to the fault type and the fault grade information, and outputting a test stopping instruction to the test control module (202) when a fatal fault is reached;
the operating parameter detection module (206) comprises at least one of the following for parallel detection: the device comprises a clamping detection circuit, an undervoltage detection circuit, a temperature and humidity detection circuit, an over-range detection circuit and an overcurrent detection circuit;
the test system includes a floating voltage current source module, which includes: the non-inverting input end of the Null amplifier is grounded, one end of the inverting input end is connected with a floating voltage current source port, the other end of the inverting input end is connected with a working mode control end, and the working mode control end is used for selecting the state of the floating voltage current source port to be a current clamping mode or a voltage clamping mode; the output end of the Null amplifier is connected to the inverting input end of the integrating amplifier, and the non-inverting input end of the integrating amplifier is grounded; the output end of the Null amplifier is a clamping control end;
the clamp fault detection circuit includes:
the non-inverting input end of the positive clamp amplifier receives clamping upper limit information, and the other end of the positive clamp amplifier is connected with the non-inverting input end of the negative clamp amplifier after being connected with a first resistor R6 and a second resistor R7 in series; the common connection end of the first resistor R6 and the second resistor R7 is used as the input end of the clamping circuit;
one end of the inverting input end of the positive clamping amplifier is connected with the inverting input end of the negative clamping amplifier, and the other end of the inverting input end of the positive clamping amplifier is connected with a clamping control end in the test system after being connected with a third resistor R5 in series;
the connection end of the third resistor R5 and the inverting input end of the positive clamping amplifier is also connected with a fourth resistor R4 and then grounded;
the output end of the forward clamp amplifier is connected with a reverse diode and then connected with a clamp control end and an abnormal information processing module (205) in the test system;
the non-inverting input end of the reverse clamp amplifier receives the clamping lower limit information, and the output end of the reverse clamp amplifier is connected with a forward diode and then connected with a clamping control end and an abnormal information processing module (205) in the test system.
6. The system of claim 5, wherein the under-voltage fault detection circuit, the over-range fault detection circuit, or the over-current fault detection circuit respectively comprise:
a comparator, two input ends of which are respectively connected with a voltage division circuit;
one input end of the test system receives the actual voltage value, the actual measuring range value or the actual current value of the test system; the other input end receives the threshold value of the voltage value, the range value or the current value;
the comparator output is connected to the exception information handling module (205).
Priority Applications (1)
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