CN112188281A

CN112188281A - Image processing method, image processing apparatus, image processing system, and transmission card

Info

Publication number: CN112188281A
Application number: CN201910593622.2A
Authority: CN
Inventors: 韩剑南; 韦桂锋
Original assignee: Xian Novastar Electronic Technology Co Ltd
Current assignee: Xian Novastar Electronic Technology Co Ltd
Priority date: 2019-07-03
Filing date: 2019-07-03
Publication date: 2021-01-05
Anticipated expiration: 2039-07-03
Also published as: CN112188281B

Abstract

The embodiment of the invention provides an image processing method, which comprises the following steps: a data expansion step, which is used for expanding the pixel data of the input source to obtain an expanded pixel data group; a data storage step of writing the expanded pixel data group into a target memory; a data caching step, which is used for reading the expanded pixel data group from the target memory and removing invalid data to obtain an effective pixel data group and writing the effective pixel data group into a first cache; a data conversion step of outputting the effective pixel data group from the first buffer in units of even number of pixel data to obtain an output pixel data group; and an output processing step of performing output processing on the output pixel data according to an output unit of an output interface to obtain a plurality of output unit data to be output from the output interface. The embodiment of the invention solves the problem of low transmission efficiency of the output interface on the premise of ensuring the compatibility of equipment and the code portability.

Description

Image processing method, image processing apparatus, image processing system, and transmission card

Technical Field

The present invention relates to the field of image processing technologies, and in particular, to an image processing method, an image processing apparatus, an image processing system, and a transmitting card.

Background

Nowadays, the RGB color space is the most common color space for display device usage, RGB respectively representing the three-color lamp of an LED display: red, green, blue. The color bit depth of each of the three primary colors may be different, and different color bit depths can bring different visual effects. The color bit depth determines the maximum number of colors that can be present in a color image or the maximum gray scale level in a gray scale image. For example, if each pixel has 8 bits, the maximum number of gray levels is 2 to the power of 8, i.e., 256. The color bit depth of 3 colors of an RGB color image is 4bit, 4bit and 2bit respectively, then the maximum color number is 4+4+2 power of 2, namely 1024, each pixel can be one of 1024 colors. Therefore, the deeper the color bit depth of each color component (RGB), the more colors each pixel can represent, and the finer the visual effect.

However, the deeper the color bit depth is, the larger the bandwidth occupied by the transmitted image is, and the more complicated the processing flow is, and especially in the communication line of the customized protocol, it is very important how to reasonably transmit the image with high color bit depth, and reasonably utilize the bandwidth of the line.

Disclosure of Invention

Embodiments of the present invention provide an image processing method, an image processing apparatus, an image processing system, and a transmitting card to improve a line bandwidth utilization rate to transmit image data of high color bit depth.

Specifically, the embodiment of the present invention provides an image processing method, including a data expansion step, configured to perform expansion processing on pixel data of an input source to obtain an expanded pixel data set; a data storage step of writing the expanded pixel data group into a target memory; a data caching step, which is used for reading the expanded pixel data group from the target memory and removing invalid data to obtain an effective pixel data group and writing the effective pixel data group into a first cache; a data conversion step of outputting the effective pixel data group from the first buffer in units of even number of pixel data to obtain an output pixel data group; and an output processing step, which is used for carrying out output processing on the output pixel data group according to the output unit of the output interface so as to obtain a plurality of output unit data to be output from the output interface.

In one embodiment of the present invention, the data expansion step includes a first expansion sub-step for performing color bit depth expansion on the pixel data of the input source to obtain first expanded pixel data; and a second expansion substep, configured to perform splicing and high-order complement on a plurality of consecutive first expanded pixel data by using a second cache, so as to obtain an expanded pixel data set matching a bit width of a data interface of the target memory.

In an embodiment of the present invention, the color bit depth is extended to perform high-order complement on the plurality of color component data of each pixel data, respectively, and the high-order complement is high-order zero.

In an embodiment of the present invention, in the data buffering step, the invalid data includes zero data generated by the color bit depth extension and zero data generated by the high complement.

In one embodiment of the invention, the output processing step comprises a data removal sub-step for removing the first [ (N/2) × 9] bytes from the output pixel data set when N is even or removing the first [ ((N-1)/2) × 9+4] bytes from the output pixel data set when N is odd, in response to the image being shifted laterally by N pixels, to obtain the output unit data to be aligned.

In an embodiment of the present invention, the output processing step further includes a data alignment sub-step, configured to delay one output unit cycle for copying and buffering the output unit data to be aligned in a buffer to be aligned when N is an even number, so as to obtain the plurality of output unit data; and when the N is an odd number, delaying an output unit period, copying and caching the output unit data to be aligned in a cache to be aligned to obtain odd-numbered pixel data to be aligned, combining the first 0.5 bytes of the output unit data to be aligned and the last 0.5 bytes of the odd-numbered pixel data to be aligned in one output unit period, and delaying an output unit period and caching in the cache to be aligned to obtain the output unit data.

The embodiment of the invention also provides an image processing device, which comprises a data expansion module, a data processing module and a data processing module, wherein the data expansion module is used for expanding the pixel data of the input source to obtain an expanded pixel data group; a data storage module for writing the expanded pixel data group into a target memory; the data cache module is used for reading the expanded pixel data group from the target memory and removing invalid data to obtain an effective pixel data group which is written into a first cache; the data conversion module is used for outputting the effective pixel data group from the first cache by taking even pixel data as a unit so as to obtain an output pixel data group; and the output processing module is used for carrying out output processing on the output pixel data group according to the output unit of the output interface so as to obtain a plurality of output unit data to be output from the output interface.

In an embodiment of the present invention, the data expansion module includes a first expansion sub-module, configured to perform color bit depth expansion on pixel data of an input source to obtain first expanded pixel data; and the second expansion submodule is used for splicing and performing high-order complement on a plurality of continuous first expanded pixel data by using a second cache so as to obtain the expanded pixel data group matched with the bit width of the data interface of the target memory.

In one embodiment of the present invention, the invalid data includes zero data generated by the color bit depth extension and zero data generated by the high complement.

In one embodiment of the invention, the output processing module comprises a data removal sub-module for removing the first [ (N/2) × 9] bytes from the output pixel data set when N is even or removing the first [ ((N-1)/2) × 9+4] bytes from the output pixel data set when N is odd in response to a lateral shift of the image by N pixels to obtain the output unit data to be aligned.

In an embodiment of the present invention, the output processing module further includes a data alignment sub-module, configured to delay one output unit cycle for copying and caching the output unit data to be aligned in a cache to be aligned when N is an even number, so as to obtain the plurality of output unit data; and when the N is an odd number, delaying an output unit period, copying and caching the output unit data to be aligned in a cache to be aligned to obtain odd-numbered pixel data to be aligned, combining the first 0.5 bytes of the output unit data to be aligned and the last 0.5 bytes of the odd-numbered pixel data to be aligned in one output unit period, and delaying an output unit period and caching in the cache to be aligned to obtain the output unit data.

The embodiment of the invention also provides an image processing system, which comprises a processor and a memory; wherein the memory stores instructions for execution by the processor and the instructions cause the processor to perform operations to perform any of the image processing methods described above.

The embodiment of the invention also provides a sending card, which comprises a programmable logic device and a processing module, wherein the programmable logic device is used for carrying out any one of the image processing methods; the volatile memory is connected with the programmable logic device and is used as the target memory; and the network port is connected with the programmable logic device and is used as the output interface.

The technical scheme can have the following advantages or beneficial effects: the image processing method, the image processing apparatus, the image processing system and the transmission card provided by the embodiment of the invention read the expanded pixel data group from the target memory and remove invalid data, writing the obtained effective pixel data group into a first buffer, and outputting the effective pixel data group from the first buffer by using an even number of pixel data as a unit, to obtain an output pixel data set, and then performing output processing on the output pixel data set according to an output interface, such as an output unit of a network port, so as to obtain a plurality of output unit data to be output from the output interface, thereby realizing the technical effect that the output interface effectively transmits the image data with high color bit depth, can save system resources, miniaturize products, improve the loading capacity of the products, and the related operation of writing into the target memory is reserved, and the compatibility of equipment and the code portability are ensured.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart of an image processing method according to an embodiment of the present invention.

Fig. 2 is a schematic specific flowchart of an image processing method according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a pixel data structure according to an embodiment of the invention.

Fig. 4 is a schematic detailed flowchart of a data alignment sub-step according to an embodiment of the present invention.

Fig. 5 is a block diagram of an image processing apparatus according to an embodiment of the present invention.

Fig. 6 is a block diagram of an image processing system according to an embodiment of the present invention.

Fig. 7 is a block diagram of a transmitting card according to an embodiment of the present invention.

[ brief description of the drawings ]

10: a programmable logic device; 11: a video source; 12: caching; 13: caching; 14: an output interface; 20: a target memory;

30: an image processing device; 31: a data expansion module; 32: a data storage module; 33: a data caching module; 34: a data conversion module; 35: an output processing module;

40: an image processing system; 41: a processor; 42: a memory;

50: sending the card; 51: a volatile memory; 52: a programmable logic device; 53: and (4) a network port.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a flowchart of an image processing method according to an embodiment of the present invention. The image processing method comprises the following steps:

a data expansion step S1 of performing expansion processing on the pixel data of the input source to obtain an expanded pixel data group; further, the data expansion step S1 may include a first expansion sub-step, configured to perform color bit depth expansion on the pixel data of the input source, for example, performing high complement on each of the plurality of color component data of each of the pixel data to obtain first expanded pixel data; and a second expansion substep, configured to perform splicing and high-order padding, for example, high-order zero padding, on a plurality of consecutive first expanded pixel data by using a second buffer to obtain the expanded pixel data set matching the bit width of the data interface of the target memory.

A data storing step S2 of writing the expanded pixel data group into a target memory;

a data caching step S3, configured to read the expanded pixel data set from the target memory and remove invalid data to obtain a valid pixel data set, and write the valid pixel data set into a first cache;

a data conversion step S4 of outputting the effective pixel data group from the first buffer in units of even-numbered pixel data to obtain an output pixel data group; and

an output processing step S5, configured to perform output processing on the output pixel data group according to an output unit of an output interface, such as a portal, so as to obtain a plurality of output unit data to be output from the output interface.

In order to ensure the device compatibility and the code portability, the image processing method reserves the relevant operation of writing into the target memory, and only improves the subsequent steps, namely a data caching step S3, a data conversion step S4 and an output processing step S5.

Because the pixel data of the input source and the output interface have a problem of different data bit widths, the data content of one pixel data cannot be output through a positive integer number of output units of the output interface, which causes the output interface to output a partial data content of two pixel data in one output unit in one output period, and therefore, when an image is shifted laterally and N pixels are removed, the output pixel data is not aligned with the output period, and therefore, the output processing step S5 further includes:

a data removal sub-step for removing the first [ (N/2) × 9] bytes from said output pixel data set when N is even or removing the first [ ((N-1)/2) × 9+4] bytes from said output pixel data set when N is odd, in response to a lateral shift of the image by N pixels, to obtain output unit data to be aligned; and

a data alignment substep, configured to delay an output unit period to copy and buffer the output unit data to be aligned in a buffer to be aligned to obtain the plurality of output unit data when N is an even number, where the buffer to be aligned is used to buffer the output unit data to be aligned, and since N is an even number, the output unit data to be aligned does not have a condition that half bytes cannot be removed after the data removal substep is completed, and thus, only the buffer to be aligned needs to be used to align output pixel data with an output period; when N is an odd number, delaying an output unit period to copy and buffer the output unit data to be aligned in a buffer to be aligned to obtain odd pixel data to be aligned, combining the first 0.5 bytes of the output unit data to be aligned and the last 0.5 bytes of the odd pixel data to be aligned in one output unit period, and delaying an output unit cycle to be buffered in an alignment buffer to obtain the output unit data, wherein the output unit data to be aligned has a condition that half byte cannot be removed after completing the data removal sub-step because N is an odd number, therefore, the output unit data to be aligned needs to be buffered in the buffer to be aligned for combination through delaying one output unit cycle, the alignment buffer is used for buffering the combined result so that the output pixel data is aligned with the output period.

In summary, the image processing method provided by the present invention can improve the data transmission efficiency of the output interface, and the data buffering step S3 reads the expanded pixel data written in the target memory and removes the invalid data, so as to reduce the invalid data of the pixel data subsequently output to the output interface, thereby achieving the purpose of improving the data transmission efficiency of the output interface.

Referring to fig. 1 and fig. 2 again, fig. 2 is a schematic specific flow chart of an image processing method according to an embodiment of the present invention. To facilitate a clearer understanding of the present embodiment, a processing procedure of the image processing method of the present embodiment is briefly described below:

in the programmable logic device 10, a video source 11 inputs image data in an RGB format, and RGB color bit depths thereof are 12bit, 12bit, and 12bit, respectively; and respectively expanding the color components of the image data, and expanding the 12-bit color component into a 16-bit color component in a high-order zero padding mode to obtain the first expanded pixel data, namely, a 36-bit video source is expanded into a 48-bit video source.

Since the data interface of the target memory 20 (e.g., DDR3SDRAM) is 512 bits, that is, the amount of data stored at a time is at least 512 bits (i.e., 64 bytes). In order to ensure the universality of the code, the data stored in the target memory 20 adopts a method of taking a pixel as a unit (namely 48 bits) and then expanding the pixel into 512 bits, and because the 512 bits cannot divide 48 bits completely, the embodiment uses the cache 12 to piece the first expanded pixel data into 384 bits, and simultaneously fills zeros in the high bits of the 384 bits and expands the high bits into 512 bits to obtain the expanded pixel data group.

When the programmable logic device 10 reads the target memory 20, all invalid data in the expanded pixel data set (i.e., invalid data formed by two expansions) are removed, so as to obtain the valid pixel data set, which is written into the buffer memory 13, such as the RAM. Since the IP core of the buffer 13 cannot generate the buffer 13 with 288 bits input and 8 bits output, the buffer 13 with 288 bits input and 72 bits output is generated, because there is an odd number 3 in the decomposition factor of 288 ═ 96 × 3, and meanwhile, the data bit width of the input source is considered to be 12 bits, and the data bit width of the output interface 14 is considered to be 8 bits, so the output bit width of the buffer 13 is selected to be 72 bits, so as to obtain the output pixel data set.

Referring to fig. 3 and 4 together, fig. 3 is a schematic diagram of a pixel data structure according to an embodiment of the invention; fig. 4 is a schematic detailed flowchart of a data alignment sub-step according to an embodiment of the present invention. The output pixel data set output from the buffer 13 contains 9 data bit widths of the output interface 14, that is, the effective pixel data set is output from the buffer 13 in units of 2 pixel data, so as to obtain 9 output unit data output from the output interface 14. In this state, a situation that the blue low 4bit in the first pixel and the red low 4bit in the second pixel are spliced into a Byte to be sent out as shown in fig. 4 may occur. So if the image is required to be laterally offset by an odd number of pixels, then there will be an already offset pixel data case that carries half a Byte. Therefore, the output step S5 further has a data removal sub-step for removing the first [ (N/2) × 9] bytes from said output pixel data group when N is even or removing the first [ ((N-1)/2) × 9+4] bytes from said output pixel data group when N is odd in response to the image being shifted laterally by N pixels to obtain output unit data to be aligned; and a data alignment substep, configured to, when N is an even number, delay one output unit cycle to copy and cache the output unit data to be aligned in a cache to be aligned, so as to obtain the plurality of output unit data, and then output the output unit data from the output interface 14; and when the number N is an odd number, delaying an output unit period, copying and caching the output unit data to be aligned in a cache to be aligned to obtain odd pixel data to be aligned, combining the first 0.5 bytes of the output unit data to be aligned and the last 0.5 bytes of the odd pixel data to be aligned in one output unit period, delaying an output unit period, caching in the cache to be aligned to obtain the output unit data, and outputting the output unit data from the output interface 14.

As shown in fig. 4, this embodiment provides a detailed description of the data alignment sub-step provided by the embodiment of the present invention on the basis of the above-mentioned embodiment.

Assuming that the image is shifted laterally by one pixel, namely removing (1-1)/2) 9+ 4-4 bytes, and delaying an output cycle to be buffered in a buffer to be aligned; in the same output period, the first 4-bit pixel data from which the byte pixel data is removed and the last 4-bit pixel data buffered in the buffer to be aligned are pieced together to form 8-bit pixel data, and an output period is delayed to be buffered in the alignment buffer, so that a plurality of output unit data are output from the output interface 14.

Assume that the image is shifted laterally by two pixels, i.e., [ (2/2) × 9] ═ 9 bytes, and the image is buffered in the buffer to be aligned after being delayed by one output cycle, so as to obtain a plurality of output unit data to be output from the output interface 14.

In summary, compared with the related art, the embodiment of the invention improves the efficiency of data transmission using the output interface 14. For example: the transmission bandwidth of the output interface 14 is 1000 × 1024 × 0.9 ═ 900Mb/s, and the number of 12-bit color depth pixels that can be transmitted per second in the related art is 900Mb/48 ═ 19660800 pixels, in the embodiment of the present invention, the number of 12-bit color depth pixels, i.e., 900Mb/36 ═ 26214400 pixels, can be transmitted per second, compared with the efficiency improved by about 33% (26214400-. Besides, the number of pixels per second of the video image with 1080P @60 is 1920 × 1080 × 60 ═ 124416000, and in the case of using 6 output interfaces 14, the embodiment of the present invention can transmit 6 × 26214400 ═ 157286400 pixels per second, so that the video image with 1080P @60 of 12-bit color bit depth can be displayed and transmitted.

Referring to fig. 5, fig. 5 is a block diagram of an image processing apparatus according to an embodiment of the present invention. The image processing apparatus 30 includes: a data expansion module 31, configured to perform expansion processing on the pixel data of the input source to obtain an expanded pixel data set; a data storage module 32, configured to write the expanded pixel data group into a target memory; a data cache module 33, configured to read the expanded pixel data set from the target memory and remove invalid data to obtain a valid pixel data set, and write the valid pixel data set into a first cache; a data conversion module 34, configured to output the effective pixel data set from the first buffer in units of even pixel data to obtain an output pixel data set; and an output processing module 35, configured to perform output processing on the output pixel data set according to an output unit of the output interface, so as to obtain multiple output unit data, and output the multiple output unit data from the output interface.

Further, the data expansion module 31 may include: the first expansion submodule is used for carrying out color bit depth expansion on pixel data of an input source, for example, carrying out high complement on a plurality of color component data of each pixel data respectively to obtain first expanded pixel data; and the second expansion submodule is used for splicing a plurality of continuous first expanded pixel data by using a second cache and performing high-order zero padding, such as high-order zero padding, so as to obtain the expanded pixel data group which is matched with the bit width of the data interface of the target memory.

Further, the output processing module 35 includes: a data removal sub-module for removing the first [ (N/2) × 9] bytes from said output pixel data set when N is an even number, or removing the first [ ((N-1)/2) × 9+4] bytes from said output pixel data set when N is an odd number, in response to a lateral shift of the image by N pixels, to obtain output unit data to be aligned; and a data alignment submodule, configured to delay an output unit cycle to copy and cache the output unit data to be aligned in a to-be-aligned cache when N is an even number, so as to obtain the plurality of output unit data, and then output the output unit data from the output interface, where the to-be-aligned cache is configured to cache the output unit data to be aligned, and since N is an even number, the output unit data to be aligned does not have a condition that half bytes cannot be removed after the data removal submodule is executed, and thus, only the to-be-aligned cache is needed to align output pixel data with an output cycle; when N is an odd number, delaying an output unit period to copy and buffer the output unit data to be aligned in a buffer to be aligned to obtain odd pixel data to be aligned, combining the first 0.5 bytes of the output unit data to be aligned and the last 0.5 bytes of the odd pixel data to be aligned in one output unit period, and delaying an output unit cycle to be buffered in an alignment buffer to obtain the output unit data, and then outputting from the output interface, wherein the output unit data to be aligned has a condition that half byte cannot be removed after completing the data removal sub-step because N is an odd number, therefore, the output unit data to be aligned needs to be buffered in the buffer to be aligned for combination through delaying one output unit cycle, the alignment buffer is used for buffering the combined result so that the output pixel data is aligned with the output period.

Referring to fig. 6, fig. 6 is a schematic structural diagram of an image processing system according to an embodiment of the present invention. The image processing system 40 comprises a processor 41 and a memory 42; wherein the memory 42 stores instructions for execution by the processor 41 and which cause the processor 41 to perform operations to perform the image processing method as described previously.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a transmitting card according to an embodiment of the present invention. The transmitting card 50 comprises a programmable logic device 52 for performing the image processing method; a volatile memory 51 connected to the programmable logic device 52 and serving as the target memory; and a network port 53 connected to the programmable logic device 52 and serving as the output interface.

In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present application, and technical solutions of the embodiments can be arbitrarily combined and used in combination without conflict, contradiction, or conflict with the purpose of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. An image processing method, comprising:

a data expansion step, which is used for expanding the pixel data of the input source to obtain an expanded pixel data group;

a data storage step of writing the expanded pixel data group into a target memory;

a data caching step, which is used for reading the expanded pixel data group from the target memory and removing invalid data to obtain an effective pixel data group and writing the effective pixel data group into a first cache;

a data conversion step of outputting the effective pixel data group from the first buffer in units of even number of pixel data to obtain an output pixel data group; and

and an output processing step, configured to perform output processing on the output pixel data group according to an output unit of an output interface, so as to obtain a plurality of output unit data, and output the output unit data from the output interface.

2. The image processing method according to claim 1, wherein the data expansion step includes:

a first expansion substep, configured to perform color bit depth expansion on pixel data of an input source to obtain first expanded pixel data;

and a second expansion substep, configured to perform splicing and high-order complement on a plurality of consecutive first expanded pixel data by using a second cache, so as to obtain an expanded pixel data set matching a bit width of a data interface of the target memory.

3. The image processing method according to claim 2, wherein the color bit depth is extended to perform high-order complement on each of the plurality of color component data of each of the pixel data, the high-order complement being high-order zero complement.

4. The image processing method according to claim 3, wherein in the data buffering step, the invalid data includes zero data generated by the color bit depth extension and zero data generated by the high complement.

5. The image processing method according to claim 1, wherein the output processing step includes:

a data removal sub-step for removing the first [ (N/2) × 9] bytes from said output pixel data set when N is even or removing the first [ ((N-1)/2) × 9+4] bytes from said output pixel data set when N is odd in response to a lateral shift of the image by N pixels to obtain output unit data to be aligned.

6. The image processing method according to claim 5, wherein the output processing step further comprises:

a data alignment substep, configured to, when N is an even number, delay one output unit period to copy and cache the output unit data to be aligned in a cache to be aligned, so as to obtain the plurality of output unit data; and when the N is an odd number, delaying an output unit period, copying and caching the output unit data to be aligned in a cache to be aligned to obtain odd-numbered pixel data to be aligned, combining the first 0.5 bytes of the output unit data to be aligned and the last 0.5 bytes of the odd-numbered pixel data to be aligned in one output unit period, and delaying an output unit period and caching in the cache to be aligned to obtain the output unit data.

7. An image processing apparatus, comprising:

the data expansion module is used for expanding the pixel data of the input source to obtain an expanded pixel data group;

a data storage module for writing the expanded pixel data group into a target memory;

the data cache module is used for reading the expanded pixel data group from the target memory and removing invalid data to obtain an effective pixel data group which is written into a first cache;

the data conversion module is used for outputting the effective pixel data group from the first cache by taking even pixel data as a unit so as to obtain an output pixel data group; and

and the output processing module is used for carrying out output processing on the output pixel data group according to the output unit of the output interface so as to obtain a plurality of output unit data to be output from the output interface.

8. The image processing apparatus according to claim 7, wherein the data expansion module includes:

the first expansion submodule is used for carrying out color bit depth expansion on the pixel data of the input source to obtain first expanded pixel data;

and the second expansion submodule is used for splicing and performing high-order complement on a plurality of continuous first expanded pixel data by using a second cache so as to obtain the expanded pixel data group matched with the bit width of the data interface of the target memory.

9. The image processing apparatus according to claim 8, wherein the color bit depth is extended to perform high-order complementary numbers, which are high-order zero-complementary numbers, respectively, for a plurality of color component data of each of the pixel data.

10. The image processing apparatus according to claim 9, wherein the invalid data includes zero data generated by the color bit depth extension and zero data generated by the high complement.

11. The image processing apparatus according to claim 7, wherein the output processing module includes:

and a data removal sub-module for removing the first [ (N/2) × 9] bytes from said output pixel data group when N is an even number, or removing the first [ ((N-1)/2) × 9+4] bytes from said output pixel data group when N is an odd number, in response to the image being shifted laterally by N pixels, to obtain output unit data to be aligned.

12. The image processing apparatus according to claim 11, wherein the output processing module further comprises:

the data alignment submodule is used for delaying one output unit period to copy and cache the output unit data to be aligned in a cache to be aligned when the N is an even number so as to obtain the output unit data; and when the N is an odd number, delaying an output unit period, copying and caching the output unit data to be aligned in a cache to be aligned to obtain odd-numbered pixel data to be aligned, combining the first 0.5 bytes of the output unit data to be aligned and the last 0.5 bytes of the odd-numbered pixel data to be aligned in one output unit period, and delaying an output unit period and caching in the cache to be aligned to obtain the output unit data.

13. An image processing system, comprising: a processor and a memory; wherein the memory stores instructions for execution by the processor and the instructions cause the processor to perform operations to perform the image processing method of any of claims 1 to 6.

14. A transmitter card, comprising:

a programmable logic device for performing the image processing method according to any one of claims 1 to 6;

the volatile memory is connected with the programmable logic device and is used as the target memory; and

and the network port is connected with the programmable logic device and is used as the output interface.