CN112185312B - Image data processing method and device - Google Patents
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The invention discloses a method and a device for processing image data. Wherein, the method comprises the following steps: acquiring initial image data through a high-level high-performance bus AHB host; and carrying out de-dithering processing and error diffusion processing on the initial image data to obtain target image data. The invention solves the technical problems of higher processing complexity and processing cost in the image data processing mode in the screen display circuit in the prior art.
Description
Technical Field
The present invention relates to the field of image processing, and in particular, to a method and an apparatus for processing image data.
Background
In the related art, the basic principle of a screen display circuit is usually realized based on 3-primary-color data, a pseudo-true color panel (RGB is less than 8-bit) used by a terminal is low in price, the design difficulty of a visual angle and contrast is relatively low, but the color number is greatly reduced, and gray scale is used as a liquid crystal panel for color display or a panel with the pseudo-true color panel less than 8 bits, so that particle noise and stepped patterns are easily generated in image display, and the human eye visual effect of the pseudo-true color panel is not ideal.
Although a certain amount of particle noise can be eliminated by adopting a general error diffusion method for image processing, the requirements on a system clock and computing power are high, a screen display circuit needs to have a large area, miniaturization of terminal equipment is not facilitated, and the complexity and implementation cost of screen display are increased.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the invention provides a method and a device for processing image data, which are used for at least solving the technical problems of higher processing complexity and processing cost in an image data processing mode in a screen display circuit in the prior art.
According to an aspect of an embodiment of the present invention, there is provided a method of processing image data, including: acquiring initial image data through a high-level high-performance bus AHB host; and carrying out de-dithering processing and error diffusion processing on the initial image data to obtain target image data.
Optionally, the acquiring the initial image data by the AHB host includes: obtaining a plurality of signals by the AHB host, wherein the plurality of signals include: an address signal, a write operation signal, a bus size signal, a burst mode signal, a transaction type signal, and a write data signal; the initial image data is acquired from a storage device based on the plurality of signals.
Optionally, the method further includes: dividing the initial image data into multiple paths of image data streams, and performing data caching processing on the multiple paths of image data streams to obtain a first processing result; performing pixel format conversion processing on the first processing result to obtain a second processing result; and under the control of an image synchronous clock, performing hybrid processing on the second processing result to obtain a third processing result.
Optionally, the performing of the de-dithering process on the initial image data includes: and carrying out de-jitter processing on the third processing result to obtain a fourth processing result.
Optionally, the performing the debouncing process on the third processing result includes: performing region division on the third processing result to obtain a plurality of image subregions; determining a dither matrix corresponding to each image subregion based on the size of each image subregion in the plurality of image subregions; and performing de-dithering processing on the third processing result by using the comparison result between each pixel in each image subarea and the dithering matrix.
Optionally, determining a dither matrix corresponding to each image sub-region based on the size of each image sub-region in the plurality of image sub-regions includes: acquiring a first pixel bit number and a second pixel bit number, wherein the first pixel bit number is an initial pixel bit number of each pixel in each image sub-area, and the second pixel bit number is a target pixel bit number of each pixel in each image sub-area after dithering; and determining the dithering bit number of the dithering matrix by adopting the first pixel bit number and the second pixel bit number.
Optionally, the performing de-dithering on the third processing result by using the comparison result between each pixel in each image sub-area and the dither matrix includes: comparing the initial pixel value of each pixel in each image subregion with the threshold value at the corresponding position in the dither matrix respectively; when the threshold value at the corresponding position in the jitter matrix is a first numerical value, the initial pixel value is kept unchanged; and when the threshold value at the corresponding position in the jitter matrix is a second value, reducing the initial pixel value to a target pixel value which can be displayed.
Optionally, the performing error diffusion processing on the initial image data includes: and performing error diffusion processing on the fourth processing result to obtain the target image data.
Optionally, performing error diffusion processing on the fourth processing result to obtain the target image data includes: performing image quantization processing on the fourth processing result to obtain a plurality of quantized pixels; and diffusing the quantization error of each quantized pixel in the plurality of quantized pixels to adjacent pixels to obtain the target image data.
According to another aspect of the embodiments of the present invention, there is also provided an apparatus for processing image data, including: the acquisition module is used for acquiring initial image data through a high-level high-performance interface AHB host; and the processing module is used for carrying out de-jitter processing and error diffusion processing on the initial image data to obtain target image data.
According to another aspect of the embodiments of the present invention, there is also provided a non-volatile storage medium having a computer program stored therein, wherein the computer program is configured to execute the processing method of the image data described in any one of the above when running.
According to another aspect of the embodiments of the present invention, there is also provided a processing chip, configured to run a program, where the program is configured to execute any one of the image data processing methods described above when running.
According to another aspect of the embodiments of the present invention, there is also provided an electronic apparatus, including a memory and a processor, the memory having a computer program stored therein, the processor being configured to execute the computer program to perform any one of the image data processing methods described above.
According to another aspect of embodiments of the present invention, there is also provided an electronic apparatus including a memory in which a computer program is stored, and a high-level high-performance bus configured to run the computer program to perform the method of processing image data described in any one of the above.
In the embodiment of the invention, the initial image data is obtained through an advanced high-performance bus AHB host; the target image data is obtained by carrying out de-jitter processing and error diffusion processing on the initial image data, and the purpose of improving the image data processing rate and efficiency in the screen display circuit is achieved, so that the technical effect of reducing the processing complexity and the processing cost is realized, and the technical problem that the processing complexity and the processing cost are higher in an image data processing mode in the screen display circuit in the prior art is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a flowchart of a method of processing image data according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an alternative image data processing system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an alternative image data processing system according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an alternative dithering process according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating an alternative N-bit dither matrix, according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an image data processing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
According to an embodiment of the present invention, there is provided an embodiment of a method for processing image data, it should be noted that the steps illustrated in the flowchart of the drawings may be executed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be executed in an order different from that herein.
Fig. 1 is a flowchart of a method for processing image data according to an embodiment of the present invention, as shown in fig. 1, the method including the steps of:
step S102, acquiring initial image data through an advanced high-performance bus AHB host;
and step S104, performing de-dithering processing and error diffusion processing on the initial image data to obtain target image data.
In the embodiment of the invention, the initial image data is obtained through an advanced high-performance bus AHB host; the target image data is obtained by carrying out de-jitter processing and error diffusion processing on the initial image data, and the purpose of improving the image data processing rate and efficiency in the screen display circuit is achieved, so that the technical effect of reducing the processing complexity and the processing cost is realized, and the technical problem that the processing complexity and the processing cost are higher in an image data processing mode in the screen display circuit in the prior art is solved.
As shown in fig. 2, in an alternative embodiment of the present application, a storage device 1 and a storage device 2 (e.g., a hardware capture cache module) are respectively used for storing initial image data and target image data, so that the acceleration screen display is not stuck and CPU resources are not released; the Bayer algorithm is adopted to carry out de-dithering processing and error diffusion processing on the initial image data, the de-dithering processing and error diffusion processing effects are obviously enhanced, the problem that the visual display effect of the image of the false-true color panel with the number of bits lower than 8 is poor in liquid crystal display is solved, in addition, compared with a traditional FS filter quantization error analysis method, the image data processing method provided by the embodiment of the application has the advantages that the hardware overhead is reduced by more than 30%, the circuit miniaturization requirement is met, and the complexity and the implementation cost are obviously reduced.
In the embodiment of the application, an advanced high performance bus AHB host (AHB _ MASTER) capable of being integrated in hardware is provided, and is used for completing an active image capturing action, namely acquiring initial image data, and realizing that the actions of cutting, rotating and the like of an image are completed by using the AHB host in a later stage under the condition that the CPUCPU is mainly responsible for the configuration of a control register in the earlier stage; and obtaining target image data through the joint processing of a dithering algorithm and an error diffusion algorithm.
In the above optional embodiment, the error after quantization in the target image data is diffused to the pixel point adjacent to the target image data as much as possible, so that the transmission error is visually eliminated, and clear reproduction of the image data can be realized in both binary equipment and multicolor binary equipment.
In an optional embodiment, the acquiring, by the AHB host, the initial image data includes:
step S202, obtaining a plurality of signals through the AHB host, wherein the plurality of signals include: an address signal, a write operation signal, a bus size signal, a burst mode signal, a transaction type signal, and a write data signal;
step S204, acquiring the initial image data from a storage device based on the plurality of signals.
As also shown in fig. 2, the AHB host is configured to actively transmit data, for example, actively acquire a plurality of signals, such as an address signal, a write operation signal, a bus size signal, a burst mode signal, a transaction type signal, and a write data signal, and acquire the initial image data from the storage devices (e.g., the storage device 1 and the storage device 2 shown in fig. 2) based on the plurality of signals.
As shown in fig. 3, another image processing system provided in an embodiment of the present application includes: AHB host computer and display platform (LCD display panel), above-mentioned AHB host computer includes: AHB bus interface, dither module (e.g., Bayer dither module), configuration and status odd register, clock generator (image synchronization clock generation module), data buffer module (FIFO buffer layer 1 and FIFO buffer layer 2), pixel format conversion module (PFC module), Blending module (Blending).
Still as shown in fig. 3, in an alternative embodiment, the AHB bus interface receives a plurality of signals sent by the AHB host: address (ADDR [31:0]), WRITE operation (WRITE), bus SIZE (SIZE [2:0]), BURST mode (BURST [2:0]), transaction type (TRANS [2:0]), WRITE data (WDATA [31:0]), and the AHB host reads the initial image data from the storage device 1 in accordance with the above-described plurality of signals.
In an optional embodiment, the method further includes:
step S302, dividing the initial image data into multiple paths of image data streams, and performing data caching processing on the multiple paths of image data streams to obtain a first processing result;
step S304, the first processing result is processed by pixel format conversion to obtain a second processing result;
and step S306, under the control of the image synchronous clock, performing hybrid processing on the second processing result to obtain a third processing result.
As an alternative embodiment, the de-dithering of the initial image data includes:
step S402, performing a debouncing process on the third processing result to obtain a fourth processing result.
In the above optional embodiment, as shown in fig. 3, after the AHB host reads the initial image data from the storage device 1 according to the above multiple signals, the initial image data is divided into multiple image data streams, the multiple image data streams are respectively transmitted to the FIFO buffer layer 1 and the FIFO buffer layer 2 for data buffering processing, and then the first processing result obtained by the buffering processing is led to the pixel format conversion module for pixel format conversion processing to obtain the second processing result; and then, under the control of an image synchronous clock, a mixing module is adopted to carry out mixing processing on the second processing result to obtain a third processing result, and a debouncing module is adopted to carry out debouncing processing on the third processing result to obtain a fourth processing result.
As shown in fig. 3, by using a debounce module, such as a Bayer algorithm debounce module, instead of performing a debounce process using an FS filter in the prior art, the visual effect of the non-true color lcd panel can be significantly enhanced, and the hardware overhead and power consumption are reduced.
In another optional embodiment, the performing de-jittering processing on the third processing result includes:
step S502, performing area division on the third processing result to obtain a plurality of image sub-areas;
step S504, determining a jitter matrix corresponding to each image subregion based on the size of each image subregion in the plurality of image subregions;
step S506, using the comparison result between each pixel in each image sub-area and the dither matrix, performing de-dither processing on the third processing result.
Digital halftoning is a technique for realizing image reproduction on a binary device using tools such as mathematics and computers based on visual characteristics of human eyes and color forming characteristics of images, and diffuses errors after image quantization to pixels adjacent to the pixels as much as possible so that errors in reproduced images are as small as possible.
In the above optional embodiment, a plurality of image sub-regions may be obtained by performing region division on the third processing result; determining a dither matrix corresponding to each image subregion based on the size of each image subregion in the plurality of image subregions; and performing de-dithering processing on the third processing result by using the comparison result between each pixel in each image subarea and the dithering matrix.
As an alternative embodiment, determining the dither matrix corresponding to each image sub-region based on the size of each image sub-region in the plurality of image sub-regions includes:
step S602, acquiring a first pixel bit number and a second pixel bit number, wherein the first pixel bit number is an initial pixel bit number of each pixel in each image sub-area, and the second pixel bit number is a target pixel bit number of each pixel in each image sub-area after dithering;
step S604, determining the dither bit number of the dither matrix by using the first pixel bit number and the second pixel bit number.
In the above alternative embodiment, the number of bits of each pixel in each image sub-region and the number of target pixels of each pixel in each image sub-region after the dithering process are performed may be determined; and determining the dithering bit number of the dithering matrix.
In the embodiment of the present application, the essence of the Bayer algorithm debouncing module is to compare each pixel value with a corresponding threshold in its dither matrix, and optionally, a dither matrix array that can be selected according to different dither bits is placed in an image sub-area, so that each pixel in the image sub-area corresponds to each threshold of the dither matrix one to one.
In an alternative embodiment, the de-dithering the third processing result using the comparison result between each pixel in each image sub-area and the dither matrix includes:
step S702, comparing the initial pixel value of each pixel in each image sub-area with the threshold value at the corresponding position in the dither matrix;
step S704, when the threshold value at the corresponding position in the dither matrix is the first value, the initial pixel value remains unchanged;
step S706, when the threshold value at the corresponding position in the dither matrix is the second value, decreasing the initial pixel value to the displayable target pixel value.
As an alternative embodiment, as shown in fig. 4, for the color of the 2 × 2 pixel block, if the pixels are all 0, the visual effect is also 0, and if all 2 pixels are red and 2 pixels are 0, the visual effect may generate 5-level gray. Still as shown in fig. 4, in the state 1 and the state 4, the jitter "0" indicates that the corresponding position input is not changed, the "1" indicates that the input value of the corresponding module is to be reduced to the next displayable value, and if the lower 2 bits of the pixel are "00", "01", "10", and "11", respectively, the pixel value of the blank portion is not changed, the pixel value is reduced to the next displayable pixel value.
In an alternative embodiment, since each 8-bit data in the 2 × 2 pixel block is output as 6 bits, and considering any 8-bit pixel value 0xA8(1010_1000), the upper 6 bits are 0x2A, and if there is no dithering module, 0xA9, 0xA a, 0xA b, and 0xA8 all show the same pixel value 0x2A, i.e. values 0xA8 to 0xAC are lost, dithering modification is performed on 0xA8, 0xA9, and 0xA 35a by using the dithering module.
In the above optional embodiment, the dither matrix may include, but is not limited to, a 1-bit matrix, a 2-bit matrix, a 3-bit matrix, and a 4-bit matrix shown in the schematic diagram of the N-bit dither matrix shown in fig. 5, and when the initial pixel value of each pixel in each image sub-area is compared with the threshold value at the corresponding position in the dither matrix, the dither bit number of the dither matrix may be determined according to the initial pixel bit number of each pixel in each image sub-area and the target pixel bit number of each pixel in each image sub-area after the dither processing.
As an alternative embodiment, the performing the error diffusion process on the initial image data includes:
step S802, performing error diffusion processing on the fourth processing result to obtain the target image data.
As another alternative embodiment, performing error diffusion processing on the fourth processing result to obtain the target image data includes:
step S902, performing image quantization processing on the fourth processing result to obtain a plurality of quantized pixels;
in step S904, the quantization error of each of the plurality of quantized pixels is diffused to an adjacent pixel to obtain the target image data.
In an alternative embodiment, since the error diffusion halftone algorithm is a neighborhood processing process, a single pixel is quantized, that is, an error exists, and surrounding pixels are affected. Performing error diffusion processing on the fourth processing result, and performing image quantization processing on the fourth processing result to obtain a plurality of quantized pixels; and diffusing the quantization error of each quantized pixel in the plurality of quantized pixels to adjacent pixels to obtain the target image data.
As an alternative embodiment, the digital filter that spectrally shapes the quantization error is a quantization of white noise, but the color image is not a single valued quantization. It should be noted that, by adopting the visual effect of the trueness display, compared with the human eye visual effect graph after adding the jitter correction, the display effect difference between the two is not great, but the display effect of the two is better than that of the visual effect graph with the lower 2bit being directly deleted.
Example 2
According to an embodiment of the present invention, there is further provided an apparatus embodiment for implementing the method for processing image data, fig. 6 is a schematic structural diagram of an apparatus for processing image data according to an embodiment of the present invention, and as shown in fig. 6, the apparatus for processing image data includes: an acquisition module 60 and a processing module 62, wherein:
an obtaining module 60, configured to obtain initial image data through a high-level high-performance interface AHB host; and the processing module 62 is configured to perform de-dithering and error diffusion on the initial image data to obtain target image data.
It should be noted that the above modules may be implemented by software or hardware, for example, for the latter, the following may be implemented: the modules can be located in the same processor; alternatively, the modules may be located in different processors in any combination.
It should be noted here that the above-mentioned obtaining module 60 and the processing module 62 correspond to steps S102 to S104 in embodiment 1, and the above-mentioned modules are the same as the examples and application scenarios realized by the corresponding steps, but are not limited to the disclosure of embodiment 1. It should be noted that the modules described above may be implemented in a computer terminal as part of an apparatus.
It should be noted that, reference may be made to the relevant description in embodiment 1 for alternative or preferred embodiments of this embodiment, and details are not described here again.
The image data processing device may further include a processor and a memory, wherein the acquiring module 60, the processing module 62, and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to implement corresponding functions.
The processor comprises a kernel, and the kernel calls a corresponding program unit from the memory, wherein one or more than one kernel can be arranged. The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.
According to the embodiment of the application, the embodiment of the nonvolatile storage medium is also provided. Optionally, in this embodiment, the nonvolatile storage medium includes a stored program, and the apparatus in which the nonvolatile storage medium is located is controlled to execute the any one of the image data processing methods when the program runs.
Optionally, in this embodiment, the nonvolatile storage medium may be located in any one of a group of computer terminals in a computer network, or in any one of a group of mobile terminals, and the nonvolatile storage medium includes a stored program.
Optionally, the apparatus in which the non-volatile storage medium is controlled to perform the following functions when the program is executed: acquiring initial image data through a high-level high-performance bus AHB host; and carrying out de-dithering processing and error diffusion processing on the initial image data to obtain target image data.
Optionally, the apparatus in which the non-volatile storage medium is controlled to perform the following functions when the program is executed: obtaining a plurality of signals by the AHB host, wherein the plurality of signals include: an address signal, a write operation signal, a bus size signal, a burst mode signal, a transaction type signal, and a write data signal; the initial image data is acquired from a storage device based on the plurality of signals.
Optionally, the apparatus in which the non-volatile storage medium is controlled to perform the following functions when the program is executed: dividing the initial image data into multiple paths of image data streams, and performing data caching processing on the multiple paths of image data streams to obtain a first processing result; performing pixel format conversion processing on the first processing result to obtain a second processing result; and under the control of an image synchronous clock, performing hybrid processing on the second processing result to obtain a third processing result.
Optionally, the apparatus in which the non-volatile storage medium is controlled to perform the following functions when the program is executed: and carrying out de-jitter processing on the third processing result to obtain a fourth processing result.
Optionally, the apparatus in which the non-volatile storage medium is controlled to perform the following functions when the program is executed: performing region division on the third processing result to obtain a plurality of image subregions; determining a dither matrix corresponding to each image subregion based on the size of each image subregion in the plurality of image subregions; and performing de-dithering processing on the third processing result by using the comparison result between each pixel in each image subarea and the dithering matrix.
Optionally, the apparatus in which the non-volatile storage medium is controlled to perform the following functions when the program is executed: acquiring a first pixel bit number and a second pixel bit number, wherein the first pixel bit number is an initial pixel bit number of each pixel in each image sub-area, and the second pixel bit number is a target pixel bit number of each pixel in each image sub-area after dithering; and determining the dithering bit number of the dithering matrix by adopting the first pixel bit number and the second pixel bit number.
Optionally, the apparatus in which the non-volatile storage medium is controlled to perform the following functions when the program is executed: comparing the initial pixel value of each pixel in each image subregion with the threshold value at the corresponding position in the dither matrix respectively; when the threshold value at the corresponding position in the jitter matrix is a first numerical value, the initial pixel value is kept unchanged; and when the threshold value at the corresponding position in the jitter matrix is a second value, reducing the initial pixel value to a target pixel value which can be displayed.
Optionally, the apparatus in which the non-volatile storage medium is controlled to perform the following functions when the program is executed: and performing error diffusion processing on the fourth processing result to obtain the target image data.
Optionally, the apparatus in which the non-volatile storage medium is controlled to perform the following functions when the program is executed: performing image quantization processing on the fourth processing result to obtain a plurality of quantized pixels; and diffusing the quantization error of each quantized pixel in the plurality of quantized pixels to adjacent pixels to obtain the target image data.
According to the embodiment of the application, the embodiment of the processing chip is further provided. Optionally, in this embodiment, the processing chip is configured to run a program, where the program executes any one of the image data processing methods when running.
In the embodiment of the present application, the AHB _ MASTER is a part of a hardware design, the processing chip is designed based on an ARM bus architecture as a hardware entity, and the AHB _ MASTER, the CPU, and the DMA (direct access device) are MASTERs as the ARM bus architecture, and can actively send out addresses and control signals of a bus and realize data transfer.
According to an embodiment of the present application, there is also provided an electronic apparatus embodiment, which includes a memory and a processor, where the memory stores a computer program, and the processor is configured to execute the computer program to perform any one of the image data processing methods.
According to an embodiment of the present application, there is also provided an electronic apparatus embodiment, including a memory in which a computer program is stored, and a high-level high-performance bus configured to run the computer program to perform the method of processing image data described in any one of the above.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (13)
1. A method of processing image data, comprising:
acquiring initial image data through a high-level high-performance bus AHB host;
performing de-jitter processing and error diffusion processing on the initial image data to obtain target image data;
wherein the initial image data and the target image data are respectively stored in different storage devices;
the method further comprises the following steps: acquiring a first pixel bit number and a second pixel bit number, wherein the first pixel bit number is an initial pixel bit number of each pixel in each image sub-area, and the second pixel bit number is a target pixel bit number of each pixel in each image sub-area after dithering; and determining the dithering bit number of the dithering matrix by adopting the first pixel bit number and the second pixel bit number.
2. The method of claim 1, wherein acquiring, by the AHB host, the initial image data comprises:
obtaining, by the AHB host, a plurality of signals, wherein the plurality of signals comprises: an address signal, a write operation signal, a bus size signal, a burst mode signal, a transaction type signal, and a write data signal;
the initial image data is retrieved from a storage device based on the plurality of signals.
3. The method of claim 2, further comprising:
dividing the initial image data into multiple paths of image data streams, and performing data caching processing on the multiple paths of image data streams to obtain a first processing result;
performing pixel format conversion processing on the first processing result to obtain a second processing result;
and under the control of an image synchronous clock, performing hybrid processing on the second processing result to obtain a third processing result.
4. The method of claim 3, wherein de-dithering the initial image data comprises:
and carrying out de-jitter processing on the third processing result to obtain a fourth processing result.
5. The method of claim 4, wherein de-dithering the third processing result comprises:
performing region division on the third processing result to obtain a plurality of image subregions;
determining a dither matrix corresponding to each image subregion based on the size of each image subregion in the plurality of image subregions;
and carrying out de-dithering processing on the third processing result by utilizing the comparison result between each pixel in each image subarea and the dithering matrix.
6. The method of claim 5, wherein de-dithering the third processing result using the comparison result between the respective pixels in each image sub-region and the dither matrix comprises:
comparing the initial pixel value of each pixel in each image sub-area with the threshold value at the corresponding position in the dither matrix respectively;
when the threshold value at the corresponding position in the jitter matrix is a first numerical value, the initial pixel value is kept unchanged; and when the threshold value at the corresponding position in the jitter matrix is a second numerical value, reducing the initial pixel value to a target pixel value which can be displayed.
7. The method of claim 4, wherein error diffusion processing the initial image data comprises:
and performing error diffusion processing on the fourth processing result to obtain the target image data.
8. The method according to claim 7, wherein performing error diffusion processing on the fourth processing result to obtain the target image data comprises:
performing image quantization processing on the fourth processing result to obtain a plurality of quantized pixels;
and diffusing the quantization error of each quantized pixel in the plurality of quantized pixels to adjacent pixels to obtain the target image data.
9. An apparatus for processing image data, comprising:
the acquisition module is used for acquiring initial image data through a high-level high-performance interface AHB host;
the processing module is used for carrying out de-jitter processing and error diffusion processing on the initial image data to obtain target image data;
wherein the initial image data and the target image data are respectively stored in different storage devices;
the apparatus is further configured to: acquiring a first pixel bit number and a second pixel bit number, wherein the first pixel bit number is an initial pixel bit number of each pixel in each image sub-area, and the second pixel bit number is a target pixel bit number of each pixel in each image sub-area after dithering; and determining the dithering bit number of the dithering matrix by adopting the first pixel bit number and the second pixel bit number.
10. A non-volatile storage medium, characterized in that a computer program is stored in the storage medium, wherein the computer program is arranged to execute the method of processing image data according to any of claims 1 to 8 when running.
11. A processing chip for running a program, wherein the program is arranged to execute the method of processing image data according to any one of claims 1 to 8 when running.
12. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and the processor is configured to execute the computer program to perform the method of processing image data as claimed in any one of claims 1 to 8.
13. An electronic device comprising a memory and an advanced high performance bus, wherein the memory has stored therein a computer program, the advanced high performance bus being arranged to run the computer program to perform the method of processing image data as claimed in any one of claims 1 to 8.
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