CN112187203A - Automatic gain control circuit and gain adjusting method thereof - Google Patents
Automatic gain control circuit and gain adjusting method thereof Download PDFInfo
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Abstract
The automatic gain control circuit comprises a series-parallel connection attenuation circuit, wherein the series-parallel connection attenuation circuit comprises a first amplifier, a first field effect tube and a second field effect tube, the inverting end of the first amplifier is connected to a voltage division node through a first impedance element, the first field effect tube is connected between the voltage division node and the inverting end of the first amplifier in series, and the second field effect tube is connected between the voltage division node and a set power supply end in series; and the control voltage forming circuit outputs the voltage-regulated direct current signal to the control end of the first field effect transistor to adjust the equivalent resistance of the first field effect transistor, outputs the voltage-regulated direct current signal to the control end of the second field effect transistor to adjust the equivalent resistance of the second field effect transistor, and further adjusts the gain of the series-parallel connection attenuation circuit to control the voltage amplitude of the output signal of the series-parallel connection attenuation circuit to be unchanged. Through the technical scheme disclosed by the invention, a larger gain adjustable range is realized.
Description
Technical Field
The present disclosure relates to the field of electronic circuits, and in particular, to an automatic gain control circuit and a gain adjustment method thereof.
Background
Automatic Gain Control (AGC) refers to a Control method in which a system automatically adjusts the Gain to overcome instability of an input quantity and keep the output quantity relatively constant. At present, the automatic gain control is widely applied to the fields of wireless communication and the like, and can ensure that an output signal fluctuates only in a small range under the condition that the amplitude variation range of an input signal of a receiver is large so as to overcome the influence of factors such as environment and the like on transmission quality in the signal transmission process. With the progress of technology, optical signals are becoming important signal transmission methods, and the problems of loss and external interference also exist when optical signals propagate in optical fibers or other media, so that automatic gain control is also gradually applied to the fields of optical communication and optical sensing. In addition, automatic gain control is also commonly used in high-power grid systems for reasonably distributing power and improving power utilization efficiency.
The most basic control object of automatic gain control is an electric signal, a module for realizing the automatic gain control function in a circuit is called an AGC amplifier, and the basic design idea of the AGC amplifier is to sample an output signal to form a control voltage and adjust the gain by using the control voltage. Programmable modules are commonly used in digital circuits, and automatic gain control is realized through a specific algorithm. Unlike digital circuits, analog circuits often use control voltages to adjust the resistance of variable resistors, producing different degrees of signal attenuation to achieve gain control. However, due to the characteristic limitation of the variable resistor, a single variable resistor often cannot achieve a large gain adjustable range, so that the gain adjustable range of the automatic gain control is difficult to be increased.
Disclosure of Invention
In order to solve the above technical problem or at least partially solve the above technical problem, the present disclosure provides an automatic gain control circuit and a gain adjustment method thereof, which achieve a larger gain adjustable range.
In a first aspect, an embodiment of the present disclosure provides an automatic gain control circuit, including:
the series-parallel attenuation circuit is used for amplifying an input signal of the automatic gain control circuit by a set multiple and then outputting the amplified input signal, and comprises a first amplifier, a first field effect tube and a second field effect tube, wherein the inverting end of the first amplifier is connected to a voltage division node through a first impedance element, the first field effect tube is connected in series between the voltage division node and the in-phase end of the first amplifier, and the second field effect tube is connected in series between the voltage division node and a set power supply end;
the control voltage forming circuit is connected with the series-parallel connection attenuation circuit and used for converting alternating current signals output by the series-parallel connection attenuation circuit into direct current signals and adjusting the voltage of the direct current signals, the control voltage forming circuit outputs the voltage regulation signals, the direct current signals reach the control end of the first field effect tube to adjust the equivalent resistance of the first field effect tube, and the control voltage regulation signals reach the control end of the second field effect tube to adjust the equivalent resistance of the second field effect tube, and then the gain of the series-parallel connection attenuation circuit is adjusted to control the voltage amplitude of output signals of the series-parallel connection attenuation circuit to be unchanged.
Optionally, the inverting terminal of the first amplifier is connected to the input signal of the automatic gain control circuit through the first impedance element and the second impedance element connected in series, a series node of the first impedance element and the second impedance element is the voltage dividing node, and the voltage dividing node is connected to the output terminal of the first amplifier through a third impedance element.
Optionally, a first end of the first field effect transistor is connected to the voltage dividing node, a second end of the first field effect transistor is connected to the non-inverting end of the first amplifier, and a control end of the first field effect transistor is connected to an output end of the control voltage forming circuit.
Optionally, the non-inverting terminal of the first amplifier is connected to the setting power supply signal through a fourth impedance element.
Optionally, a first end of the second field effect transistor is connected to the voltage dividing node, a second end of the second field effect transistor is connected to the set power signal, and a control end of the second field effect transistor is connected to an output end of the control voltage forming circuit.
Optionally, the control voltage forming circuit includes:
and the rectifying circuit is connected with the series-parallel connection attenuation circuit and used for converting the alternating current signal output by the series-parallel connection attenuation circuit into a direct current signal and outputting the direct current signal.
Optionally, the rectifier circuit comprises:
the inverting terminal of the second amplifier is connected with the output signal of the series-parallel connection attenuation circuit through a fifth impedance element;
a sixth impedance element connected in series between an inverting terminal of the second amplifier and an output terminal of the rectifier circuit;
a first unidirectional pass device connected in series in the forward direction between the output of the second amplifier and the inverting terminal of the second amplifier;
and the second one-way conduction device is connected between the output end of the rectification circuit and the output end of the second amplifier in series in the forward direction.
Optionally, the control voltage forming circuit further includes:
and the filter circuit is respectively connected with the series-parallel connection attenuation circuit and the rectifying circuit and used for filtering ripples in the direct-current signal output by the rectifying circuit and adjusting the voltage of the direct-current signal output by the rectifying circuit, the filter circuit outputs the direct-current signal after voltage regulation to the control end of the first field-effect tube so as to adjust the equivalent resistance of the first field-effect tube, and outputs the direct-current signal after voltage regulation to the control end of the second field-effect tube so as to adjust the equivalent resistance of the second field-effect tube.
Optionally, the filter circuit comprises:
the inverting end of the third amplifier is connected to the output signal of the rectifying circuit sequentially through a seventh impedance element and an eighth impedance element which are connected in series, and the non-inverting end of the third amplifier is connected to an adjustable signal;
a ninth impedance element connected in series between an inverting terminal of the third amplifier and an output terminal of the third amplifier;
a first capacitor connected in series between an inverting terminal of the third amplifier and an output terminal of the third amplifier;
a second capacitor connected in series between a series node of the seventh impedance element and the eighth impedance element and a set power supply terminal.
In a second aspect, an embodiment of the present disclosure further provides a gain adjustment method for an automatic gain control circuit, which is performed by the automatic gain control circuit according to the first aspect, and the gain adjustment method for the automatic gain control circuit includes:
controlling the direct current signals output to the first field effect transistor and the second field effect transistor by the control voltage forming circuit to change in the same direction as the input signals according to the input signals of the automatic gain control circuit;
and adjusting the gain of the series-parallel connection attenuation circuit according to the equivalent resistance of the first field effect transistor and the second field effect transistor so as to control the voltage amplitude of the output signal of the series-parallel connection attenuation circuit to be unchanged.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
the equivalent resistance of the first field effect transistor and the equivalent resistance of the second field effect transistor in the automatic gain control circuit provided by the embodiment of the disclosure are adjustable, the control voltage forming circuit can feed back and adjust the equivalent resistance of the first field effect transistor and the equivalent resistance of the second field effect transistor in real time according to the output signal of the automatic gain control circuit, the first field effect transistor and the second field effect transistor are used for carrying out attenuation control superposition on the input signal of the automatic gain control circuit, the limitation of single variable resistance performance is broken through, a larger gain adjustable range can be effectively realized, the first field effect transistor and the second field effect transistor are used for carrying out attenuation control superposition on the input signal of the automatic gain control circuit, and the recovery speed of the output signal voltage amplitude of the automatic gain control circuit can be accelerated when the voltage amplitude of the input signal of the automatic gain control circuit is changed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of an automatic gain control circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a series attenuated variable gain amplifier used in the prior art;
FIG. 3 is a schematic diagram of a parallel attenuating variable gain amplifier used in the prior art;
fig. 4 is a schematic waveform diagram of an input signal and an output signal of a rectifier circuit provided in the embodiment of the present disclosure;
fig. 5 is a schematic model diagram of an N-channel jfet according to an embodiment of the disclosure;
FIG. 6 is a waveform diagram of an output signal of an automatic gain control circuit employing a series attenuator circuit;
fig. 7 is a waveform diagram of an output signal of an automatic gain control circuit using series-parallel attenuation circuits according to an embodiment of the disclosure;
fig. 8 is a schematic flowchart of a gain adjustment method of a dynamic gain control circuit according to an embodiment of the present disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.
Fig. 1 is a schematic structural diagram of an automatic gain control circuit according to an embodiment of the present disclosure. As shown in fig. 1, the automatic gain control circuit includes a series-parallel attenuation circuit 1 and a control voltage forming circuit 2, the control voltage forming circuit 2 is connected to the series-parallel attenuation circuit 1, the series-parallel attenuation circuit 1 is configured to amplify a set multiple of an input signal UI of the automatic gain control circuit and output the amplified signal UI, an output signal is UO, and the control voltage forming circuit 2 is configured to convert an alternating current signal output by the series-parallel attenuation circuit 1, that is, the output signal UO, into a direct current signal and adjust a voltage of the converted direct current signal.
The series-parallel attenuator circuit 1 includes a first amplifier a1, a first field effect transistor Q1, and a second field effect transistor Q2, wherein an inverting terminal of the first amplifier a1 is connected to a voltage dividing node N through a first impedance element R1, the first field effect transistor Q1 is connected in series between the voltage dividing node N and a non-inverting terminal + of the first amplifier a1, and the second field effect transistor Q2 is connected in series between the voltage dividing node N and a set power supply terminal, which may be, for example, a ground terminal GND. The control voltage forming circuit 2 outputs the regulated dc signal to the control terminal of the first fet Q1 to adjust the equivalent resistance of the first fet Q1, and outputs the regulated dc signal to the control terminal of the second fet Q2 to adjust the equivalent resistance of the second fet Q2, thereby adjusting the gain of the series-parallel attenuator circuit 1 to control the voltage amplitude of the output signal of the series-parallel attenuator circuit 1 to be constant.
The existing attenuation circuit mainly utilizes a single variable resistor to attenuate an input signal through voltage division or shunt, and can be divided into a series attenuation variable gain amplifier and a parallel attenuation variable gain amplifier according to different circuit structures. Fig. 2 is a schematic diagram of a series attenuation variable gain amplifier adopted in the prior art. As shown in fig. 2, the variable resistor RV1 attenuates the input signal UI1 by dividing voltage, and when the input signal UI1 changes, the equivalent resistance of the variable resistor RV1 is controlled to change so that the divided voltage of the signal input to the fixed gain amplifier a4 does not change, and the gain AU1 of the series attenuation variable gain amplifier satisfies the following calculation formula:
wherein, UO1To output the voltage of signal UO1, UI1Is the electricity of input signal UI1Pressure, RV1、R11、R21And Rf1The resistances of resistors RV1, R11, R21 and Rf1,
for the fixed gain of the fixed gain amplifier a4,
the gain expression of the series attenuation variable gain amplifier is that the attenuation amount depends on the variation range of the variable resistor RV 1.
Fig. 3 is a schematic diagram of a parallel attenuation variable gain amplifier adopted in the prior art. As shown in fig. 3, variable resistor RV2 attenuates input signal UI2 by shunting. When the input signal UI2 changes, the equivalent resistance of the variable resistor RV2 is controlled to change, so that the difference value of signals input to the in-phase end + and the anti-phase end of the fixed gain amplifier A5 changes, the purpose of changing the gain of the parallel attenuation variable gain amplifier is achieved, and the gain AU2 of the parallel attenuation variable gain amplifier meets the following calculation formula:
wherein, UO2To output the voltage of signal UO2, UI2Is the voltage of input signal UI2, RV2、R12、R22And Rf2The resistances of resistors RV2, R12, R22 and Rf2,
to attenuate the inverting input gain of the variable gain amplifier in parallel,
in order to attenuate the non-inverting input gain of the variable gain amplifier in parallel, the amount of attenuation of the variable gain amplifier in parallel also depends on the range of variation of the variable resistor RV 2.
However, due to the characteristic limitation of the variable resistor, in the series attenuation variable gain amplifier shown in fig. 2 and the parallel attenuation variable gain amplifier shown in fig. 3, a single variable resistor often cannot achieve a large gain adjustable range, so that the gain adjustable range of the automatic gain control is difficult to be improved.
As shown in fig. 1, in the embodiment of the present disclosure, the first fet Q1 and the second fet Q2 may be controlled to operate in the variable resistance region, such that the first fet Q1 functions as a parallel variable resistor and the second fet Q2 functions as a series variable resistor. Through simulation tests, the gain adjustable range of the automatic gain control circuit with the single variable resistor is about 13bB, and the first field effect transistor Q1 and the second field effect transistor Q2 are utilized to perform series and parallel attenuation control superposition on input signals of the automatic gain control circuit, so that the gain adjustable range of the automatic gain control circuit is increased to about 38dB, the performance limit of the single variable resistor is broken through, and a larger gain adjustable range is effectively realized.
In addition, the automatic gain control circuit provided by the embodiment of the disclosure further includes a control voltage forming circuit 2, the control voltage forming circuit 2 is configured to convert the ac signal output by the series-parallel connection attenuation circuit 1 into a dc signal and adjust the voltage of the converted dc signal, the control voltage forming circuit 2 outputs the voltage-adjusted dc signal to the control terminal of the first fet Q1 to adjust the equivalent resistance of the first fet Q1, and outputs the voltage-adjusted dc signal to the control terminal of the second fet Q2 to adjust the equivalent resistance of the second fet Q2, thereby adjusting the gain of the series-parallel connection attenuation circuit 1, and changing the attenuation degree of the input signal of the automatic gain control circuit to control the voltage amplitude of the output signal of the series-parallel connection attenuation circuit 1 to be unchanged.
Specifically, as shown in fig. 1, if the amplitude of the input signal UI of the agc circuit increases to increase the output signal U0 of the agc circuit, the control voltage forming circuit 2 may adjust the equivalent resistance of the first fet Q1 and the equivalent resistance of the second fet Q2 to decrease by adjusting the dc signals output to the control terminal of the first fet Q1 and the control terminal of the second fet Q2, so that the voltage division of the input signal UI of the agc circuit at the input terminal of the first amplifier a1 decreases, the signal difference between the two input terminals of the first amplifier a1 decreases, and the output signal U0 of the agc circuit decreases and approaches to the original value.
Similarly, if the amplitude of the input signal UI of the agc circuit decreases to decrease the output signal U0 of the agc circuit, the control voltage forming circuit 2 may adjust the equivalent resistance of the first fet Q1 and the equivalent resistance of the second fet Q2 to increase by adjusting the dc signals output to the control terminal of the first fet Q1 and the control terminal of the second fet Q2, so that the voltage division of the input signal UI of the agc circuit at the input terminal of the first amplifier a1 increases, the signal difference between the two input terminals of the first amplifier a1 increases, and the output signal U0 of the agc circuit increases and tends to the original value.
Thus, the equivalent resistances of the first field effect transistor Q1 and the second field effect transistor Q2 are adjusted by feedback of the control voltage forming circuit 2, the gain of the series-parallel attenuation circuit 1 is adjusted, the attenuation degree of the input signal UI of the automatic gain control circuit is effectively changed, the voltage amplitude of the output signal of the series-parallel attenuation circuit 1 is kept unchanged, and automatic gain control, that is, AGC control is realized.
In addition, through simulation tests, the stabilizing time of the output signal of the automatic gain control circuit needs about 60ms, and the first field effect transistor Q1 and the second field effect transistor Q2 are utilized to perform superposition of series attenuation control and parallel attenuation control on the input signal of the automatic gain control circuit in the embodiment of the disclosure, so that the stabilizing time of the output signal U0 of the automatic gain control circuit is shortened to about 30ms, the limitation of the performance of a single variable resistor is broken through, and the recovery speed of the voltage amplitude of the output signal of the automatic gain control circuit is effectively accelerated when the voltage amplitude of the input signal of the automatic gain control circuit is changed.
Alternatively, as shown in fig. 1, the inverting terminal of the first amplifier a1 is connected to the input signal UI of the automatic gain control circuit through the first impedance element R1 and the second impedance element R2 connected in series, the series node of the first impedance element R1 and the second impedance element R2 is a voltage dividing node N, and the voltage dividing node N is connected to the output terminal of the first amplifier a1 through the third impedance element R3.
Illustratively, the resistances of the first impedance element R1 and the second impedance element R2 may be adjustable, the third impedance element R3 constitutes a feedback loop circuit of the first amplifier a1 to ensure that the first amplifier a1 performs an amplifying function, and the non-inverting terminal + of the first amplifier a1 may access a set power signal through the fourth impedance element R4, for example, the set power signal may be a ground signal GND.
Alternatively, as shown in fig. 1, a first terminal of the first fet Q1 is connected to the voltage dividing node N, a second terminal of the first fet Q1 is connected to the non-inverting terminal + of the first amplifier a1, and a control terminal of the first fet Q1 is connected to the output terminal B of the control voltage forming circuit 2. Illustratively, the control terminal of the first fet Q1 may be provided as the gate of the first fet Q1, the first terminal of the first fet Q1 as the source of the first fet Q1, the second terminal of the first fet Q1 as the drain of the first fet Q1, and the first fet Q1 in parallel relationship with the first impedance element R1 connected to the inverting terminal of the first amplifier a 1.
Alternatively, as shown in fig. 1, a first terminal of the second fet Q2 is connected to the voltage dividing node N, and a second terminal of the second fet Q2 is connected to a set power signal, for example, the set power signal may be a ground signal GND, and a control terminal of the second fet Q2 is connected to the output terminal B of the control voltage forming circuit 2. Similarly, the control terminal of the second fet Q2 may be provided as the gate of the second fet Q2, the first terminal of the second fet Q2 as the source of the second fet Q2, the second terminal of the second fet Q2 as the drain of the second fet Q2, and the second fet Q2 in series with the first impedance element R1 connected to the inverting terminal of the first amplifier a 1.
Specifically, as shown in fig. 1, the second fet Q2 constitutes a series attenuation section that attenuates the input signal UI of the agc circuit to UI', which satisfies the following calculation relationship:
wherein, UIFor the voltage of the input signal UI, UI’Is the voltage of signal UI', RVIs the equivalent resistance of the first FET Q1 and the second FET Q2, R2Is the resistance, R, of the second impedance element R2i1The following calculation formula is satisfied:
the first field effect transistor Q1 forms a parallel attenuation part ri1Being input resistance of parallel attenuation part, R1Is the resistance of the first impedance element R1, R4The parallel attenuation section attenuates the signal UI 'to the output signal U0, which is the resistance of the fourth impedance element R4, and UI' and U0 satisfy the following calculation formula:
wherein, UOTo the voltage of the output signal UO, R3For the resistance of the third impedance element R3, the UI and U0 obtained from the above formula satisfy the following calculation formula:
wherein UI corresponds to the numerator part N (R) in the gain expression of U0V) The following calculation formula is satisfied:
N(RV)＝RV·(R3·RV-R2·R4)·(R4+RV)
UI the denominator part D (R) in the gain expression corresponding to U0V) The following calculation formula is satisfied:
D(RV)＝(2R1R2+2R2R4+R1R4)·RV 2+R1R2R4 2+(R1+R2)·RV 3+(3R1R2R4+R2R4 2)·RV
alternatively, as shown in fig. 1, the control voltage forming circuit 2 may be provided to include a rectifying circuit 21, the rectifying circuit 21 is connected to the series-parallel attenuation circuit 1, and the rectifying circuit 21 is configured to convert the alternating current signal UO output by the series-parallel attenuation circuit 1 into a direct current signal and output the direct current signal UO.
Illustratively, as shown in fig. 1, the rectifier circuit 21 may be provided to include a second amplifier a2, a sixth impedance element R6, a first unidirectional conducting device D1 and a second unidirectional conducting device D2, an inverting terminal of the second amplifier a2 is connected to the output signal UO of the series-parallel attenuator circuit 1 through a fifth impedance element R5, the sixth impedance element R6 is connected in series between the inverting terminal of the second amplifier a2 and the output terminal E of the rectifier circuit 21, the first unidirectional conducting device D1 is connected in series between the output terminal F of the second amplifier a2 and the inverting terminal of the second amplifier a2, and the second unidirectional conducting device D2 is connected in series between the output terminal B of the rectifier circuit 21 and the output terminal F of the second amplifier a 2.
Specifically, taking the input signal of the rectifier circuit 21 as UI3 and the output signal as UO3 as an example, when the input signal of the rectifier circuit 21 is UI3 greater than zero, the output of the second amplifier a2 is inevitably made smaller than zero, the first one-way conduction device D1 and the second one-way conduction device D2 may be diodes, for example, the output of the second amplifier a2 is smaller than zero, the second one-way conduction device D2 is turned on, the first one-way conduction device D1 is turned off, the rectifier circuit 21 implements inverse proportion operation, and the output signal UO3 and the input signal UI3 satisfy the following calculation formula:
wherein, UO3To output the voltage of signal UO3, UI3Is the voltage of input signal UI3, R5Is as followsResistance of five resistance elements R5, R5Is the resistance of the sixth impedance element R6.
When the input signal UI3 of the rectifier circuit 21 is less than zero, the output of the second amplifier a2 is inevitably made greater than zero, the second unidirectional conducting device D2 is turned off, the first unidirectional conducting device D1 is turned on, the current flowing through the sixth impedance element R6 is zero, the output signal UO3 is equal to zero, the waveforms of the input signal UI3 and the output signal UO3 are as shown in fig. 4, the abscissa in fig. 4 represents the time t, and the ordinate represents the voltages of the input signal UI3 and the output signal UO3, respectively, as can be seen from fig. 4, the rectifier circuit 21 converts the ac signal output by the series-parallel attenuator circuit 1 into a dc signal and outputs the dc signal, at this time, the output signal UO3 and the input signal UI3 satisfy the following calculation formulas:
wherein UO3(AV) is the average value of the output signal UO3, UI3 is the voltage of the input signal UI3, and ω is the coil rotational angular velocity.
Optionally, as shown in fig. 1, the control voltage forming circuit 2 may further include a filter circuit 22, the filter circuit 22 is connected to the series-parallel attenuator circuit 1 and the rectifier circuit 21, respectively, the filter circuit 22 is configured to filter out ripples in the dc signal output by the rectifier circuit 21 and adjust the voltage of the dc signal output by the rectifier circuit 21, the filter circuit 22 outputs the voltage-adjusted dc signal to the control terminal of the first fet Q1 to adjust the equivalent resistance of the first fet Q1, and outputs the voltage-adjusted dc signal to the control terminal of the second fet Q2 to adjust the equivalent resistance of the second fet Q2.
Illustratively, as shown in fig. 1, the filter circuit 22 may be provided to include a third amplifier a3, a seventh impedance element R7, an eighth impedance element R8, a ninth impedance element R9, a first capacitor C1 and a second capacitor C2, wherein an inverting terminal of the third amplifier A3 is connected to the output signal of the rectifying circuit 21 sequentially through a seventh impedance element R7 and an eighth impedance element R8 which are connected in series, a non-inverting terminal + of the third amplifier A3 is connected to the adjustable signal U +, the ninth impedance element R9 is connected in series between the inverting terminal of the third amplifier A3 and the output terminal of the third amplifier A3, the first capacitor C1 is connected in series between the inverting terminal of the third amplifier A3 and the output terminal of the third amplifier A3, and the second capacitor C2 is connected in series between a series node M of the seventh impedance element R7 and the eighth impedance element R8 and a set power supply terminal.
Illustratively, the filter circuit 22 may be, for example, a second-order low-pass filter circuit, and the gain Au of the filter circuit 22 satisfies the following calculation formula:
wherein R is7Is the resistance of the seventh impedance element R7, R8Is the resistance of the eighth impedance element R8, R9Is the resistance, C, of the ninth impedance element R91Is the capacitance of the first capacitor C1, C2Is the capacitance of the second capacitor C2,
considering only the dc component of the input signal of the filter circuit 22, ignoring the ripple of the output signal of the filter circuit 22, the output signal of the filter circuit 22 can be considered as a dc voltage, and the input signal UI4 and the output signal UO4 of the filter circuit 22 satisfy the following calculation relationship:
wherein, UI4(AV)Is the average value, U, of the input signal UI4O4For the voltage of the output signal UO4, the magnitude of the output signal of the filter circuit 22 can be adjusted by changing the voltage U + at the non-inverting terminal + of the third amplifier A3, and the input signal UI4 and the output signal UO4 satisfy the following calculation relationship:
in summary, as shown in fig. 1, the control voltage forming circuit 2 converts the output signal UO of the agc circuit into UO3 through the half-wave precision rectifier circuit 21, and converts the output signal UO into the dc control voltage UO4 through the second-order low-pass filter circuit 22, so that the dc control voltage UO4 satisfies the following calculation formula:
wherein, UGSIs the gate-source voltage difference of the first fet Q1 or the first fet Q2. The FET is a semiconductor device for controlling current of output loop by using electric field effect of input loop, and can control gate-source voltage U when it is operated in variable resistance regionGSTo change the equivalent resistance R between the drain and the sourceDSTherefore, the first fet Q1 and the second fet Q2 are used as variable resistors in the series-parallel attenuator circuit 1.
The embodiment of the disclosure analyzes R by utilizing the model of the N-channel junction field effect transistor in the SPICE device modelDSAnd UGSThe relationship (2) of (c). Fig. 5 is a schematic model diagram of an N-channel jfet according to an embodiment of the disclosure. As shown in FIG. 5, G is the gate of the N-channel JFET, D is the drain of the N-channel JFET, S is the source of the N-channel JFET, and IDSBeing a non-linear current source, diode DDAnd DSRespectively representing two PN junctions, R, in a field effect transistorDAnd RSOhmic resistance of drain and source of field effect transistor, and capacitor CGDAnd CGSRespectively reflecting the capacitance storage effect of the two PN junctions.
When the N-channel junction field effect transistor works in the variable resistance region, IDSThe following calculation formula is satisfied:
IDS＝βUDS[2(UGS-UGS(off))-UDS](1+λUDS)
where β is the transconductance parameter, λ is the channel length modulation factor, UGS(off)The corresponding grid source voltage when the field effect tube is turned off is lambda 0. If the voltage between the gate and the source is stableFixed DC power supply UGSThe voltage between drain and source is AC small signal UDSThen D isDAnd DSAll are cut off, CGSEquivalent to open circuit, flowing through CGDCurrent ratio of (A) to (B)DSNegligible, equivalent resistance R between drain and sourceVThe following calculation formula is satisfied:
wherein, Delta UGSThe following expression is satisfied:
junction field effect transistor grid source voltage UGSLess than or equal to 0V, substituting into the equivalent resistance R between the drain and the sourceVThe calculation formula obtains the equivalent resistance R between the drain and the source of the field effect transistorVThe following calculation formula is satisfied:
the output signal UO4 of the filter circuit 22 is the gate voltage of the first FET Q1 and the second FET Q2, and the voltage U of the output signal UO4 of the filter circuit 22 is measuredO4Is calculated by
Brought into the above-mentioned Delta UGSIs expressed by (1), to obtain Δ UGSThe following expression is satisfied:
wherein the coefficients a and B satisfy the following calculation formula:
the operation of the automatic gain control circuit of fig. 1 is explained in detail below:
if the output signal UO of the automatic gain control circuit increases due to the increase of the amplitude of the input signal UI of the automatic gain control circuit, the gate input voltage U of the first field effect transistor Q1 and the second field effect transistor Q2GRising, gate-source voltage UGSIncreasing the equivalent resistance R of the first FET Q1 and the second FET Q2VWhen the voltage of the input signal UI of the agc circuit at the input of the first amplifier a1 decreases, the difference between the signals at the two inputs of the first amplifier a1 decreases, and the output signal UO of the agc circuit decreases to approach the original value. If the amplitude of the input signal UI of the automatic gain control circuit is reduced to cause the output signal UO of the automatic gain control circuit to be reduced, the grid input voltage U of the field effect tubeGFalling, gate source voltage UGSReduced FET equivalent resistance RVIf the voltage of the input signal UI of the agc circuit at the input of the first amplifier a1 increases, and the signal difference between the two inputs of the first amplifier a1 increases, the output signal UO of the agc circuit is controlled to increase and approach to the original value.
Simultaneous calculation of the above formulas
And
the obtained input signal UI of the automatic gain control circuit and the output signal UO of the automatic gain control circuit satisfy the following calculation formula:
then there is
When N (R (V (U))O) → 0), input signal U of the agc circuitI→ infinity, when the output signal UO of the AGC circuit changes with the rate of change of the input signal UI of the AGC circuit
It can thus be verified that the magnitude of the output signal UO of the automatic gain control circuit remains unchanged when the input signal UI of the automatic gain control circuit changes.
Based on the above analysis and simulation circuit verification, the parameter R of the series-parallel damping circuit 1 can be set1＝470Ω，R2＝2kΩ，R3＝1MΩ，R41k omega, so that the gain adjustable range is large; taking the parameter R of the control voltage forming circuit 25＝10kΩ，R6＝20kΩ，R8＝10kΩ，R7＝10kΩ，R9＝1MΩ，C2＝1μF，C1＝1μF，U+The voltage is controlled to be proper in size and change rate due to-1.6V; the parameters of the field effect transistor are SPICE model parameters of 2N5486, namely beta is 8.327 multiplied by 10-4A/V2，UGS(off)＝-6V。
Then the above formula of A and B
And
the following calculation formula can be derived:
maximum gain A of attenuation circuit containing only single variable resistor and series-parallel attenuation circuitUMAXAll are as follows:
when U is turnedGSWhen the voltage is equal to 0V, the field effect transistor is just at the boundary point of the variable resistance region and the unstable state, and the formula is shown in the specification
The following can be obtained:
RDS＝RDSmin＝100.1Ω
r is to beDSSubstituting the calculation formula into the gain calculation formula of the series attenuation circuit
It can be seen that the minimum gain A is for the series attenuation circuitUMIN184.3. By substituting the above calculation formula of the series-parallel damping circuit 1, the minimum gain a of the series-parallel damping circuit 1 can be foundUMIN2＝8.3。
For series-parallel attenuation circuit delta U GS6V, from
It can be derived that the output signal UO satisfies the following calculation formula:
it follows that the input signal UI satisfies the following calculation:
when Δ UGSWhen equal to 0, is prepared from
It can be obtained that the output signal UO satisfies the following calculation formula, and at this time, the fet is in the off state:
UO≤B/A＝1.64V
at this time RV→ infinity, substitution
The relationship of input and output can be obtained as follows:
then the input voltage U at that time is obtained from the above two equationsIThe following calculation formula is satisfied:
knowing the effective value U along with the input signal UIIIncreasing from 0 to 4.06mV to 214mV, the effective value U of the output signal UOOIt will increase rapidly from 0 to 1.64V and then slowly to 1.78V. When U is turnedI>At 214mV, the gate-source voltage U of the FETGS>0V, at the moment, the field effect transistor does not work in a stable state, so that the output voltage is unstable.
The gain adjustable range of the series attenuation circuit can be obtained by the formula as follows:
the gain adjustable range of the series-parallel connection attenuation circuit 1 can be obtained by the following formula:
therefore, the first field effect transistor Q1 and the second field effect transistor Q2 are utilized to perform attenuation control superposition on the input signal of the automatic gain control circuit, the limitation of single variable resistance performance is broken through, and a larger gain adjustable range is effectively achieved.
The field effect transistor SPICE model is innovatively substituted into the circuit model for quantitative calculation, and the influence of each circuit parameter on the output effect is determined through quantitative analysis, so that the circuit parameters can be adjusted in a targeted manner. E.g. increase | U+L, or decrease R6/R5The stable value of the output signal can be effectively increased. Through quantitative analysis, the blindness of parameter setting and debugging is avoided.
If the field effect transistor for parallel attenuation is removed and only the series attenuation is reserved, when the amplitude of the input voltage is increased by 100% and then decreased by 50%, the output image of the simulation circuit oscilloscope is shown in fig. 6. If the dual fet is retained, the output image under the same input condition is as shown in fig. 7, the abscissa in fig. 6 and 7 represents the time t, and the ordinate represents the output signal UO of the agc circuit. As shown in fig. 6, when the input voltage is increased for about 20ms, the output voltage U0 changes accordingly, and the output voltage U0 to 80ms is substantially stabilized; the input voltage is reduced for about 80ms, the output voltage U0 changes accordingly, the output voltage U0 to 140ms is basically stabilized, and therefore the stabilization time is about 60ms when only series attenuation is used. As shown in fig. 7, when the input voltage is increased for about 40ms, the output voltage U0 changes accordingly, and the output voltage U0 to 70ms is substantially stabilized; the input voltage is reduced for about 100ms, the output voltage U0 changes accordingly, the output voltage U0 to 130ms is basically stabilized, and therefore the stabilization time is about 30ms when only series attenuation is used. Therefore, the output voltage recovery speed of the series-parallel attenuation circuit is far higher than that of the series-parallel attenuation circuit. Therefore, the simulation result is consistent with the theoretical analysis result.
Illustratively, the amplifier in the embodiment of the present disclosure may adopt an integrated operational amplifier with model number LM7322MA, the model number of the first fet Q1 and the model number of the second fet Q2 being 2N5486, and a voltage regulatorThe model of the tube DZ is 1N5231B, and the stable voltage U thereofZThe voltage is approximately equal to 5V; the type of the diodes D1 and D2 is 1N5817, and the diodes are Schottky rectifier diodes; potentiometers R1, R2, R3, R4, R6, R9 and R11 are 3296W in model.
The embodiment of the disclosure realizes automatic gain control by using a performance control attenuation circuit of a field effect transistor in a variable resistance region, introduces double field effect transistors to form a series-parallel attenuation circuit 1, breaks through the limitation of the performance of a single field effect transistor by the superposition of variable resistance control attenuation, realizes a larger gain adjustable range, and simultaneously forms a control voltage forming circuit 2 by using a half-wave precision rectifying circuit 21 and a second-order low-pass filter circuit 22 to control the equivalent resistance of the field effect transistor. And then introducing an SPICE model of the field effect transistor, obtaining the theoretical performance of the automatic gain control circuit through theoretical calculation, and comparing the theoretical performance with the theoretical performance of a typical circuit to confirm the superiority of the performance of the automatic gain control circuit provided by the embodiment of the disclosure.
The embodiment of the disclosure also provides a gain adjusting method of the dynamic gain control circuit. Fig. 8 is a schematic flowchart of a gain adjustment method of a dynamic gain control circuit according to an embodiment of the present disclosure, where the gain adjustment method of the dynamic gain control circuit may be executed by the dynamic gain control circuit according to the above embodiment. As shown in fig. 8, the gain adjustment method of the dynamic gain control circuit includes:
and S1, controlling the direct current signals output to the first field effect transistor and the second field effect transistor by the voltage forming circuit to change in the same direction as the input signals according to the input signals of the automatic gain control circuit.
And S2, adjusting the gain of the series-parallel connection attenuation circuit according to the equivalent resistance of the first field effect transistor and the second field effect transistor to control the voltage amplitude of the output signal of the series-parallel connection attenuation circuit to be unchanged.
Referring to fig. 1 to 7, if the amplitude of the input signal UI of the agc circuit increases to increase the output signal UO of the agc circuit, the gate input voltage U of the fet is increasedGRising, i.e. the DC signals output by the voltage forming circuit to the first FET Q1 and the second FET Q2 change in the same direction as the input signal, the gate-source voltage UGSWhen the equivalent resistance of the field effect transistor is reduced, the voltage division of the input signal UI of the automatic gain control circuit at the input end of the first amplifier a1 is reduced, and the signal difference between the two input ends of the first amplifier a1 is reduced, so that the output signal UO of the automatic gain control circuit is controlled to be reduced and approaches to the original value.
If the amplitude of the input signal UI of the automatic gain control circuit is reduced to cause the output signal UO of the automatic gain control circuit to be reduced, the grid input voltage U of the field effect tubeGThe voltage is reduced, i.e. the DC signals output by the voltage forming circuit to the first field effect transistor Q1 and the second field effect transistor Q2 change in the same direction as the input signal, and the gate-source voltage U isGSWhen the equivalent resistance of the field effect transistor is decreased and increased, the voltage division of the input signal UI of the automatic gain control circuit at the input end of the first amplifier a1 is increased, and the signal difference between the two input ends of the first amplifier a1 is increased, so that the output signal UO of the automatic gain control circuit is controlled to be increased and tends to the original value.
In summary, the equivalent resistances of the first field effect transistor and the second field effect transistor in the agc circuit are adjustable, the control voltage forming circuit can feed back and adjust the equivalent resistances of the first field effect transistor and the second field effect transistor in real time according to the output signal of the agc circuit, and the first field effect transistor and the second field effect transistor are used to perform attenuation control superposition on the input signal of the agc circuit, thereby breaking through the limitation of single variable resistance performance, and effectively achieving a larger gain adjustable range.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An automatic gain control circuit, comprising:
the series-parallel attenuation circuit is used for amplifying an input signal of the automatic gain control circuit by a set multiple and then outputting the amplified input signal, and comprises a first amplifier, a first field effect tube and a second field effect tube, wherein the inverting end of the first amplifier is connected to a voltage division node through a first impedance element, the first field effect tube is connected in series between the voltage division node and the in-phase end of the first amplifier, and the second field effect tube is connected in series between the voltage division node and a set power supply end;
the control voltage forming circuit is connected with the series-parallel connection attenuation circuit and used for converting alternating current signals output by the series-parallel connection attenuation circuit into direct current signals and adjusting the voltage of the direct current signals, the control voltage forming circuit outputs the voltage regulation signals, the direct current signals reach the control end of the first field effect tube to adjust the equivalent resistance of the first field effect tube, and the control voltage regulation signals reach the control end of the second field effect tube to adjust the equivalent resistance of the second field effect tube, and then the gain of the series-parallel connection attenuation circuit is adjusted to control the voltage amplitude of output signals of the series-parallel connection attenuation circuit to be unchanged.
2. The automatic gain control circuit of claim 1, wherein the inverting terminal of the first amplifier is connected to the input signal of the automatic gain control circuit through the first impedance element and the second impedance element connected in series, a series node of the first impedance element and the second impedance element is the voltage dividing node, and the voltage dividing node is connected to the output terminal of the first amplifier through a third impedance element.
3. The automatic gain control circuit according to claim 1 or 2, wherein a first terminal of the first fet is connected to the voltage dividing node, a second terminal of the first fet is connected to the non-inverting terminal of the first amplifier, and a control terminal of the first fet is connected to the output terminal of the control voltage forming circuit.
4. The automatic gain control circuit of claim 3 wherein the non-inverting terminal of the first amplifier is coupled to the set power supply signal through a fourth impedance element.
5. The automatic gain control circuit according to claim 1 or 2, wherein a first terminal of the second fet is connected to the voltage dividing node, a second terminal of the second fet is connected to the set power signal, and a control terminal of the second fet is connected to an output terminal of the control voltage forming circuit.
6. The automatic gain control circuit of claim 1, wherein the control voltage forming circuit comprises:
and the rectifying circuit is connected with the series-parallel connection attenuation circuit and used for converting the alternating current signal output by the series-parallel connection attenuation circuit into a direct current signal and outputting the direct current signal.
7. The automatic gain control circuit of claim 6, wherein the rectifier circuit comprises:
the inverting terminal of the second amplifier is connected with the output signal of the series-parallel connection attenuation circuit through a fifth impedance element;
a sixth impedance element connected in series between an inverting terminal of the second amplifier and an output terminal of the rectifier circuit;
a first unidirectional pass device connected in series in the forward direction between the output of the second amplifier and the inverting terminal of the second amplifier;
and the second one-way conduction device is connected between the output end of the rectification circuit and the output end of the second amplifier in series in the forward direction.
8. The automatic gain control circuit of claim 6 or 7, wherein the control voltage forming circuit further comprises:
and the filter circuit is respectively connected with the series-parallel connection attenuation circuit and the rectifying circuit and used for filtering ripples in the direct-current signal output by the rectifying circuit and adjusting the voltage of the direct-current signal output by the rectifying circuit, the filter circuit outputs the direct-current signal after voltage regulation to the control end of the first field-effect tube so as to adjust the equivalent resistance of the first field-effect tube, and outputs the direct-current signal after voltage regulation to the control end of the second field-effect tube so as to adjust the equivalent resistance of the second field-effect tube.
9. The automatic gain control circuit of claim 8, wherein the filtering circuit comprises:
the inverting end of the third amplifier is connected to the output signal of the rectifying circuit sequentially through a seventh impedance element and an eighth impedance element which are connected in series, and the non-inverting end of the third amplifier is connected to an adjustable signal;
a ninth impedance element connected in series between an inverting terminal of the third amplifier and an output terminal of the third amplifier;
a first capacitor connected in series between an inverting terminal of the third amplifier and an output terminal of the third amplifier;
a second capacitor connected in series between a series node of the seventh impedance element and the eighth impedance element and a set power supply terminal.
10. A method of gain adjustment of an automatic gain control circuit, performed by the automatic gain control circuit of any of claims 1-9, the method of gain adjustment of the automatic gain control circuit comprising:
controlling the direct current signals output to the first field effect transistor and the second field effect transistor by the control voltage forming circuit to change in the same direction as the input signals according to the input signals of the automatic gain control circuit;
and adjusting the gain of the series-parallel connection attenuation circuit according to the equivalent resistance of the first field effect transistor and the second field effect transistor so as to control the voltage amplitude of the output signal of the series-parallel connection attenuation circuit to be unchanged.
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