CN112185248A - Pixel structure - Google Patents
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- CN112185248A CN112185248A CN201910603382.XA CN201910603382A CN112185248A CN 112185248 A CN112185248 A CN 112185248A CN 201910603382 A CN201910603382 A CN 201910603382A CN 112185248 A CN112185248 A CN 112185248A
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- insulating layer
- pixel structure
- interlayer insulating
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- layer
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
Abstract
The invention provides a pixel structure, which comprises a first metal layer, a gate insulating layer, a second metal layer, a first interlayer insulating layer, a first conducting layer, a second interlayer insulating layer and a second conducting layer. The first metal layer comprises a grid and a scanning line. The scan lines extend in a first direction. The gate insulating layer is disposed on the first metal layer. The second metal layer is arranged on the gate insulating layer. The second metal layer comprises a source electrode, a drain electrode, a data line and a sensing line. The data line extends in a second direction. The sensing line comprises a trunk and an extension part. The trunk extends in a first direction. The extension portion extends in a second direction. The extension portion is provided corresponding to the scan line. The first interlayer insulating layer is arranged on the second metal layer. The first conductive layer is disposed on the first interlayer insulating layer. The second interlayer insulating layer is arranged on the first conductive layer. The second conductive layer is disposed on the second interlayer insulating layer.
Description
Technical Field
The present invention relates to a pixel structure, and more particularly, to a pixel structure with a triple gate design.
Background
In a display panel driving chip integrated with a touch function, a portion of a common electrode above a scan line and a sense line in a pixel structure is usually removed (i.e., the common electrode has a plurality of openings) to reduce the resistance-capacitance load between the scan line and the sense line and the common electrode. However, the scanning lines and the sensing lines need to be covered with a black matrix to avoid light leakage, which results in a decrease in the aperture ratio of the pixel structure.
Disclosure of Invention
The invention provides a pixel structure which can improve the aperture opening ratio under the condition of avoiding the light leakage phenomenon.
According to an embodiment of the present invention, a pixel structure of the present invention includes a first metal layer, a gate insulating layer, a second metal layer, a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer. The first metal layer comprises a grid and a scanning line. The scan lines extend in a first direction. The gate insulating layer is disposed on the first metal layer. The second metal layer is arranged on the gate insulating layer. The second metal layer comprises a source electrode, a drain electrode, a data line and a sensing line. The data line extends in a second direction. The sensing line comprises a trunk and an extension part. The trunk extends along a second direction. The extension portion extends in a first direction. The extension portion is provided corresponding to the scan line. The first interlayer insulating layer is arranged on the second metal layer. The first conductive layer is disposed on the first interlayer insulating layer. The second interlayer insulating layer is arranged on the first conductive layer. The second conductive layer is disposed on the second interlayer insulating layer.
In the pixel structure according to the embodiment of the present invention, the pixel structure is applied to a display panel of a triple gate design.
In the pixel structure according to the embodiment of the invention, the second conductive layer includes a slit.
According to an embodiment of the present invention, a pixel structure of the present invention includes a first metal layer, a gate insulating layer, a second metal layer, a first interlayer insulating layer, a third metal layer, a second interlayer insulating layer, a first conductive layer, a third interlayer insulating layer, and a second conductive layer. The first metal layer comprises a grid and a scanning line. The scan lines extend in a first direction. The gate insulating layer is disposed on the first metal layer. The second metal layer is arranged on the gate insulating layer. The second metal layer comprises a source electrode, a drain electrode and a data line. The data line extends in a second direction. The first interlayer insulating layer is arranged on the second metal layer. The third metal layer is disposed on the first interlayer insulating layer. The third metal layer includes a sense line. The sensing line comprises a trunk and an extension part. The trunk extends along a second direction. The extension portion extends in a first direction. The extension portion is provided corresponding to the scan line. The second interlayer insulating layer is arranged on the third metal layer. The first conductive layer is disposed on the second interlayer insulating layer. The third interlayer insulating layer is arranged on the first conductive layer. The second conductive layer is disposed on the third interlayer insulating layer.
In the pixel structure according to the embodiment of the invention, the pixel structure further comprises a flat layer. The flat layer is disposed between the first interlayer insulating layer and the second interlayer insulating layer. The third metal layer is disposed on the planarization layer.
In the pixel structure according to the embodiment of the present invention, the pixel structure is applied to a display panel of a triple gate design.
In the pixel structure according to the embodiment of the invention, the second conductive layer includes a slit.
According to an embodiment of the present invention, a pixel structure of the present invention includes a scan line, a data line, an active device, a sensing line, a pixel electrode, and a common electrode. The scan lines extend in a first direction. The data line extends in a second direction. The active components are electrically connected with the corresponding scanning lines and the corresponding data lines. The sensing line comprises a trunk and an extension part. The trunk extends along a second direction. The extension portion extends in a first direction. The extension portion is provided corresponding to the scan line. The pixel electrode is electrically connected with the active component. The shared electrode is electrically connected with the sensing line. The pixel structure of the invention is applied to a display panel with a three-grid design.
In the pixel structure according to the embodiment of the invention, the data line and the sensing line are the same metal layer.
In the pixel structure according to the embodiment of the invention, the data line and the sensing line are different metal layers.
The pixel structure of the invention enables the extending part of the sensing line to be correspondingly arranged with the scanning line, and the pixel structure can be used for shielding the light leakage phenomenon of the scanning line, thereby being unnecessary to arrange an additional black matrix above the scanning line and increasing the aperture opening ratio of the pixel structure.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
Fig. 1A is a schematic top view of a pixel structure according to an embodiment of the invention.
FIG. 1B is a cross-sectional view of the cross-section line A-A' of FIG. 1A.
Fig. 2A is a schematic top view of a pixel structure according to another embodiment of the invention.
FIG. 2B is a cross-sectional view of an embodiment according to section line B-B' of FIG. 2A.
FIG. 2C is a cross-sectional view of another embodiment according to section line B-B' of FIG. 2A.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. The present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numbers refer to the same or similar components, and the following paragraphs will not be repeated. In addition, directional terms mentioned in the embodiments, for example: up, down, left, right, front or rear, etc., are simply directions with reference to the drawings. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting.
Fig. 1A is a schematic top view of a pixel structure according to an embodiment of the invention, and fig. 1B is a schematic cross-sectional view taken along a sectional line a-a' of fig. 1A.
Referring to fig. 1A and fig. 1B, in the present embodiment, the pixel structure 10 is a triple-gate pixel structure. In detail, the pixel structure 10 of the present embodiment drives one pixel unit through three scan lines (or gate lines). The display panel using the pixel structure of the triple gate type includes three times as many scanning lines and one third of data lines at the same resolution as the common display panel using the pixel structure of the single gate type. In this case, since the cost and power consumption of the gate driving chip electrically connected to the scan line are lower than those of the source driving chip electrically connected to the data line, the cost and power consumption of the display panel using the triple-gate pixel structure can be reduced.
In one embodiment, the pixel structure 10 includes a scan line SL, a data line DL, an active device T, a sensing line Sx, a pixel electrode PE, and a common electrode CE. In addition, the pixel structure 10 may further include a substrate 100, a gate insulating layer GI, and interlayer insulating layers PV1, PV 3.
For convenience of illustration, only a partial region of the pixel structure 10 is shown in fig. 1A, and a person skilled in the art can understand the structure or layout of the pixel structure 10 according to the following embodiments.
The substrate 100 may be, for example, a rigid substrate or a flexible substrate. For example, the material of the substrate 100 may be, for example, glass, quartz, or an organic polymer, or the material of the substrate 100 may be, for example, polyimide, polyethylene naphthalate, polyethylene terephthalate, polycarbonate polyethersulfone, or polyarylate. In one embodiment, the scan line SL, the data line DL, the active device T, the sensing line Sx, the pixel electrode PE, and the common electrode CE are disposed on the substrate 100.
For example, the scan lines SL substantially extend along the first direction E1 and are arranged along the second direction E2, and the data lines DL substantially extend along the second direction E2 and are arranged along the first direction E1, but the invention is not limited thereto. In one embodiment, the first direction E1 is substantially perpendicular to the second direction E2. In the present embodiment, the scan lines SL are zigzag, and the data lines DL are straight, but the invention is not limited thereto. In other embodiments, the scan lines SL may be linear or have other shapes, and the data lines DL may also be zigzag or have other shapes. The scan lines SL and the data lines DL generally include a metal material in consideration of conductivity, but the present invention is not limited thereto. In other embodiments, other conductive materials can be used for the scan lines SL and the data lines DL, such as: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or stacked layers of a metal material and other conductive materials.
The active device T is electrically connected to the scan line SL and the data line DL, for example. In the present embodiment, the active device T is a bottom gate thin film transistor, but the invention is not limited thereto. The active device T may also be a top gate type thin film transistor or other type of active device.
The active device T includes, for example, a gate G electrically connected to the scan line SL, a source S electrically connected to the data line DL, and a drain D. The materials of the active component T may include (but are not limited to): metal materials, alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials. In one embodiment, the scan line SL and the gate G of the active device T are formed by the same layer of the first metal layer M1, and the data line DL and the source S and the drain D of the active device T are formed by another layer of the second metal layer M2.
The gate G is disposed on the substrate 100, for example. The gate insulating layer GI is disposed on the first metal layer M1 and may cover the gate G, for example. In an embodiment, the material of the gate insulating layer GI may be an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof), an organic material (such as polyimide-based resin, epoxy-based resin, acrylic-based resin, or a combination thereof), or a combination thereof, but the invention is not limited thereto. The gate insulating layer GI may have a single-layer structure, but the invention is not limited thereto. In other embodiments, the gate insulating layer GI may also be a multilayer structure.
The active component T may for example further comprise a semiconductor layer SE. The semiconductor layer SE is provided on the gate insulating layer GI, for example (not shown). The material of the semiconductor layer SE may be amorphous silicon, but the invention is not limited thereto. The material of the semiconductor layer SE may also be polycrystalline silicon, microcrystalline silicon, monocrystalline silicon, nanocrystalline silicon or other semiconductor materials or metal oxide semiconductor materials with different lattice arrangements. In one embodiment, the semiconductor layer SE is disposed corresponding to the gate electrode G. The source S and the drain D are also disposed on the gate insulating layer GI, and are electrically connected to the semiconductor layer SE.
The interlayer insulating layer PV1 is disposed on the second metal layer M2 and may cover the source S and the drain D, for example. In the embodiment, the material of the interlayer insulating layer PV1 may be an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof), an organic material (such as polyimide-based resin, epoxy-based resin, acrylic-based resin, or a combination thereof), or a combination thereof, but the invention is not limited thereto. The interlayer insulating layer PV1 may have a single-layer structure, but the present invention is not limited thereto. In other embodiments, the interlayer insulating layer PV1 may also be a multi-layer structure.
The pixel electrode PE and the common electrode CE are disposed on the interlayer insulating layer PV1, for example. In the embodiment, the pixel electrode PE is disposed above the common electrode CE, and the interlayer insulating layer PV3 is sandwiched between the pixel electrode PE and the common electrode CE, but the invention is not limited thereto. That is, the common electrode CE may also be disposed above the pixel electrode PE. The interlayer insulating layer PV3 has similar materials and structures as the interlayer insulating layer PV1, and thus will not be described herein. The pixel electrode PE is electrically connected to the drain D of the active device T, for example, through the contact window H. The materials of the pixel electrode PE and the common electrode CE may include metal oxide conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable oxides, or stacked layers of at least two of the foregoing. The pixel electrode PE and the common electrode CE may optionally have a slit, but the invention is not limited thereto. In the present embodiment, the pixel electrode PE has a slit PE _ S.
The sensing line Sx is electrically connected to the shared electrode CE, for example. In the embodiment, the sensing line Sx is a part of the second metal layer M2, but the invention is not limited thereto. The sensing line Sx includes a stem Sx1 and an extension Sx2, for example. The stem Sx1 of the sensing line Sx substantially extends along the second direction E2, and the extension Sx2 of the sensing line Sx substantially extends along the first direction E1. In one embodiment, the extension portion Sx2 of the sensing line Sx is disposed corresponding to the scan line SL. That is, the extension portion Sx2 of the sensing line Sx is disposed above the scan line SL and substantially overlaps the scan line SL.
In the present embodiment, the extension portion Sx2 of the sensing line Sx is disposed corresponding to the scan line SL, so as to change the control strength of the electric field and further avoid the light leakage phenomenon at the boundary of the scan line SL, thereby reducing the critical dimension loss (CD loss) of the black matrix and increasing the aperture ratio of the pixel structure 10.
Fig. 2A is a schematic top view of a pixel structure according to another embodiment of the invention, and fig. 2B is a schematic cross-sectional view of an embodiment according to a cross-sectional line B-B' of fig. 2A. It should be noted that fig. 2A is along with the component numbers and partial contents of fig. 1A, fig. 2B is along with the component numbers and partial contents of fig. 1B, wherein the same or similar reference numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
Referring to fig. 2A and fig. 2B, the main difference between the pixel structure 20 of the present embodiment and the pixel structure 10 of the previous embodiment is: the sensing line Sx is not a part of the second metal layer M2, but is a part of the third metal layer M3. In the present embodiment, the sensing line Sx is disposed on the interlayer insulating layer PV1 and covered by the interlayer insulating layer PV 2.
In the present embodiment, the extension portion Sx2 of the sensing line Sx is disposed corresponding to the scan line SL, so as to change the control strength of the electric field and further avoid the light leakage phenomenon at the boundary of the scan line SL, thereby reducing the critical dimension loss (CD loss) of the black matrix and increasing the aperture ratio of the pixel structure 20.
FIG. 2C is a cross-sectional view of another embodiment according to section line B-B' of FIG. 2A. It should be noted that fig. 2C follows the reference numerals and parts of the components in fig. 2B, wherein the same or similar reference numerals are used to indicate the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
Referring to fig. 2A and fig. 2C, the main difference between the pixel structure 30 of the present embodiment and the pixel structure 20 of the previous embodiment is: a planarization layer OC is disposed between the third metal layer M3 and the second metal layer M2, that is, between the sensing line Sx and the data line DL. In the present embodiment, the planarization layer OC is interposed between the interlayer insulating layer PV1 and the interlayer insulating layer PV 2. The flat layer OC is disposed such that the sensing line Sx and the data line DL can reduce electrical interference therebetween even if they are partially overlapped.
In the present embodiment, the extension portion Sx2 of the sensing line Sx is disposed corresponding to the scan line SL, so as to change the control strength of the electric field and further avoid the light leakage phenomenon at the boundary of the scan line SL, thereby reducing the critical dimension loss (CD loss) of the black matrix and increasing the aperture ratio of the pixel structure 30.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A pixel structure, comprising:
the first metal layer comprises a grid electrode and a scanning line, wherein the scanning line extends along a first direction;
the gate insulating layer is arranged on the first metal layer;
the second metal layer is arranged on the gate insulating layer and comprises a source electrode, a drain electrode, a data line and a sensing line, wherein the data line extends along a second direction, and the sensing line comprises:
a trunk extending in the second direction; and
an extension part extending in the first direction, wherein the extension part is disposed corresponding to the scan line;
a first interlayer insulating layer disposed on the second metal layer;
a first conductive layer disposed on the first interlayer insulating layer;
a second interlayer insulating layer disposed on the first conductive layer; and
and a second conductive layer disposed on the second interlayer insulating layer.
2. The pixel structure of claim 1, wherein the pixel structure is applied to a display panel of a tri-gate design.
3. The pixel structure of claim 1, wherein the second conductive layer comprises a slit.
4. A pixel structure, comprising:
the first metal layer comprises a grid electrode and a scanning line, wherein the scanning line extends along a first direction;
the gate insulating layer is arranged on the first metal layer;
the second metal layer is arranged on the gate insulating layer and comprises a source electrode, a drain electrode and a data line, wherein the data line extends along a second direction;
a first interlayer insulating layer disposed on the second metal layer;
a third metal layer disposed on the first interlayer insulating layer and including a sensing line, wherein the sensing line includes:
a trunk extending in the second direction; and
an extension part extending in the first direction, wherein the extension part is disposed corresponding to the scan line;
a second interlayer insulating layer disposed on the third metal layer;
a first conductive layer disposed on the second interlayer insulating layer;
a third interlayer insulating layer disposed on the first conductive layer; and
and a second conductive layer disposed on the third interlayer insulating layer.
5. The pixel structure of claim 4, further comprising a planarization layer disposed between the first and second interlayer insulating layers, and the third metal layer is disposed on the planarization layer.
6. The pixel structure of claim 4, wherein the pixel structure is applied to a display panel of a tri-gate design.
7. The pixel structure of claim 4, wherein the second conductive layer comprises a slit.
8. A pixel structure, comprising:
the scanning line and the data line, wherein the scanning line extends along a first direction, and the data line extends along a second direction;
the active components are electrically connected with the corresponding scanning lines and the corresponding data lines;
a sense line, comprising:
a trunk extending in the second direction; and
an extension part extending in the first direction, wherein the extension part is disposed corresponding to the scan line;
a pixel electrode, wherein the pixel electrode is electrically connected with the active component; and
a common electrode, wherein the common electrode is electrically connected with the sensing line,
the pixel structure is applied to a display panel with a three-grid design.
9. The pixel structure of claim 8, wherein the data line and the sense line are the same metal layer.
10. The pixel structure of claim 8, wherein the data line and the sense line are different metal layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910603382.XA CN112185248A (en) | 2019-07-05 | 2019-07-05 | Pixel structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910603382.XA CN112185248A (en) | 2019-07-05 | 2019-07-05 | Pixel structure |
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| CN112185248A true CN112185248A (en) | 2021-01-05 |
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| US20090191652A1 (en) * | 2008-01-25 | 2009-07-30 | Au Optronics Corp. | Pixel structure and method for manufacturing the same |
| CN104022150A (en) * | 2014-02-20 | 2014-09-03 | 友达光电股份有限公司 | Thin film transistor and pixel structure |
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