CN112180239A - Method for detecting reliability problem of input end and output end of integrated circuit - Google Patents
Method for detecting reliability problem of input end and output end of integrated circuit Download PDFInfo
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- CN112180239A CN112180239A CN202011035786.2A CN202011035786A CN112180239A CN 112180239 A CN112180239 A CN 112180239A CN 202011035786 A CN202011035786 A CN 202011035786A CN 112180239 A CN112180239 A CN 112180239A
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- integrated circuit
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- electric leakage
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
- G01R31/68—Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
Abstract
The invention relates to the technical field of integrated circuit detection, in particular to a method for detecting the reliability of an input/output port of an integrated circuit, aiming at solving the problems that in the prior art, because a parasitic field tube and a parasitic triode have electric leakage and an ESD protection mechanism formed by a parasitic device cannot be detected, the technical key points are as follows: comprises the following steps: the method comprises the following steps: detecting and positioning the input port leakage caused by the parasitic field tube; step two: detecting and positioning the output port electric leakage caused by the parasitic triode; step three: the parasitic device is used for detecting the ESD protection effect. The method for detecting the reliability problem of the input end and the output end of the integrated circuit can effectively position the positions of the input end and the output end with electric leakage, obtain the reason of the electric leakage, effectively play the role of an ESD protection structure formed by parasitic devices and effectively discharge static electricity.
Description
Technical Field
The invention relates to the technical field of integrated circuit detection, in particular to a method for detecting the reliability problem of an input end and an output end of an integrated circuit.
Background
Each integrated circuit can be generally divided into two parts, i/o port (IO PIN) and chip core, wherein the i/o port is used as a part for exchanging signals between the core logic and the outside of the integrated circuit, and the reliability of the i/o port is very important. The input pin of each integrated circuit corresponds to a pressure welding point in the chip. Besides some structures required by the input port to realize normal functions, such as a driving unit, a buffer unit, etc., there are generally two structures: (1) a pull-down structure is usually connected to each pad to allow the input to have a stable state when the input signal is suspended. (2) There is an ESD (electrostatic discharge) ESD protection structure on each bonding pad. ESD is one of the most important reliability problems in current MOS integrated circuits, because such devices are sensitive to static electricity, and may fail due to electrostatic electric fields and electrostatic discharge currents, or cause "soft breakdown" phenomena that are difficult to be found by people, which may cause device locking, resetting, data loss, and unreliability to affect normal operation of the device, reduce reliability of the device, or even cause damage to the device. In order to avoid the damage of the integrated circuit caused by static electricity, a related circuit module called an ESD protection structure must be designed in the circuit, and the protection structure is used for avoiding the damage of an operating circuit module in the integrated circuit caused by an ESD discharge path, and ensuring that ESD generated between any two chip pins has a proper low-resistance bypass to introduce ESD current into a power line.
Since all components in an integrated circuit are fabricated on the same substrate, various parasitic effects inevitably exist, which are reflected in the generation of some parasitic devices in addition to the above-mentioned normal devices. Therefore, the pull-up and pull-down structure and the ESD protection structure in the input structure may be specially designed, or may be formed by parasitic devices, which easily cause a leakage phenomenon, causing the input/output port to fail to operate normally, and also causing an increase in power consumption of the whole chip. The technical problems that a parasitic field tube and a parasitic triode have electric leakage and an ESD protection mechanism formed by a parasitic device cannot detect exist in the prior art.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defects that the parasitic field tube and the parasitic triode have electric leakage and the ESD protection mechanism formed by the parasitic device cannot be detected in the prior art, so as to provide a method for detecting the reliability of the input/output port of the integrated circuit.
The technical purpose of the invention is realized by the following technical scheme:
a method for detecting the reliability problem of an input end and an output end of an integrated circuit comprises the following steps:
the method comprises the following steps: detecting and positioning the input port leakage caused by the parasitic field tube;
step two: detecting and positioning the output port electric leakage caused by the parasitic triode;
step three: the parasitic device is used for detecting the ESD protection effect.
Preferably, the step one comprises the following steps:
s1: disconnecting the integrated circuit input port structure to be tested from the external application circuit,
s2: connecting a pull-up resistor at the disconnected position, and measuring the magnitude of leakage current by adjusting the working voltage so as to find out the relation between the leakage current and the working voltage and judge the working voltage value causing the leakage current;
s3: and positioning the electric leakage area in the chip, and finding the electric leakage position of the parasitic field tube according to the electric leakage area.
Preferably, the second step comprises the following steps:
s1: the positive power supply end is increased by 5V, and the negative power supply end is increased by-30V;
s2: and standing for a period of time, and adding-30V voltage to measure the leakage current of the output pin when the output end of the circuit is in a low-frequency state, wherein if the test result exceeds the test specification, the output end has the leakage problem.
Preferably, the step three comprises the following steps: an ESD strike experiment was performed for each pin of the integrated circuit.
Preferably, in the third step, an ESD strike experiment is performed on each pin of the integrated circuit by using a human body model test standard.
The method for detecting the reliability problem of the input end and the output end of the integrated circuit can effectively position the positions of the input end and the output end with electric leakage, obtain the reason of the electric leakage, effectively play the role of an ESD protection structure formed by parasitic devices and effectively discharge static electricity.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below according to embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
A method for detecting reliability problems of input and output ports of an integrated circuit comprises the following steps:
the method comprises the following steps: and detecting and positioning the input port leakage caused by the parasitic field tube.
A typical input port structure of an integrated circuit has a parasitic field tube, which is usually caused by unreasonable layout design, that is, when an aluminum line crosses two adjacent N + doped regions, the aluminum line and a field oxide layer (SiO2) and the N + doped region form the parasitic field tube. Due to the reasons of process and design, a parasitic field tube is inevitably present in the chip, but the parasitic field tube does not necessarily have adverse effects on the chip, and only when the voltage applied on the aluminum wire is large enough to form a channel on the semiconductor surface below the field oxide layer, the parasitic field tube is turned on, so that current circulation is generated between the two doped regions, and circuit parameters are deteriorated or even a circuit fails. For the input structure, the port will leak current due to the conduction of the parasitic field tube.
Therefore, it is necessary to detect and locate the input port leakage caused by the field tube, and in particular, in an embodiment, the method includes the following steps:
s1: disconnecting the integrated circuit input port structure to be tested from the external application circuit,
s2: connecting a pull-up resistor at the disconnected position, and measuring the magnitude of leakage current by adjusting the working voltage so as to find out the relation between the leakage current and the working voltage and judge the working voltage value causing the leakage current;
s3: and positioning the electric leakage area in the chip, and finding the electric leakage position of the parasitic field tube according to the electric leakage area.
Specifically, a method for simultaneously measuring current for dividing and connecting the focused ion beams in different areas; and judging which region leaks electricity, and finding the position of the parasitic field tube by comparing the layout.
Step two: detecting and positioning the output port electric leakage caused by the parasitic triode;
the output port is provided with a pull-down resistor to a negative power supply (-30V), the pull-down resistor is arranged in an independent N well and is a P-type diffusion resistor, and the pull-down resistor and the P-substrate form a parasitic longitudinal PNP triode at the high-voltage output port together, wherein the potential of the P + diffusion resistor is lowest to form a collector of a parasitic PNP tube, the HV Nwell forms a base of the PNP tube, and the P-substrate forms an emitter of the PNP tube.
Parasitic devices in integrated circuits are ubiquitous and parasitic transistors do not necessarily have an adverse effect. According to the operating principle of the triode, the conduction condition of the triode is that an emitting junction is forward biased and a collecting junction is reverse biased. Both ends of the pull-down resistor are connected with negative voltage of minus 30V, namely the collector of the parasitic triode is connected with voltage of minus 30V, and the emitter is grounded to be 0V. Because the N trap is independent and is not connected with a fixed potential, the base electrode of the parasitic triode is suspended. When the base electrode is at a positive potential larger than 0V, the collector junctions of the emitter junctions are all reversely biased, and the parasitic triodes can be cut off. When the pressure welding point is added with a high voltage of minus 30V, the potential of the base electrode is negative by coupling the parasitic capacitor to the base electrode, and the parasitic triode can enter a conducting state as long as the differential pressure between the emitter electrode and the base electrode reaches a certain degree, so that a large leakage current is generated.
Therefore, in the detection process, the detection of the leakage of the output port caused by the parasitic triode is required. Specifically, in one embodiment, the detecting and positioning of the output port leakage caused by the parasitic triode includes the following steps:
s1: the positive power supply end is increased by 5V, and the negative power supply end is increased by-30V;
s2: and standing for a period of time, and adding-30V voltage to measure the leakage current of the output pin when the output end of the circuit is in a low-frequency state, wherein if the test result exceeds the test specification, the output end has the leakage problem.
Step three: the parasitic device is used for detecting the ESD protection effect.
The ESD protection structure has the highest ESD energy discharge capacity per unit area, low trigger voltage, high trigger speed and small occupied layout area.
Wherein, Q1 is a parasitic PNP transistor: the emitter region is composed of P + in the N trap, the N trap is the base region of the N trap, and the P-substrate is used as a collector; q2 is located in another parasitic NPN transistor: the N + outside the well is the emitter region, the P-substrate is its base region, and the N-well is the collector. The protection structure needs to be opened at 30-50V because the N well has a low doping concentration, so that a thin gate oxide NMOS transistor Q3 is needed as a second-stage protection circuit. To prevent the protection structure from being turned on during the CMOS normal operation of the IC, the Gate of Q3 is shorted to GND to ensure that the NMOS device is turned off. Before the ESD voltage does not rise to 30V, the ESD protection structure formed by the parasitic devices is closed, and the structure can be triggered to be turned on to discharge ESD current before the secondary protection circuit is not damaged by ESD. As soon as the ESD protection structure is turned on, its holding voltage will clamp the ESD voltage at a very low level, so that the internal circuit will not be disturbed and protected.
The method adopted in the third step is as follows: an ESD strike experiment was performed for each pin of the integrated circuit.
Specifically, an ESD striking experiment is carried out on each pin of the integrated circuit by adopting a human body model test standard HBMMIL-STD-883F (3.15.7), and the effect of the report structure is interpreted according to the ESD voltage which can be borne by one protection structure. The protection structure can bear 8KV of static electricity in the striking process.
The method for detecting the reliability problem of the input end and the output end of the integrated circuit can effectively position the positions of the input end and the output end with electric leakage, obtain the reason of the electric leakage, effectively play the role of an ESD protection structure formed by parasitic devices and effectively discharge static electricity.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (5)
1. A method for detecting the reliability problem of an input end and an output end of an integrated circuit is characterized in that: comprises the following steps:
the method comprises the following steps: detecting and positioning the input port leakage caused by the parasitic field tube;
step two: detecting and positioning the output port electric leakage caused by the parasitic triode;
step three: the parasitic device is used for detecting the ESD protection effect.
2. The method of claim 1, wherein the method comprises: the first step comprises the following steps:
s1: disconnecting the integrated circuit input port structure to be tested from the external application circuit,
s2: connecting a pull-up resistor at the disconnected position, and measuring the magnitude of leakage current by adjusting the working voltage so as to find out the relation between the leakage current and the working voltage and judge the working voltage value causing the leakage current;
s3: and positioning the electric leakage area in the chip, and finding the electric leakage position of the parasitic field tube according to the electric leakage area.
3. The method of claim 2, wherein the step of detecting the reliability problem of the input/output port of the integrated circuit comprises: the second step comprises the following steps:
s1: the positive power supply end is increased by 5V, and the negative power supply end is increased by-30V;
s2: and standing for a period of time, and adding-30V voltage to measure the leakage current of the output pin when the output end of the circuit is in a low-frequency state, wherein if the test result exceeds the test specification, the output end has the leakage problem.
4. The method of claim 3, wherein the step of detecting the reliability problem of the input/output port of the integrated circuit comprises: the third step comprises the following steps: an ESD strike experiment was performed for each pin of the integrated circuit.
5. The method of claim 4, wherein the step of detecting the reliability problem of the input/output port of the integrated circuit comprises: in the third step, an ESD striking experiment is carried out on each pin of the integrated circuit by adopting a human body model test standard.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113451167A (en) * | 2021-07-19 | 2021-09-28 | 捷捷半导体有限公司 | Packaging test method and device and electronic equipment |
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| US6838869B1 (en) * | 2001-04-02 | 2005-01-04 | Advanced Micro Devices, Inc. | Clocked based method and devices for measuring voltage-variable capacitances and other on-chip parameters |
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| CN113451167A (en) * | 2021-07-19 | 2021-09-28 | 捷捷半导体有限公司 | Packaging test method and device and electronic equipment |
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Inventor after: Ju Shuirong Inventor after: Xia Huaqiu Inventor after: Zhu Jianzhou Inventor after: Tan Yimin Inventor after: Lv Wensheng Inventor before: Ju Shuirong Inventor before: Xia Huaqiu Inventor before: Zhu Jianzhou Inventor before: Tan Yimin Inventor before: Lv Wensheng |
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Address after: No. 88, Zhongtong East Road, Shuofang street, Xinwu District, Wuxi City, Jiangsu Province Patentee after: Jiangsu Donghai Semiconductor Co.,Ltd. Address before: No. 88, Zhongtong East Road, Shuofang street, Xinwu District, Wuxi City, Jiangsu Province Patentee before: WUXI ROUM SEMICONDUCTOR TECHNOLOGY Co.,Ltd. |
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