CN112164693B - Three-dimensional memory device and method of manufacturing the same - Google Patents
Three-dimensional memory device and method of manufacturing the same Download PDFInfo
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- CN112164693B CN112164693B CN202011003643.3A CN202011003643A CN112164693B CN 112164693 B CN112164693 B CN 112164693B CN 202011003643 A CN202011003643 A CN 202011003643A CN 112164693 B CN112164693 B CN 112164693B
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Abstract
The invention provides a three-dimensional memory device and a method of manufacturing the same. Wherein the three-dimensional memory device includes: a memory device disposed on a first substrate; peripheral devices disposed on the second substrate; one or more interconnect layers formed between the memory device and the peripheral device; an isolation ring located at the periphery of the memory device; a peripheral contact hole disposed on the first substrate and located in the memory device; the filling material in the peripheral contact hole is in conductive connection with the filling material in the peripheral circuit contact hole in the peripheral device through the interconnection layer; a dummy peripheral contact hole disposed on the first substrate and between the isolation ring and the peripheral contact hole.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory device and a manufacturing method thereof.
Background
In practical application, when a layout design of a three-dimensional memory device is performed, in order to increase Electrostatic Discharge (ESD) protection strength of the three-dimensional memory device, an isolation Ring (SR, Seal Ring) (also may be referred to as a Seal Ring) is generally arranged around the three-dimensional memory device, a certain distance is provided between the SR and the three-dimensional memory device to effectively space edges of the three-dimensional memory device, and the SR mainly functions to prevent Electrostatic charge Discharge from damaging internal circuits of the three-dimensional memory device; and protecting the three-dimensional memory device from cutting stress and moisture intrusion when the three-dimensional memory device is cut.
In the related art, a method of manufacturing a three-dimensional memory device includes: forming a stacked memory device and peripheral devices, and an SR surrounding the memory device; the storage device is arranged on the front surface of the first wafer; the peripheral device is arranged on the front side of the second wafer; and forming an electrical lead-out structure on the back side of the first wafer so as to lead out the memory device and the part of the peripheral devices which needs to be connected with external devices (other devices connected with the three-dimensional memory) electrically. In forming the electrical lead-out structure, it is necessary to perform thinning processing on the back surface of the first wafer. However, when thinning is performed, the complete structure around the SR cannot be maintained, and the sealing environment is poor, so that the SR cannot protect the three-dimensional memory device well.
Disclosure of Invention
To solve the related technical problems, embodiments of the present invention provide a three-dimensional memory device and a method for manufacturing the same.
An embodiment of the present invention provides a three-dimensional memory device, including:
a memory device disposed on a first substrate;
peripheral devices disposed on the second substrate;
one or more interconnect layers formed between the memory device and the peripheral device;
an isolation ring located at the periphery of the memory device;
a peripheral contact hole disposed on the first substrate and located in the memory device; the filling material in the peripheral contact hole is in conductive connection with the filling material in the peripheral circuit contact hole in the peripheral device through the interconnection layer;
a dummy peripheral contact hole disposed on the first substrate and between the isolation ring and the peripheral contact hole.
In the scheme, at least one peripheral contact hole column is formed by a plurality of peripheral contact holes;
a plurality of said dummy peripheral contact holes forming at least one column of dummy peripheral contact holes; wherein the number of dummy peripheral contact holes included in one dummy peripheral contact hole column is the same as the number of peripheral contact holes included in one peripheral contact hole column.
In the above aspect, the dummy peripheral contact hole row is parallel to the peripheral contact hole row.
In the above solution, the dummy peripheral contact hole is located close to the isolation ring.
In the scheme, the peripheral contact hole is filled with a first material; the dummy peripheral contact hole is filled with a second material; wherein the first material is different from the second material, the second material having a dielectric constant lower than that of the first material.
An embodiment of the present invention further provides a method for manufacturing a three-dimensional memory device, including:
forming a memory device on a first substrate;
forming an isolation ring at the periphery of the memory device;
forming a peripheral device on a second substrate;
forming one or more interconnect layers between the memory device and the peripheral device;
wherein, in the process of forming the memory device, a peripheral contact hole is formed on the first substrate; the filling material in the peripheral contact hole is in conductive connection with the filling material in the peripheral circuit contact hole in the peripheral device through the interconnection layer; in the process of forming the peripheral contact hole, a dummy peripheral contact hole is formed on the first substrate and between the isolation ring and the peripheral contact hole.
In the scheme, a plurality of peripheral contact holes and a plurality of dummy peripheral contact holes are formed on the first substrate; wherein the plurality of peripheral contact holes form at least one peripheral contact hole column; the plurality of dummy peripheral contact holes form at least one dummy peripheral contact hole column; the number of dummy peripheral contact holes included in one dummy peripheral contact hole column is the same as the number of peripheral contact holes included in one peripheral contact hole column.
In the above aspect, the dummy peripheral contact hole row is parallel to the peripheral contact hole row.
In the above solution, the dummy peripheral contact hole is located between the isolation ring and the contact hole and near the isolation ring.
In the above scheme, the method further comprises:
forming a first barrier layer on the dummy peripheral contact hole;
filling a first material in the peripheral contact hole;
removing the first barrier layer;
forming a second barrier layer on the peripheral contact hole;
filling a second material in the dummy peripheral contact hole; wherein the first material is different from the second material, and the dielectric constant of the second material is lower than a preset dielectric constant;
and removing the second barrier layer.
The embodiment of the invention provides a three-dimensional memory device and a manufacturing method thereof.A memory device is formed on a first substrate; forming an SR at the periphery of the memory device; forming a peripheral device on a second substrate; forming one or more interconnect layers between the memory device and the peripheral device; wherein, in the process of forming the memory device, a first contact hole is formed on the first substrate; the filling material in the first contact hole is in conductive connection with the filling material in the peripheral circuit contact hole in the peripheral device through the interconnection layer; in the process of forming the first contact hole, a dummy peripheral circuit contact hole is formed on the first substrate and between the isolation ring and the first contact hole. In manufacturing the three-dimensional memory device in the embodiment of the invention, a peripheral contact hole for connecting a part, which is required to be connected with an external device, of a peripheral device to an electric lead-out structure and a dummy peripheral contact hole positioned between the SR and the peripheral contact hole are manufactured in the memory device. The formed dummy peripheral contact hole is not used for conducting connection, but used for relieving stress in the first substrate, so that damage does not occur around the SR when an electric leading-out structure is formed subsequently and the back surface of the first substrate is thinned, namely, the complete structure and the good closed environment can be kept around the SR, and the SR can play a good protection role in a three-dimensional memory device.
Drawings
FIG. 1 is a schematic cross-sectional view of a three-dimensional memory according to an embodiment of the invention;
FIG. 2 is a schematic view illustrating a process of thinning a back surface of a wafer according to an embodiment of the present invention;
FIG. 3a is a schematic diagram illustrating a breakage of a first wafer after a grinding step in the related art;
FIG. 3b is a schematic diagram illustrating a breakage of a first wafer after a wet etching step in the related art;
FIG. 4a is a schematic diagram illustrating a breakage in a first wafer observed by a scanning electron microscope in the related art;
FIG. 4b is a schematic diagram illustrating a breakage in the first wafer observed by a transmission electron microscope in the related art;
FIG. 5 is a schematic partial cross-sectional view of scribe lines in two adjacent chips according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating a quantitative relationship among locations of SR, peripheral conductive via and step structure in a chip according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating simulation analysis results of stress distribution in a first wafer according to an embodiment of the present invention;
FIG. 8 is a flow chart illustrating a method for fabricating a three-dimensional memory device according to an embodiment of the invention;
FIG. 9a is a schematic diagram illustrating a relationship between locations of a row of dummy peripheral vias between the SR and the peripheral vias according to an embodiment of the present invention;
fig. 9b is a schematic diagram illustrating a position correspondence relationship when two dummy peripheral conductive vias are added between the SR and the peripheral conductive vias according to an embodiment of the present invention;
fig. 10 is a graph illustrating a distribution curve of stress in the first substrate when different numbers of peripheral conductive holes are formed according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the following will describe specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.
The manufacture method of the three-dimensional memory mainly comprises the following steps: forming a storage array on the front surface of the first wafer; forming a Complementary Metal-Oxide-Semiconductor (CMOS) peripheral circuit on the front surface of the second wafer; forming a first metal interconnection layer on the memory array, and forming a second metal interconnection layer on the peripheral circuit; bonding the front surface of the first wafer and the front surface of the second wafer; after that, an electrical lead-out structure (hereinafter, the process of forming the electrical lead-out structure is referred to as a Pad-out process) is formed on the back side of the first wafer to electrically lead out portions of the memory array and the CMOS peripheral circuits, which need to be connected to external devices. The process of forming the electrical lead-out structure includes: forming a through silicon via (TSC) on the back of the first wafer; a wiring layer (also referred to as a bottom top metal layer (BTM)) is again formed on the through silicon via, optionally creating a PAD out (PAD) on the rewiring layer. When the part needing to be connected with the external device is electrically connected to the through silicon via, the electrical leading-out can be realized.
In practical applications, a cross-sectional view of a three-dimensional memory is shown in fig. 1, a memory array and a CMOS peripheral circuit are stacked by bonding, the memory array is located above the CMOS peripheral circuit, and an electrical lead-out structure (not shown in fig. 1) is formed on a back surface of a first wafer (shown in fig. 1 by a dashed line frame).
In practical applications, forming the memory array on the first wafer may include the step-like stacked structure, the Channel Holes (CH), and the like shown in fig. 1, and the metal layers M1-M2, the dielectric layers V0-V1, and the like in fig. 1; forming CMOS peripheral circuits on the second wafer may include the transistors shown in fig. 1 and their control circuits, etc., as well as the contact regions TAC, the metal layers M2-M3, the dielectric layer V2, etc., in fig. 1.
In practical application, the first wafer and the second wafer can form a wafer stacking structure through bonding, and the back of the first wafer can be thinned after bonding, so that the subsequent difficulty in forming a through silicon via (TSC) is simplified. Here, the back surface of the first wafer may be thinned using a Grinding (expressed as Grinding in english) + Wet etching (expressed as Wet Etch in english) + Chemical Mechanical Polishing (CMP) process as shown in fig. 2. As can be seen from fig. 2, in one particular embodiment, the first wafer comprises a silicon substrate and an epitaxial layer (EPI), and after the grinding step is performed, the thickness of the first substrate is thinned (leaving a small amount of silicon substrate and the entire EMP); after the wet etching step, the thickness of the first substrate is further thinned (remaining part of the EMP); after the CMP step, the thickness of the first substrate reaches the target thickness (remaining thinner EMP).
However, after grinding and wet etching are sequentially performed on the back surface of the first wafer, a large number of damages are formed in the vicinity of the alignment (OVerLay) mark of SR and scribe line.
The inventor further traces the process of thinning and finds that: the defects are caused by grinding at the interface of the epitaxial layer and the base material of the silicon substrate region and are amplified by wet etching. Specifically, after the grinding step is performed, as shown in fig. 3a, in the direction along the thickness of the first wafer, breakage occurs in the vicinity of the interface between the silicon substrate and the epitaxial layer, while in the radial direction of the first wafer, breakage occurs in the vicinity of the SR and in the vicinity of the OVL mark of the scribe line; and the size of the breakage occurring after the grinding step is performed is small. After the wet etching step is performed, as shown in fig. 3b, in the direction along the thickness of the first wafer, the damage occurs near the interface between the silicon substrate and the epitaxial layer, and in the radial direction of the first wafer, the damage occurs near the SR and near the OVL mark of the scribe line; and the size of the breakage after the wet etching step is performed is further enlarged.
In practical applications, the damage observed by a Scanning Electron Microscope (SEM) is shown in fig. 4 a; the damage observed by a Transmission Electron Microscope (TEM) is shown in fig. 4 b. As can be seen from fig. 4b, the larger size of the damage may cause the SR to have an incomplete surrounding structure, and the closed environment may be degraded, so that the SR may not provide a good protection effect for the three-dimensional memory device.
In practical applications, the occurrence of breakage is often closely related to the distribution of stress, and based on this, the inventors have conducted simulation analysis on the distribution of stress in the first wafer. To show the simulation analysis results more clearly, the position distribution of the relevant structures in the first wafer is described.
Fig. 5 shows a schematic partial cross-sectional view at the scribe line in two adjacent chips. As shown in fig. 5, located beside the Step structure (SS, stable Step) and near the chip edge side (at the position shown by the dotted line in fig. 5), is a peripheral Contact hole, in which a filling material (also referred to as a connecting line or a plug) is conductively connected with a filling material in a peripheral circuit Contact hole (also referred to as a peripheral Contact, or simply referred to as PC1) in the CMOS peripheral circuit through the action of the first interconnection layer and the second interconnection layer, and the peripheral Contact hole and the PC1 are used together to lead out a portion to be electrically led out in the CMOS peripheral circuit to the first wafer, and then the electrical lead-out is realized by using an electrical lead-out structure provided in the first wafer. Note that the peripheral contact hole is a contact hole located in the memory device (as shown in fig. 1), and the PC1 is a contact hole located in the CMOS peripheral circuit (as shown in fig. 1), and the plug in the PC1 is conductively connected to the plug in the peripheral circuit contact hole through the interconnect layer.
In practice, the peripheral contact holes may comprise a plurality of columns, and 2 peripheral contact hole columns are included in each of the two chips shown in fig. 5.
The side of the peripheral contact hole close to the chip edge is SR. It should be noted that the SR encloses the devices in the whole chip, and forms a good closed structure along the thickness direction of the first wafer. In practical application, the sealing ring comprises a metal ring, the metal ring is composed of a plurality of metal layers, and each two adjacent metal layers are connected through a conductive guide hole, so that an electrostatic discharge path is formed. The SR of each of two adjacent chips is shown in fig. 5, and each SR contains 2 metal rings.
Between the SRs of two adjacent chips is the OVL mark of the scribe lane.
The quantitative relationship between the locations of SR (including 2 metal rings, SR-1 and SR-2), peripheral contact holes (including 2 columns of peripheral contact holes), and SS in a chip is shown in FIG. 6.
The results of the simulation analysis of the stress distribution in the first wafer, in which the pressure corresponding to the SR end is highest and the regional pressure difference (the difference between the maximum pressure value and the minimum pressure value) around the SR is large, are shown in fig. 7. The result is highly matched with the region where the breakage occurs.
Based on this discovery, dummy peripheral contact holes may be added alongside the SR to relieve stress in the first wafer. In the actual manufacturing process, the dummy peripheral contact hole and the peripheral contact circuit only have different functions, the manufacturing process of the dummy peripheral contact hole and the manufacturing process of the peripheral contact circuit are completely the same, and the structures are completely consistent, so that extra manufacturing processes are not added in a mode of relieving stress by adding the dummy peripheral contact hole, and the realization is convenient. In addition, while the stress is relieved, the process window of the thinning processing process performed on the back surface of the first wafer is increased, and the yield of the three-dimensional memory device is improved under the condition of no damage.
It should be noted that when the dummy peripheral contact hole is disposed beside the SR and close to the edge side of the three-dimensional memory device (i.e., between the SRs of two adjacent three-dimensional memory devices or in the scribe groove), the dummy peripheral contact hole in the scribe groove may be damaged due to the uncertainty of the scribing operation, and the dummy peripheral contact hole is disposed beside the SR and close to the center side of the three-dimensional memory device (i.e., between the SR and the peripheral contact hole), so that the dummy peripheral contact hole is disposed between the SR and the peripheral contact circuit in the embodiment of the present invention.
Based on this, in manufacturing the three-dimensional memory device in the embodiments of the present invention, both a peripheral contact hole for connecting a portion of a peripheral device, which is required to be connected to an external device, to an electrical lead-out structure and a dummy peripheral contact hole between the SR and the peripheral contact hole are manufactured in the memory device. The formed dummy peripheral contact hole is not used for conducting connection, but used for relieving stress in the first substrate, so that damage does not occur around the SR when an electric leading-out structure is formed subsequently and the back surface of the first substrate is thinned, namely, the complete structure and the good closed environment can be kept around the SR, and the SR can play a good protection role in a three-dimensional memory device.
An embodiment of the invention provides a method for manufacturing a three-dimensional memory device, and fig. 8 is a flow chart illustrating a method for manufacturing a three-dimensional memory device according to the invention. As shown in fig. 8, the method comprises the steps of:
step 801: forming a memory device on a first substrate;
step 802: forming an isolation ring at the periphery of the memory device;
step 803: forming a peripheral device on a second substrate;
step 804: forming one or more interconnect layers between the memory device and the peripheral device; wherein, in the process of forming the memory device, a peripheral contact hole is formed on the first substrate; the filling material in the peripheral contact hole is in conductive connection with the filling material in the peripheral circuit contact hole in the peripheral device through the interconnection layer; in the process of forming the peripheral contact hole, a dummy peripheral contact hole is formed on the first substrate and between the isolation ring and the peripheral contact hole.
Here, the first substrate may include the aforementioned first wafer; the second substrate may comprise the second wafer described above. In practice, in some embodiments, the memory devices may be formed on the front side of the first substrate and the peripheral devices may be formed on the front side of the second substrate.
In practical application, the memory device is a memory array of a three-dimensional memory device, and the peripheral device is a peripheral circuit of the three-dimensional memory device. The memory array may include a plurality of memory cells, each of which may include a transistor and a storage capacitor, and is mainly used for a storage function of the three-dimensional memory device. The peripheral circuit may include a plurality of transistors and a logic control circuit formed by the transistors, and the transistors may be CMOS transistors for controlling on and off of the peripheral device.
In some embodiments, the process of forming the memory device may include: forming a stacked structure on the front side of the first substrate; forming a channel hole in the stacked structure; generating a step structure on at least one side of the stacked structure; replacing materials of the dielectric layers in the stacked structure to form a grid; and forming a gate contact hole and a peripheral contact hole.
In some embodiments, the process of forming the peripheral device may include: forming a plurality of transistors and a logic control circuit formed by the transistors; and forming a peripheral circuit contact hole.
It should be noted that, in the embodiment of the present invention, the order of forming the memory device on the first substrate (step 801) and forming the peripheral device on the second substrate (step 803) is not limited, and the two steps may also be performed simultaneously.
As mentioned previously, it is desirable to locate the dummy peripheral contact between the SR and the peripheral contact. In practical application, the position of the dummy peripheral contact hole is arranged between the SR and the peripheral contact hole and does not interfere with the SR and the size of the peripheral contact hole.
In some embodiments, a plurality of peripheral contact holes and a plurality of dummy peripheral contact holes are formed on the first substrate; wherein the plurality of peripheral contact holes form at least one peripheral contact hole column; the plurality of dummy peripheral contact holes form at least one dummy peripheral contact hole column; the number of dummy peripheral contact holes included in one dummy peripheral contact hole column is the same as the number of peripheral contact holes included in one peripheral contact hole column.
In some embodiments, the column of dummy peripheral contact holes is parallel to the column of peripheral contact holes.
In some embodiments, the dummy peripheral contact hole is located between the isolation ring and the contact hole, and is proximate to the isolation ring. In practical applications, the peripheral contact hole may be located beside the step structure, and a plurality of peripheral contact hole columns are formed. The dummy peripheral contact holes may be disposed closer to the spacer ring, and the number of the dummy peripheral contact holes may include one or more columns, the dummy peripheral contact holes columns and the dummy peripheral contact holes.
Fig. 9a is an example of the positional correspondence when a column of dummy peripheral contact holes is added between the SR and the peripheral contact holes. In some embodiments, the peripheral contact hole row 1 is spaced apart from the SR-1 by a distance d, the thickness of one metal ring SR-1 of the SR is 0.01d, the distance between two metal rings SR-1 and SR-2 of the SR is 0.03d, the distance between the peripheral contact hole row 2 and the SR-1 is 1.3d, and the distance between the dummy peripheral contact hole row 1 and the SR-1 is 0.25 d.
Fig. 9b is an example of the positional correspondence when two columns of dummy peripheral contact holes are added between the SR and the peripheral contact holes. In some embodiments, the peripheral contact hole row 1 is spaced apart from the SR-1 by a distance d, the thickness of one metal ring SR-1 of the SR is 0.01d, the distance between two metal rings SR-1 and SR-2 of the SR is 0.03d, the distance between the peripheral contact hole row 2 and the SR-1 is 1.3d, the distance between the dummy peripheral contact hole row 1 and the SR-1 is 0.25d, and the distance between the dummy peripheral contact hole row 2 and the SR-1 is 0.2 d.
Fig. 10 shows the distribution of stress in the first substrate for two rows of peripheral contact holes, three rows of peripheral contact holes (i.e., two rows of peripheral contact holes + one row of dummy peripheral contact holes), and four rows of PC1 (two rows of peripheral contact holes + two rows of dummy peripheral contact holes). In the graph of FIG. 10, the abscissa corresponds to the position (where two peaks correspond to SR-1 and SR-2, respectively) in mm; the ordinate corresponds to the stress in MPa. As can be seen from fig. 10, after one and two columns of dummy peripheral contact holes are added, the maximum stress value is reduced, and the difference in stress is reduced significantly. That is, the addition of the dummy PC1 does act to relieve stress in the first substrate.
It should be noted that the distances between the peripheral contact hole column 1 shown in fig. 9a and the peripheral contact hole columns 1, 2 and SR shown in fig. 9b are exemplary, and are not intended to limit the specific positions of the dummy peripheral contact holes of the three-dimensional memory device in the present application. In other embodiments, the dummy peripheral contact hole row is disposed between the SR and the peripheral contact hole row without interfering with the SR and the peripheral contact hole row.
In practical applications, the number of columns of the dummy peripheral contact hole rows can be selected according to practical situations, and the more the columns are, the more the stress relieving effect is obvious, but the more the manufacturing process is complicated.
In practical applications, in order to realize the conductive connection through the peripheral contact hole, the peripheral contact hole is also filled with a conductive material (such as tungsten) to form a peripheral conductive plug. The dummy peripheral contact hole mainly used for relieving stress can be selected according to actual conditions. In particular, the amount of the solvent to be used,
in some embodiments, the fill material in the dummy peripheral contact holes may be the same as the fill material in the peripheral contact holes. At this time, the process of filling the dummy peripheral contact hole is completely the same as that of the peripheral contact hole, i.e., the dummy peripheral contact hole is filled without adding an additional process.
In other embodiments, the fill material in the dummy peripheral contact hole may be different from the fill material in the peripheral contact hole, and the dummy peripheral contact hole is filled with a material that is more effective in relieving stress, such as a material having a dielectric constant lower than a predetermined dielectric constant. Here, the preset dielectric constant may be adjusted according to actual conditions. In practical applications, the low dielectric constant material may include: fluorinated amorphous carbon (k < 2), carbon-doped amorphous glass (k < 2), porous silicon (k < 3), carbon-doped silica glass (k < 3), silsesquioxane (SSQ), Polytetrafluoroethylene (PTFE) (k 2.1), polyimide (k 3.4), and the like. At this time, there is a difference in the process of filling the dummy peripheral contact hole and the peripheral contact hole row, and an additional process is required, but the effect of relieving stress of the dummy peripheral contact hole is better.
Based on this, in an embodiment, the method further comprises:
forming a first barrier layer on the dummy peripheral contact hole;
filling a first material in the peripheral contact hole;
removing the first barrier layer;
forming a second barrier layer on the peripheral contact hole;
filling a second material in the dummy peripheral contact hole; wherein the first material is different from the second material, and the dielectric constant of the second material is lower than a preset dielectric constant;
and removing the second barrier layer.
Here, the first material is a material filled in the peripheral contact hole. In practice, the first material may comprise tungsten. The second material is a material filled in the dummy peripheral contact hole. In practice, the second material may comprise the aforementioned low dielectric constant material, and the dielectric constant of the second material is lower than that of the first material. The first barrier layer is used for protecting the dummy peripheral contact hole from being filled with the first material, and the second barrier layer is used for protecting the peripheral contact hole from being filled with the second material. In practical applications, the material of the first barrier layer and the second barrier layer may include photoresist.
After the location, number and special process requirements of the dummy peripheral contact holes are determined, the dummy peripheral contact holes can be manufactured according to a similar manufacturing method as the peripheral contact holes.
In practical applications, in one embodiment, the specific process of fabricating the peripheral contact holes and the dummy peripheral contact holes may include: forming a dielectric layer on corresponding areas of the peripheral contact hole to be formed and the dummy peripheral contact hole; forming a mask layer corresponding to the peripheral contact hole and the dummy peripheral contact hole on the dielectric layer; and at least etching the dielectric layer according to the mask layer to form a peripheral contact hole and a dummy peripheral contact hole. In practical application, the material of the dielectric layer may include tetraethyl orthosilicate (TEOS); the material of the mask layer may include a Photoresist (PR).
In practical applications, in an embodiment, the specific process of manufacturing the SR in the memory device in step 802 may include: forming a plurality of metal layers at corresponding positions where the SR is to be formed; and forming a conductive via hole between every two adjacent metal layers so as to connect the two adjacent metal layers. Here, two adjacent metal layers are connected to form an electrostatic discharge path.
In practical applications, one or more interconnection layers are formed between the memory device and the peripheral device, so that the interconnection layers are formed on the memory device and the peripheral device respectively, and then the two interconnection layers are conductively connected by bonding.
In practical applications, the bonding step may specifically include: the memory devices on the first substrate (which may be understood as the front side of the first wafer having been correspondingly surface processed) and the peripheral devices on the second substrate (which may be understood as the front side of the second wafer having been correspondingly surface processed) are aligned such that the conductive contacts on the front side of the first wafer are in contact with the conductive contacts on the front side of the second wafer. Subsequently, the conductive contacts of the two wafers are electrically connected together by heating, and the hydrogen ions and the oxygen ions of the non-metal regions of the two wafers are combined with each other, so that the non-metal regions of the first wafer and the second wafer are bonded together. Before the first wafer and the second wafer are contacted, the method further comprises the following steps: and cleaning and ion bombardment are carried out on the surfaces of the first wafer and the second wafer, so that the free hydrogen ions and oxygen ions on the surfaces of the wafers are increased, and the subsequent bonding is facilitated. Electrically connecting the conductive contacts of the two wafers together, comprising: and melting the metal parts of the conductive contacts of the first wafer and the second wafer by heating, and re-solidifying the metal parts into a whole after cooling.
In practical applications, an electrical lead-out structure is formed in a subsequent process, so that the PC1 is connected to an external device through the lead-out structure.
Based on this, in some embodiments, an electrical extraction structure is formed on the first substrate; and the middle part of the peripheral device is connected to the electric leading-out structure through the peripheral circuit contact hole and is connected with an external device through the electric leading-out structure.
Here, the external device refers to an external circuit, an external apparatus, an external system, or the like that the three-dimensional memory device needs to be connected to when used.
Wherein, in some embodiments, the forming of the electrical extraction structure on the first substrate comprises:
forming a through silicon via on the first substrate;
and forming a wiring layer on the silicon through hole.
In practical applications, the process of forming the electrical lead-out structure includes: forming a through silicon via on the back surface of the first substrate; forming a wiring layer on the through silicon via; optionally, a lead-out pad is generated on the rewiring layer. When the part needing to be connected with the external device is electrically connected to the through silicon via, the electrical leading-out can be realized. It is understood that in order to realize the conductive connection through the through silicon via, the through silicon via is further filled with a conductive material to form a through silicon conductive plug.
The manufacturing method of the three-dimensional memory device provided by the embodiment of the invention comprises the steps of forming a memory device on a first substrate; forming an SR at the periphery of the memory device; forming a peripheral device on a second substrate; forming one or more interconnect layers between the memory device and the peripheral device; wherein, in the process of forming the memory device, a first contact hole is formed on the first substrate; the filling material in the first contact hole is in conductive connection with the filling material in the peripheral circuit contact hole in the peripheral device through the interconnection layer; in the process of forming the first contact hole, a dummy peripheral circuit contact hole is formed on the first substrate and between the isolation ring and the first contact hole. In manufacturing the three-dimensional memory device in the embodiment of the invention, a peripheral contact hole for connecting a part, which is required to be connected with an external device, of a peripheral device to an electrical lead-out structure and a dummy peripheral circuit contact hole positioned between the SR and the peripheral contact hole are manufactured in the memory device. The formed dummy peripheral circuit contact hole is not used for conducting connection, but used for relieving stress in the first substrate, so that damage does not occur around the SR when an electric leading-out structure is formed subsequently and the back surface of the first substrate is thinned, namely, the complete structure and the good closed environment can be kept around the SR, and the SR can play a good protection role in a three-dimensional memory device.
Based on the above method for manufacturing a three-dimensional memory device, an embodiment of the present invention further provides a three-dimensional memory device, including:
a memory device disposed on a first substrate;
peripheral devices disposed on the second substrate;
one or more interconnect layers formed between the memory device and the peripheral device;
an isolation ring located at the periphery of the memory device;
a first peripheral contact hole disposed on the first substrate and located in the memory device; the filling material in the peripheral contact hole is in conductive connection with the filling material in the peripheral circuit contact hole in the peripheral device through the interconnection layer;
a dummy peripheral circuit contact hole disposed on the first substrate and between the isolation ring and the peripheral contact hole.
In one embodiment, the first contact hole includes a plurality; a plurality of said peripheral contact holes forming at least one peripheral contact hole column;
the dummy peripheral contact holes include a plurality; a plurality of dummy peripheral circuit contact holes forming at least one dummy peripheral contact hole column; wherein the number of dummy peripheral contact holes included in one dummy peripheral contact hole column is the same as the number of peripheral contact holes included in one peripheral contact hole column.
In an embodiment, the column of dummy peripheral contact holes is parallel to the column of peripheral contact holes.
In an embodiment, the dummy peripheral contact hole is located near the isolation ring.
In one embodiment, the peripheral contact hole is filled with a first material; the dummy peripheral contact hole is filled with a second material; wherein the first material is different from the second material, and the dielectric constant of the second material is lower than a preset dielectric constant.
The embodiment of the invention provides a three-dimensional memory device, which comprises a memory device arranged on a first substrate; peripheral devices disposed on the second substrate; one or more interconnect layers formed between the memory device and the peripheral device; an isolation ring located at the periphery of the memory device; a first peripheral contact hole disposed on the first substrate and located in the memory device; the filling material in the peripheral contact hole is in conductive connection with the filling material in the peripheral circuit contact hole in the peripheral device through the interconnection layer; a dummy peripheral circuit contact hole disposed on the first substrate and between the isolation ring and the peripheral contact hole. The three-dimensional memory device in the embodiment of the invention comprises a peripheral contact hole for connecting the part of the peripheral device, which needs to be connected with an external device, to an electric leading-out structure, and also comprises a dummy peripheral contact hole positioned between the SR and the peripheral contact hole. The formed dummy peripheral contact hole is not used for conducting connection, but used for relieving stress in the first substrate, so that when an electric leading-out structure is formed subsequently and the back surface of the first substrate is thinned, the periphery of the SR cannot be damaged, namely, the periphery of the SR can keep a complete structure and a good closed environment, and the SR can play a good protection role in a three-dimensional memory device.
It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (10)
1. A three-dimensional memory device, comprising:
a memory device disposed on a first substrate;
peripheral devices disposed on the second substrate;
one or more interconnect layers formed between the memory device and the peripheral device;
an isolation ring located at the periphery of the memory device;
a peripheral contact hole disposed on the first substrate and located in the memory device; the filling material in the peripheral contact hole is in conductive connection with the filling material in the peripheral circuit contact hole in the peripheral device through the interconnection layer;
a dummy peripheral contact hole disposed on the first substrate and between the isolation ring and the peripheral contact hole.
2. The three-dimensional memory device of claim 1, wherein a plurality of the peripheral contact holes form at least one peripheral contact hole column;
a plurality of said dummy peripheral contact holes forming at least one column of dummy peripheral contact holes; wherein the number of dummy peripheral contact holes included in one dummy peripheral contact hole column is the same as the number of peripheral contact holes included in one peripheral contact hole column.
3. The three-dimensional memory device of claim 2, wherein the column of dummy peripheral contact holes is parallel to the column of peripheral contact holes.
4. The three-dimensional memory device of claim 1, wherein the dummy peripheral contact hole is located proximate to the isolation ring.
5. The three-dimensional memory device according to claim 1, wherein the peripheral contact hole is filled with a first material; the dummy peripheral contact hole is filled with a second material; wherein the first material is different from the second material, and the dielectric constant of the second material is lower than a preset dielectric constant.
6. A method of fabricating a three-dimensional memory device, comprising:
forming a memory device on a first substrate;
forming an isolation ring at the periphery of the memory device;
forming a peripheral device on a second substrate;
forming one or more interconnect layers between the memory device and the peripheral device;
wherein, in the process of forming the memory device, a peripheral contact hole is formed on the first substrate; the filling material in the peripheral contact hole is in conductive connection with the filling material in the peripheral circuit contact hole in the peripheral device through the interconnection layer; in the process of forming the peripheral contact hole, a dummy peripheral contact hole is formed on the first substrate and between the isolation ring and the peripheral contact hole.
7. The method of claim 6, wherein a plurality of peripheral contact holes and a plurality of dummy peripheral contact holes are formed on the first substrate; wherein the plurality of peripheral contact holes form at least one peripheral contact hole column; the plurality of dummy peripheral contact holes form at least one dummy peripheral contact hole column; the number of dummy peripheral contact holes included in one dummy peripheral contact hole column is the same as the number of peripheral contact holes included in one peripheral contact hole column.
8. The method of claim 7, wherein the column of dummy peripheral contact holes is parallel to the column of peripheral contact holes.
9. The method of claim 6, wherein the dummy peripheral contact hole is located between the isolation ring and the contact hole and near the isolation ring.
10. The method of claim 6, further comprising:
forming a first barrier layer on the dummy peripheral contact hole;
filling a first material in the peripheral contact hole;
removing the first barrier layer;
forming a second barrier layer on the peripheral contact hole;
filling a second material in the dummy peripheral contact hole; wherein the first material is different from the second material, and the dielectric constant of the second material is lower than a preset dielectric constant;
and removing the second barrier layer.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290912A (en) * | 2007-04-19 | 2008-10-22 | 松下电器产业株式会社 | Semiconductor device and manufacturing method thereof |
| CN104009024A (en) * | 2013-02-26 | 2014-08-27 | 瑞萨电子株式会社 | Semiconductor device and semiconductor wafer |
| CN104752325A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof and method for improving cutting yield of wafer |
| US10115681B1 (en) * | 2018-03-22 | 2018-10-30 | Sandisk Technologies Llc | Compact three-dimensional memory device having a seal ring and methods of manufacturing the same |
| CN110970443A (en) * | 2018-10-01 | 2020-04-07 | 三星电子株式会社 | Semiconductor device with a plurality of transistors |
Family Cites Families (1)
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| CN106910746B (en) * | 2017-03-08 | 2018-06-19 | 长江存储科技有限责任公司 | A kind of 3D nand memories part and its manufacturing method, packaging method |
-
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- 2020-09-22 CN CN202111465280.XA patent/CN114446981A/en active Pending
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290912A (en) * | 2007-04-19 | 2008-10-22 | 松下电器产业株式会社 | Semiconductor device and manufacturing method thereof |
| CN104009024A (en) * | 2013-02-26 | 2014-08-27 | 瑞萨电子株式会社 | Semiconductor device and semiconductor wafer |
| CN104752325A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof and method for improving cutting yield of wafer |
| US10115681B1 (en) * | 2018-03-22 | 2018-10-30 | Sandisk Technologies Llc | Compact three-dimensional memory device having a seal ring and methods of manufacturing the same |
| CN110970443A (en) * | 2018-10-01 | 2020-04-07 | 三星电子株式会社 | Semiconductor device with a plurality of transistors |
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